Changes in v6:
- Fixed build with clang (thanks Nathan!)
- Removed unused mtk_rmw() macro in mtk-dvfsrc.c
- Added MODULE_DESCRIPTION() to mtk-dvfsrc-regulator.c
Changes in v5:
- Fixed Kconfig dependencies in interconnect
- Fixed module build for dvfsrc and interconnect
Changes in v4:
- Updated patch [3/7] to actually remove address/size cells
as the old version got unexpectedly pushed in v3.
Changes in v3:
- Removed examples from interconnect and regulator bindings
and kept example node with interconnect and regulator in
the main DVFSRC binding as suggested
- Removed 'reg' from interconnect and regulator, removed both
address and size cells from the main DVFSRC binding as that
was not really needed
- Added anyOf-required entries in the regulator binding as it
doesn't make sense to probe it without any regulator subnode
Changes in v2:
- Fixed issues with regulator binding about useless quotes and
wrong binding path (oops)
- Removed useless 'items' from DVFSRC main binding
- Allowed address/size cells to DVFSRC main binding to resolve
validation issues on the regulator and interconnect bindings
- Changed dvfsrc node name to `system-controller`, as the DVFSRC
is actually able to control multiple system components.
- Added a commit to remove mtk-dvfs-regulator.c before adding the
new, refactored regulator driver
This series adds support for the MediaTek Dynamic Voltage and Frequency
Scaling Resource Controller (DVFSRC), found on many MediaTek SoCs.
This hardware collects requests from both software and the various remote
processors embededd into the SoC, and decides about a minimum operating
voltage and a minimum DRAM frequency to fulfill those requests, in an
effort to provide the best achievable performance per watt.
Such hardware IP is capable of transparently performing direct register
R/W on all of the DVFSRC-controlled regulators and SoC bandwidth knobs.
Summarizing how the DVFSRC works for Interconnect:
ICC provider ICC Nodes
---- ----
_________ |CPU | |--- |VPU |
_____ | |----- ---- | ----
| |->| DRAM | ---- | ----
|DRAM |->|scheduler|----- |GPU | |--- |DISP|
| |->| (EMI) | ---- | ----
|_____|->|_________|---. ----- | ----
/|\ `-|MMSYS|--|--- |VDEC|
| ----- | ----
| | ----
| change DRAM freq |--- |VENC|
-------- | ----
SMC --> | DVFSRC | | ----
-------- |--- |IMG |
| ----
| ----
|--- |CAM |
----
...and for regulators, it's simply...
SMC -> DVFSRC -> Regulator voltage decider -> (vreg) Registers R/W
Please note that this series is based on an old (abandoned) series from
MediaTek [1], and reuses some parts of the code found in that.
Besides, included in this series, there's also a refactoring of the
mtk-dvfsrc-regulator driver, which never got compiled at all, and would
not build anyway because of missing headers and typos: that commit did
not get any Fixes tag because, well, backporting makes no sense at all
as the DVFSRC support - which is critical for that driver to work - is
introduced with *this series*! :-)
P.S.: The DVFSRC regulator is a requirement for the MediaTek UFSHCI
controller's crypto boost feature, which is already upstream but
lacking the actual regulator to work....... :-)
[1]: https://lore.kernel.org/all/[email protected]/
AngeloGioacchino Del Regno (7):
dt-bindings: regulator: Add bindings for MediaTek DVFSRC Regulators
dt-bindings: interconnect: Add MediaTek EMI Interconnect bindings
dt-bindings: soc: mediatek: Add DVFSRC bindings for MT8183 and MT8195
soc: mediatek: Add MediaTek DVFS Resource Collector (DVFSRC) driver
regulator: Remove mtk-dvfsrc-regulator.c
regulator: Add refactored mtk-dvfsrc-regulator driver
interconnect: mediatek: Add MediaTek MT8183/8195 EMI Interconnect
driver
.../interconnect/mediatek,mt8183-emi.yaml | 51 ++
.../mediatek,mt6873-dvfsrc-regulator.yaml | 43 ++
.../soc/mediatek/mediatek,mt8183-dvfsrc.yaml | 83 +++
drivers/interconnect/Kconfig | 1 +
drivers/interconnect/Makefile | 1 +
drivers/interconnect/mediatek/Kconfig | 29 +
drivers/interconnect/mediatek/Makefile | 5 +
drivers/interconnect/mediatek/icc-emi.c | 153 +++++
drivers/interconnect/mediatek/icc-emi.h | 40 ++
drivers/interconnect/mediatek/mt8183.c | 143 +++++
drivers/interconnect/mediatek/mt8195.c | 339 +++++++++++
drivers/regulator/mtk-dvfsrc-regulator.c | 248 ++++----
drivers/soc/mediatek/Kconfig | 11 +
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mtk-dvfsrc.c | 545 ++++++++++++++++++
.../interconnect/mediatek,mt8183.h | 23 +
.../interconnect/mediatek,mt8195.h | 44 ++
include/linux/soc/mediatek/dvfsrc.h | 36 ++
include/linux/soc/mediatek/mtk_sip_svc.h | 3 +
19 files changed, 1666 insertions(+), 133 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interconnect/mediatek,mt8183-emi.yaml
create mode 100644 Documentation/devicetree/bindings/regulator/mediatek,mt6873-dvfsrc-regulator.yaml
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml
create mode 100644 drivers/interconnect/mediatek/Kconfig
create mode 100644 drivers/interconnect/mediatek/Makefile
create mode 100644 drivers/interconnect/mediatek/icc-emi.c
create mode 100644 drivers/interconnect/mediatek/icc-emi.h
create mode 100644 drivers/interconnect/mediatek/mt8183.c
create mode 100644 drivers/interconnect/mediatek/mt8195.c
create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
create mode 100644 include/dt-bindings/interconnect/mediatek,mt8183.h
create mode 100644 include/dt-bindings/interconnect/mediatek,mt8195.h
create mode 100644 include/linux/soc/mediatek/dvfsrc.h
--
2.45.2
The Dynamic Voltage and Frequency Scaling Resource Collector Regulators
are controlled with votes to the DVFSRC hardware.
This adds support for the regulators found in MT6873, MT8183, MT8192
and MT8195 SoCs.
Reviewed-by: Rob Herring (Arm) <[email protected]>
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
.../mediatek,mt6873-dvfsrc-regulator.yaml | 43 +++++++++++++++++++
1 file changed, 43 insertions(+)
create mode 100644 Documentation/devicetree/bindings/regulator/mediatek,mt6873-dvfsrc-regulator.yaml
diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6873-dvfsrc-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6873-dvfsrc-regulator.yaml
new file mode 100644
index 000000000000..704828687970
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6873-dvfsrc-regulator.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/mediatek,mt6873-dvfsrc-regulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek DVFSRC-controlled Regulators
+
+description:
+ The Dynamic Voltage and Frequency Scaling Resource Collector Regulators
+ are controlled with votes to the DVFSRC hardware.
+
+maintainers:
+ - AngeloGioacchino Del Regno <[email protected]>
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt6873-dvfsrc-regulator
+ - mediatek,mt8183-dvfsrc-regulator
+ - mediatek,mt8192-dvfsrc-regulator
+ - mediatek,mt8195-dvfsrc-regulator
+
+ dvfsrc-vcore:
+ description: DVFSRC-controlled SoC Vcore regulator
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+
+ dvfsrc-vscp:
+ description: DVFSRC-controlled System Control Processor regulator
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+
+anyOf:
+ - required:
+ - dvfsrc-vcore
+ - required:
+ - dvfsrc-vscp
+
+additionalProperties: false
--
2.45.2
Add bindings for the MediaTek External Memory Interface Interconnect,
which providers support system bandwidth requirements through Dynamic
Voltage Frequency Scaling Resource Collector (DVFSRC) hardware.
This adds bindings for MediaTek MT8183 and MT8195 SoCs.
Note that this is modeled as a subnode of DVFSRC for multiple reasons:
- Some SoCs have more than one interconnect on the DVFSRC (and two
different kinds of EMI interconnect, and also a SMI interconnect);
- Some boards will want to not enable the interconnect driver because
some of those are not battery powered (so they just keep the knobs
at full thrust from the bootloader and never care scaling busses);
- Some DVFSRC interconnect features may depend on firmware.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
.../interconnect/mediatek,mt8183-emi.yaml | 51 +++++++++++++++++++
.../interconnect/mediatek,mt8183.h | 23 +++++++++
.../interconnect/mediatek,mt8195.h | 44 ++++++++++++++++
3 files changed, 118 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/mediatek,mt8183-emi.yaml
create mode 100644 include/dt-bindings/interconnect/mediatek,mt8183.h
create mode 100644 include/dt-bindings/interconnect/mediatek,mt8195.h
diff --git a/Documentation/devicetree/bindings/interconnect/mediatek,mt8183-emi.yaml b/Documentation/devicetree/bindings/interconnect/mediatek,mt8183-emi.yaml
new file mode 100644
index 000000000000..017c8478b2a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/mediatek,mt8183-emi.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/mediatek,mt8183-emi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek External Memory Interface (EMI) Interconnect
+
+maintainers:
+ - AngeloGioacchino Del Regno <[email protected]>
+
+description: |
+ EMI interconnect providers support system bandwidth requirements through
+ Dynamic Voltage Frequency Scaling Resource Collector (DVFSRC) hardware.
+ The provider is able to communicate with the DVFSRC through Secure Monitor
+ Call (SMC).
+
+ ICC provider ICC Nodes
+ ---- ----
+ _________ |CPU | |--- |VPU |
+ _____ | |----- ---- | ----
+ | |->| DRAM | ---- | ----
+ |DRAM |->|scheduler|----- |GPU | |--- |DISP|
+ | |->| (EMI) | ---- | ----
+ |_____|->|_________|---. ----- | ----
+ /|\ `-|MMSYS|--|--- |VDEC|
+ | ----- | ----
+ | | ----
+ | change DRAM freq |--- |VENC|
+ -------- | ----
+ SMC --> | DVFSRC | | ----
+ -------- |--- |IMG |
+ | ----
+ | ----
+ |--- |CAM |
+ ----
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8183-emi
+ - mediatek,mt8195-emi
+
+ '#interconnect-cells':
+ const: 1
+
+required:
+ - compatible
+ - '#interconnect-cells'
+
+unevaluatedProperties: false
diff --git a/include/dt-bindings/interconnect/mediatek,mt8183.h b/include/dt-bindings/interconnect/mediatek,mt8183.h
new file mode 100644
index 000000000000..1088c350258d
--- /dev/null
+++ b/include/dt-bindings/interconnect/mediatek,mt8183.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2024 Collabora Ltd.
+ * AngeloGioacchino Del Regno <[email protected]>
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8183_H
+#define __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8183_H
+
+#define SLAVE_DDR_EMI 0
+#define MASTER_MCUSYS 1
+#define MASTER_MFG 2
+#define MASTER_MMSYS 3
+#define MASTER_MM_VPU 4
+#define MASTER_MM_DISP 5
+#define MASTER_MM_VDEC 6
+#define MASTER_MM_VENC 7
+#define MASTER_MM_CAM 8
+#define MASTER_MM_IMG 9
+#define MASTER_MM_MDP 10
+
+#endif
diff --git a/include/dt-bindings/interconnect/mediatek,mt8195.h b/include/dt-bindings/interconnect/mediatek,mt8195.h
new file mode 100644
index 000000000000..33e0e6cde732
--- /dev/null
+++ b/include/dt-bindings/interconnect/mediatek,mt8195.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Copyright (c) 2024 Collabora Ltd.
+ * AngeloGioacchino Del Regno <[email protected]>
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8195_H
+#define __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8195_H
+
+#define SLAVE_DDR_EMI 0
+#define MASTER_MCUSYS 1
+#define MASTER_GPUSYS 2
+#define MASTER_MMSYS 3
+#define MASTER_MM_VPU 4
+#define MASTER_MM_DISP 5
+#define MASTER_MM_VDEC 6
+#define MASTER_MM_VENC 7
+#define MASTER_MM_CAM 8
+#define MASTER_MM_IMG 9
+#define MASTER_MM_MDP 10
+#define MASTER_VPUSYS 11
+#define MASTER_VPU_0 12
+#define MASTER_VPU_1 13
+#define MASTER_MDLASYS 14
+#define MASTER_MDLA_0 15
+#define MASTER_UFS 16
+#define MASTER_PCIE_0 17
+#define MASTER_PCIE_1 18
+#define MASTER_USB 19
+#define MASTER_DBGIF 20
+#define SLAVE_HRT_DDR_EMI 21
+#define MASTER_HRT_MMSYS 22
+#define MASTER_HRT_MM_DISP 23
+#define MASTER_HRT_MM_VDEC 24
+#define MASTER_HRT_MM_VENC 25
+#define MASTER_HRT_MM_CAM 26
+#define MASTER_HRT_MM_IMG 27
+#define MASTER_HRT_MM_MDP 28
+#define MASTER_HRT_DBGIF 29
+#define MASTER_WIFI 30
+#define MASTER_BT 31
+#define MASTER_NETSYS 32
+#endif
--
2.45.2
The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a
Hardware module used to collect all the requests from both software and the
various remote processors embedded into the SoC and decide about a minimum
operating voltage and a minimum DRAM frequency to fulfill those requests in
an effort to provide the best achievable performance per watt.
This hardware IP is capable of transparently performing direct register R/W
on all of the DVFSRC-controlled regulators and SoC bandwidth knobs.
This driver includes support for MT8183, MT8192 and MT8195.
Co-Developed-by: Dawei Chien <[email protected]>
[Angelo: Partial refactoring and cleanups]
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
drivers/soc/mediatek/Kconfig | 11 +
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mtk-dvfsrc.c | 545 +++++++++++++++++++++++
include/linux/soc/mediatek/dvfsrc.h | 36 ++
include/linux/soc/mediatek/mtk_sip_svc.h | 3 +
5 files changed, 596 insertions(+)
create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
create mode 100644 include/linux/soc/mediatek/dvfsrc.h
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index 1b7afb19ccd6..d7293977f06e 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -26,6 +26,17 @@ config MTK_DEVAPC
The violation information is logged for further analysis or
countermeasures.
+config MTK_DVFSRC
+ tristate "MediaTek DVFSRC Support"
+ depends on ARCH_MEDIATEK
+ help
+ Say yes here to add support for the MediaTek Dynamic Voltage
+ and Frequency Scaling Resource Collector (DVFSRC): a HW
+ IP found on many MediaTek SoCs, which is responsible for
+ collecting DVFS requests from various SoC IPs, other than
+ software, and performing bandwidth scaling to provide the
+ best achievable performance-per-watt.
+
config MTK_INFRACFG
bool "MediaTek INFRACFG Support"
select REGMAP
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index 6830512848fd..0665573e3c4b 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
obj-$(CONFIG_MTK_DEVAPC) += mtk-devapc.o
+obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o
obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_REGULATOR_COUPLER) += mtk-regulator-coupler.o
diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c b/drivers/soc/mediatek/mtk-dvfsrc.c
new file mode 100644
index 000000000000..83bf46fdcf2d
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-dvfsrc.c
@@ -0,0 +1,545 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Copyright (c) 2024 Collabora Ltd.
+ * AngeloGioacchino Del Regno <[email protected]>
+ */
+
+#include <linux/arm-smccc.h>
+#include <linux/bitfield.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/dvfsrc.h>
+#include <linux/soc/mediatek/mtk_sip_svc.h>
+
+/* DVFSRC_LEVEL */
+#define DVFSRC_V1_LEVEL_TARGET_LEVEL GENMASK(15, 0)
+#define DVFSRC_TGT_LEVEL_IDLE 0x00
+#define DVFSRC_V1_LEVEL_CURRENT_LEVEL GENMASK(31, 16)
+
+/* DVFSRC_SW_REQ, DVFSRC_SW_REQ2 */
+#define DVFSRC_V1_SW_REQ2_DRAM_LEVEL GENMASK(1, 0)
+#define DVFSRC_V1_SW_REQ2_VCORE_LEVEL GENMASK(3, 2)
+
+#define DVFSRC_V2_SW_REQ_DRAM_LEVEL GENMASK(3, 0)
+#define DVFSRC_V2_SW_REQ_VCORE_LEVEL GENMASK(6, 4)
+
+/* DVFSRC_VCORE */
+#define DVFSRC_V2_VCORE_REQ_VSCP_LEVEL GENMASK(14, 12)
+
+#define DVFSRC_POLL_TIMEOUT_US 1000
+#define STARTUP_TIME_US 1
+
+#define MTK_SIP_DVFSRC_INIT 0x0
+#define MTK_SIP_DVFSRC_START 0x1
+
+struct dvfsrc_bw_constraints {
+ u16 max_dram_nom_bw;
+ u16 max_dram_peak_bw;
+ u16 max_dram_hrt_bw;
+};
+
+struct dvfsrc_opp {
+ u32 vcore_opp;
+ u32 dram_opp;
+};
+
+struct dvfsrc_opp_desc {
+ const struct dvfsrc_opp *opps;
+ u32 num_opp;
+};
+
+struct dvfsrc_soc_data;
+struct mtk_dvfsrc {
+ struct device *dev;
+ struct platform_device *icc;
+ struct platform_device *regulator;
+ const struct dvfsrc_soc_data *dvd;
+ const struct dvfsrc_opp_desc *curr_opps;
+ void __iomem *regs;
+ int dram_type;
+};
+
+struct dvfsrc_soc_data {
+ const int *regs;
+ const struct dvfsrc_opp_desc *opps_desc;
+ u32 (*get_target_level)(struct mtk_dvfsrc *dvfsrc);
+ u32 (*get_current_level)(struct mtk_dvfsrc *dvfsrc);
+ u32 (*get_vcore_level)(struct mtk_dvfsrc *dvfsrc);
+ u32 (*get_vscp_level)(struct mtk_dvfsrc *dvfsrc);
+ void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_dram_peak_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_dram_hrt_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ void (*set_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ void (*set_vscp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ int (*wait_for_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ int (*wait_for_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ const struct dvfsrc_bw_constraints *bw_constraints;
+};
+
+static u32 dvfsrc_readl(struct mtk_dvfsrc *dvfs, u32 offset)
+{
+ return readl(dvfs->regs + dvfs->dvd->regs[offset]);
+}
+
+static void dvfsrc_writel(struct mtk_dvfsrc *dvfs, u32 offset, u32 val)
+{
+ writel(val, dvfs->regs + dvfs->dvd->regs[offset]);
+}
+
+enum dvfsrc_regs {
+ DVFSRC_SW_REQ,
+ DVFSRC_SW_REQ2,
+ DVFSRC_LEVEL,
+ DVFSRC_TARGET_LEVEL,
+ DVFSRC_SW_BW,
+ DVFSRC_SW_PEAK_BW,
+ DVFSRC_SW_HRT_BW,
+ DVFSRC_VCORE,
+ DVFSRC_REGS_MAX,
+};
+
+static const int dvfsrc_mt8183_regs[] = {
+ [DVFSRC_SW_REQ] = 0x4,
+ [DVFSRC_SW_REQ2] = 0x8,
+ [DVFSRC_LEVEL] = 0xDC,
+ [DVFSRC_SW_BW] = 0x160,
+};
+
+static const int dvfsrc_mt8195_regs[] = {
+ [DVFSRC_SW_REQ] = 0xc,
+ [DVFSRC_VCORE] = 0x6c,
+ [DVFSRC_SW_PEAK_BW] = 0x278,
+ [DVFSRC_SW_BW] = 0x26c,
+ [DVFSRC_SW_HRT_BW] = 0x290,
+ [DVFSRC_LEVEL] = 0xd44,
+ [DVFSRC_TARGET_LEVEL] = 0xd48,
+};
+
+static const struct dvfsrc_opp *dvfsrc_get_current_opp(struct mtk_dvfsrc *dvfsrc)
+{
+ u32 level = dvfsrc->dvd->get_current_level(dvfsrc);
+
+ return &dvfsrc->curr_opps->opps[level];
+}
+
+static bool dvfsrc_is_idle(struct mtk_dvfsrc *dvfsrc)
+{
+ if (!dvfsrc->dvd->get_target_level)
+ return true;
+
+ return dvfsrc->dvd->get_target_level(dvfsrc) == DVFSRC_TGT_LEVEL_IDLE;
+}
+
+static int dvfsrc_wait_for_vcore_level_v1(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+ const struct dvfsrc_opp *curr;
+
+ return readx_poll_timeout_atomic(dvfsrc_get_current_opp, dvfsrc, curr,
+ curr->vcore_opp >= level, STARTUP_TIME_US,
+ DVFSRC_POLL_TIMEOUT_US);
+}
+
+static int dvfsrc_wait_for_opp_level_v1(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+ const struct dvfsrc_opp *target, *curr;
+ int ret;
+
+ target = &dvfsrc->curr_opps->opps[level];
+ ret = readx_poll_timeout_atomic(dvfsrc_get_current_opp, dvfsrc, curr,
+ curr->dram_opp >= target->dram_opp &&
+ curr->vcore_opp >= target->vcore_opp,
+ STARTUP_TIME_US, DVFSRC_POLL_TIMEOUT_US);
+ if (ret < 0) {
+ dev_warn(dvfsrc->dev,
+ "timeout! target OPP: %u, dram: %d, vcore: %d\n", level,
+ curr->dram_opp, curr->vcore_opp);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int dvfsrc_wait_for_opp_level_v2(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+ const struct dvfsrc_opp *target, *curr;
+ int ret;
+
+ target = &dvfsrc->curr_opps->opps[level];
+ ret = readx_poll_timeout_atomic(dvfsrc_get_current_opp, dvfsrc, curr,
+ curr->dram_opp >= target->dram_opp &&
+ curr->vcore_opp >= target->vcore_opp,
+ STARTUP_TIME_US, DVFSRC_POLL_TIMEOUT_US);
+ if (ret < 0) {
+ dev_warn(dvfsrc->dev,
+ "timeout! target OPP: %u, dram: %d\n", level, curr->dram_opp);
+ return ret;
+ }
+
+ return 0;
+}
+
+static u32 dvfsrc_get_target_level_v1(struct mtk_dvfsrc *dvfsrc)
+{
+ u32 val = dvfsrc_readl(dvfsrc, DVFSRC_LEVEL);
+
+ return FIELD_GET(DVFSRC_V1_LEVEL_TARGET_LEVEL, val);
+}
+
+static u32 dvfsrc_get_current_level_v1(struct mtk_dvfsrc *dvfsrc)
+{
+ u32 val = dvfsrc_readl(dvfsrc, DVFSRC_LEVEL);
+ u32 current_level = FIELD_GET(DVFSRC_V1_LEVEL_CURRENT_LEVEL, val);
+
+ return ffs(current_level) - 1;
+}
+
+static u32 dvfsrc_get_target_level_v2(struct mtk_dvfsrc *dvfsrc)
+{
+ return dvfsrc_readl(dvfsrc, DVFSRC_TARGET_LEVEL);
+}
+
+static u32 dvfsrc_get_current_level_v2(struct mtk_dvfsrc *dvfsrc)
+{
+ u32 val = dvfsrc_readl(dvfsrc, DVFSRC_LEVEL);
+ u32 level = ffs(val);
+
+ /* Valid levels */
+ if (level < dvfsrc->curr_opps->num_opp)
+ return dvfsrc->curr_opps->num_opp - level;
+
+ /* Zero for level 0 or invalid level */
+ return 0;
+}
+
+static u32 dvfsrc_get_vcore_level_v1(struct mtk_dvfsrc *dvfsrc)
+{
+ u32 val = dvfsrc_readl(dvfsrc, DVFSRC_SW_REQ2);
+
+ return FIELD_GET(DVFSRC_V1_SW_REQ2_VCORE_LEVEL, val);
+}
+
+static void dvfsrc_set_vcore_level_v1(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+ u32 val = dvfsrc_readl(dvfsrc, DVFSRC_SW_REQ2);
+
+ val &= ~DVFSRC_V1_SW_REQ2_VCORE_LEVEL;
+ val |= FIELD_PREP(DVFSRC_V1_SW_REQ2_VCORE_LEVEL, level);
+
+ dvfsrc_writel(dvfsrc, DVFSRC_SW_REQ2, val);
+}
+
+static u32 dvfsrc_get_vcore_level_v2(struct mtk_dvfsrc *dvfsrc)
+{
+ u32 val = dvfsrc_readl(dvfsrc, DVFSRC_SW_REQ);
+
+ return FIELD_GET(DVFSRC_V2_SW_REQ_VCORE_LEVEL, val);
+}
+
+static void dvfsrc_set_vcore_level_v2(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+ u32 val = dvfsrc_readl(dvfsrc, DVFSRC_SW_REQ);
+
+ val &= ~DVFSRC_V2_SW_REQ_VCORE_LEVEL;
+ val |= FIELD_PREP(DVFSRC_V2_SW_REQ_VCORE_LEVEL, level);
+
+ dvfsrc_writel(dvfsrc, DVFSRC_SW_REQ, val);
+}
+
+static u32 dvfsrc_get_vscp_level_v2(struct mtk_dvfsrc *dvfsrc)
+{
+ u32 val = dvfsrc_readl(dvfsrc, DVFSRC_VCORE);
+
+ return FIELD_GET(DVFSRC_V2_VCORE_REQ_VSCP_LEVEL, val);
+}
+
+static void dvfsrc_set_vscp_level_v2(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+ u32 val = dvfsrc_readl(dvfsrc, DVFSRC_VCORE);
+
+ val &= ~DVFSRC_V2_VCORE_REQ_VSCP_LEVEL;
+ val |= FIELD_PREP(DVFSRC_V2_VCORE_REQ_VSCP_LEVEL, level);
+
+ dvfsrc_writel(dvfsrc, DVFSRC_VCORE, val);
+}
+
+static void __dvfsrc_set_dram_bw_v1(struct mtk_dvfsrc *dvfsrc, u32 reg,
+ u16 max_bw, u16 min_bw, u64 bw)
+{
+ u32 new_bw = (u32)div_u64(bw, 100 * 1000);
+
+ /* If bw constraints (in mbps) are defined make sure to respect them */
+ if (max_bw)
+ new_bw = min(new_bw, max_bw);
+ if (min_bw && new_bw > 0)
+ new_bw = max(new_bw, min_bw);
+
+ dvfsrc_writel(dvfsrc, reg, new_bw);
+}
+
+static void dvfsrc_set_dram_bw_v1(struct mtk_dvfsrc *dvfsrc, u64 bw)
+{
+ u64 max_bw = dvfsrc->dvd->bw_constraints->max_dram_nom_bw;
+
+ __dvfsrc_set_dram_bw_v1(dvfsrc, DVFSRC_SW_BW, max_bw, 0, bw);
+};
+
+static void dvfsrc_set_dram_peak_bw_v1(struct mtk_dvfsrc *dvfsrc, u64 bw)
+{
+ u64 max_bw = dvfsrc->dvd->bw_constraints->max_dram_peak_bw;
+
+ __dvfsrc_set_dram_bw_v1(dvfsrc, DVFSRC_SW_PEAK_BW, max_bw, 0, bw);
+}
+
+static void dvfsrc_set_dram_hrt_bw_v1(struct mtk_dvfsrc *dvfsrc, u64 bw)
+{
+ u64 max_bw = dvfsrc->dvd->bw_constraints->max_dram_hrt_bw;
+
+ __dvfsrc_set_dram_bw_v1(dvfsrc, DVFSRC_SW_HRT_BW, max_bw, 0, bw);
+}
+
+static void dvfsrc_set_opp_level_v1(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+ const struct dvfsrc_opp *opp = &dvfsrc->curr_opps->opps[level];
+ u32 val;
+
+ /* Translate Pstate to DVFSRC level and set it to DVFSRC HW */
+ val = FIELD_PREP(DVFSRC_V1_SW_REQ2_DRAM_LEVEL, opp->dram_opp);
+ val |= FIELD_PREP(DVFSRC_V1_SW_REQ2_VCORE_LEVEL, opp->vcore_opp);
+
+ dev_dbg(dvfsrc->dev, "vcore_opp: %d, dram_opp: %d\n", opp->vcore_opp, opp->dram_opp);
+ dvfsrc_writel(dvfsrc, DVFSRC_SW_REQ, val);
+}
+
+int mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, u64 data)
+{
+ struct mtk_dvfsrc *dvfsrc = dev_get_drvdata(dev);
+ bool state;
+ int ret;
+
+ dev_dbg(dvfsrc->dev, "cmd: %d, data: %llu\n", cmd, data);
+
+ switch (cmd) {
+ case MTK_DVFSRC_CMD_BW:
+ dvfsrc->dvd->set_dram_bw(dvfsrc, data);
+ return 0;
+ case MTK_DVFSRC_CMD_HRT_BW:
+ if (dvfsrc->dvd->set_dram_hrt_bw)
+ dvfsrc->dvd->set_dram_hrt_bw(dvfsrc, data);
+ return 0;
+ case MTK_DVFSRC_CMD_PEAK_BW:
+ if (dvfsrc->dvd->set_dram_peak_bw)
+ dvfsrc->dvd->set_dram_peak_bw(dvfsrc, data);
+ return 0;
+ case MTK_DVFSRC_CMD_OPP:
+ if (!dvfsrc->dvd->set_opp_level)
+ return 0;
+
+ dvfsrc->dvd->set_opp_level(dvfsrc, data);
+ break;
+ case MTK_DVFSRC_CMD_VCORE_LEVEL:
+ dvfsrc->dvd->set_vcore_level(dvfsrc, data);
+ break;
+ case MTK_DVFSRC_CMD_VSCP_LEVEL:
+ if (!dvfsrc->dvd->set_vscp_level)
+ return 0;
+
+ dvfsrc->dvd->set_vscp_level(dvfsrc, data);
+ break;
+ default:
+ dev_err(dvfsrc->dev, "unknown command: %d\n", cmd);
+ return -EOPNOTSUPP;
+ }
+
+ /* DVFSRC needs at least 2T(~196ns) to handle a request */
+ udelay(STARTUP_TIME_US);
+
+ ret = readx_poll_timeout_atomic(dvfsrc_is_idle, dvfsrc, state, state,
+ STARTUP_TIME_US, DVFSRC_POLL_TIMEOUT_US);
+ if (ret < 0) {
+ dev_warn(dvfsrc->dev,
+ "%d: idle timeout, data: %llu, last: %d -> %d\n", cmd, data,
+ dvfsrc->dvd->get_current_level(dvfsrc),
+ dvfsrc->dvd->get_target_level(dvfsrc));
+ return ret;
+ }
+
+ if (cmd == MTK_DVFSRC_CMD_OPP)
+ ret = dvfsrc->dvd->wait_for_opp_level(dvfsrc, data);
+ else
+ ret = dvfsrc->dvd->wait_for_vcore_level(dvfsrc, data);
+
+ if (ret < 0) {
+ dev_warn(dvfsrc->dev,
+ "%d: wait timeout, data: %llu, last: %d -> %d\n",
+ cmd, data,
+ dvfsrc->dvd->get_current_level(dvfsrc),
+ dvfsrc->dvd->get_target_level(dvfsrc));
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(mtk_dvfsrc_send_request);
+
+int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd, int *data)
+{
+ struct mtk_dvfsrc *dvfsrc = dev_get_drvdata(dev);
+
+ switch (cmd) {
+ case MTK_DVFSRC_CMD_VCORE_LEVEL:
+ *data = dvfsrc->dvd->get_vcore_level(dvfsrc);
+ break;
+ case MTK_DVFSRC_CMD_VSCP_LEVEL:
+ *data = dvfsrc->dvd->get_vscp_level(dvfsrc);
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(mtk_dvfsrc_query_info);
+
+static int mtk_dvfsrc_probe(struct platform_device *pdev)
+{
+ struct arm_smccc_res ares;
+ struct mtk_dvfsrc *dvfsrc;
+ int ret;
+
+ dvfsrc = devm_kzalloc(&pdev->dev, sizeof(*dvfsrc), GFP_KERNEL);
+ if (!dvfsrc)
+ return -ENOMEM;
+
+ dvfsrc->dvd = of_device_get_match_data(&pdev->dev);
+ dvfsrc->dev = &pdev->dev;
+
+ dvfsrc->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
+ if (IS_ERR(dvfsrc->regs))
+ return PTR_ERR(dvfsrc->regs);
+
+ arm_smccc_smc(MTK_SIP_DVFSRC_VCOREFS_CONTROL, MTK_SIP_DVFSRC_INIT,
+ 0, 0, 0, 0, 0, 0, &ares);
+ if (ares.a0)
+ return dev_err_probe(&pdev->dev, -EINVAL, "DVFSRC init failed: %lu\n", ares.a0);
+
+ dvfsrc->dram_type = ares.a1;
+ dev_dbg(&pdev->dev, "DRAM Type: %d\n", dvfsrc->dram_type);
+
+ dvfsrc->curr_opps = &dvfsrc->dvd->opps_desc[dvfsrc->dram_type];
+ platform_set_drvdata(pdev, dvfsrc);
+
+ ret = devm_of_platform_populate(&pdev->dev);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "Failed to populate child devices\n");
+
+ /* Everything is set up - make it run! */
+ arm_smccc_smc(MTK_SIP_DVFSRC_VCOREFS_CONTROL, MTK_SIP_DVFSRC_START,
+ 0, 0, 0, 0, 0, 0, &ares);
+ if (ares.a0)
+ return dev_err_probe(&pdev->dev, -EINVAL, "Cannot start DVFSRC: %lu\n", ares.a0);
+
+ return 0;
+}
+
+static const struct dvfsrc_opp dvfsrc_opp_mt8183_lp4[] = {
+ { 0, 0 }, { 0, 1 }, { 0, 2 }, { 1, 2 },
+};
+
+static const struct dvfsrc_opp dvfsrc_opp_mt8183_lp3[] = {
+ { 0, 0 }, { 0, 1 }, { 1, 1 }, { 1, 2 },
+};
+
+static const struct dvfsrc_opp_desc dvfsrc_opp_mt8183_desc[] = {
+ [0] = {
+ .opps = dvfsrc_opp_mt8183_lp4,
+ .num_opp = ARRAY_SIZE(dvfsrc_opp_mt8183_lp4),
+ },
+ [1] = {
+ .opps = dvfsrc_opp_mt8183_lp3,
+ .num_opp = ARRAY_SIZE(dvfsrc_opp_mt8183_lp3),
+ },
+ [2] = {
+ .opps = dvfsrc_opp_mt8183_lp3,
+ .num_opp = ARRAY_SIZE(dvfsrc_opp_mt8183_lp3),
+ }
+};
+
+static const struct dvfsrc_bw_constraints dvfsrc_bw_constr_mt8183 = { 0, 0, 0 };
+
+static const struct dvfsrc_soc_data mt8183_data = {
+ .opps_desc = dvfsrc_opp_mt8183_desc,
+ .regs = dvfsrc_mt8183_regs,
+ .get_target_level = dvfsrc_get_target_level_v1,
+ .get_current_level = dvfsrc_get_current_level_v1,
+ .get_vcore_level = dvfsrc_get_vcore_level_v1,
+ .set_dram_bw = dvfsrc_set_dram_bw_v1,
+ .set_opp_level = dvfsrc_set_opp_level_v1,
+ .set_vcore_level = dvfsrc_set_vcore_level_v1,
+ .wait_for_opp_level = dvfsrc_wait_for_opp_level_v1,
+ .wait_for_vcore_level = dvfsrc_wait_for_vcore_level_v1,
+ .bw_constraints = &dvfsrc_bw_constr_mt8183,
+};
+
+static const struct dvfsrc_opp dvfsrc_opp_mt8195_lp4[] = {
+ { 0, 0 }, { 1, 0 }, { 2, 0 }, { 3, 0 },
+ { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1 },
+ { 0, 2 }, { 1, 2 }, { 2, 2 }, { 3, 2 },
+ { 1, 3 }, { 2, 3 }, { 3, 3 }, { 1, 4 },
+ { 2, 4 }, { 3, 4 }, { 2, 5 }, { 3, 5 },
+ { 3, 6 },
+};
+
+static const struct dvfsrc_opp_desc dvfsrc_opp_mt8195_desc[] = {
+ [0] = {
+ .opps = dvfsrc_opp_mt8195_lp4,
+ .num_opp = ARRAY_SIZE(dvfsrc_opp_mt8195_lp4),
+ }
+};
+
+static const struct dvfsrc_bw_constraints dvfsrc_bw_constr_mt8195 = {
+ .max_dram_nom_bw = 255,
+ .max_dram_peak_bw = 255,
+ .max_dram_hrt_bw = 1023,
+};
+
+static const struct dvfsrc_soc_data mt8195_data = {
+ .opps_desc = dvfsrc_opp_mt8195_desc,
+ .regs = dvfsrc_mt8195_regs,
+ .get_target_level = dvfsrc_get_target_level_v2,
+ .get_current_level = dvfsrc_get_current_level_v2,
+ .get_vcore_level = dvfsrc_get_vcore_level_v2,
+ .get_vscp_level = dvfsrc_get_vscp_level_v2,
+ .set_dram_bw = dvfsrc_set_dram_bw_v1,
+ .set_dram_peak_bw = dvfsrc_set_dram_peak_bw_v1,
+ .set_dram_hrt_bw = dvfsrc_set_dram_hrt_bw_v1,
+ .set_vcore_level = dvfsrc_set_vcore_level_v2,
+ .set_vscp_level = dvfsrc_set_vscp_level_v2,
+ .wait_for_opp_level = dvfsrc_wait_for_opp_level_v2,
+ .wait_for_vcore_level = dvfsrc_wait_for_vcore_level_v1,
+ .bw_constraints = &dvfsrc_bw_constr_mt8195,
+};
+
+static const struct of_device_id mtk_dvfsrc_of_match[] = {
+ { .compatible = "mediatek,mt8183-dvfsrc", .data = &mt8183_data },
+ { .compatible = "mediatek,mt8195-dvfsrc", .data = &mt8195_data },
+ { /* sentinel */ }
+};
+
+static struct platform_driver mtk_dvfsrc_driver = {
+ .probe = mtk_dvfsrc_probe,
+ .driver = {
+ .name = "mtk-dvfsrc",
+ .of_match_table = mtk_dvfsrc_of_match,
+ },
+};
+module_platform_driver(mtk_dvfsrc_driver);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <[email protected]>");
+MODULE_AUTHOR("Dawei Chien <[email protected]>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MediaTek DVFSRC driver");
diff --git a/include/linux/soc/mediatek/dvfsrc.h b/include/linux/soc/mediatek/dvfsrc.h
new file mode 100644
index 000000000000..1498b3ed396b
--- /dev/null
+++ b/include/linux/soc/mediatek/dvfsrc.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2024 Collabora Ltd.
+ * AngeloGioacchino Del Regno <[email protected]>
+ */
+
+#ifndef __MEDIATEK_DVFSRC_H
+#define __MEDIATEK_DVFSRC_H
+
+enum mtk_dvfsrc_cmd {
+ MTK_DVFSRC_CMD_BW,
+ MTK_DVFSRC_CMD_HRT_BW,
+ MTK_DVFSRC_CMD_PEAK_BW,
+ MTK_DVFSRC_CMD_OPP,
+ MTK_DVFSRC_CMD_VCORE_LEVEL,
+ MTK_DVFSRC_CMD_VSCP_LEVEL,
+ MTK_DVFSRC_CMD_MAX,
+};
+
+#if IS_ENABLED(CONFIG_MTK_DVFSRC)
+
+int mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, u64 data);
+int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd, int *data);
+
+#else
+
+static inline int mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, u64 data)
+{ return -ENODEV; }
+
+static inline int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd, int *data)
+{ return -ENODEV; }
+
+#endif /* CONFIG_MTK_DVFSRC */
+
+#endif
diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h b/include/linux/soc/mediatek/mtk_sip_svc.h
index 0761128b4354..abe24a73ee19 100644
--- a/include/linux/soc/mediatek/mtk_sip_svc.h
+++ b/include/linux/soc/mediatek/mtk_sip_svc.h
@@ -22,6 +22,9 @@
ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \
ARM_SMCCC_OWNER_SIP, fn_id)
+/* DVFSRC SMC calls */
+#define MTK_SIP_DVFSRC_VCOREFS_CONTROL MTK_SIP_SMC_CMD(0x506)
+
/* IOMMU related SMC call */
#define MTK_SIP_KERNEL_IOMMU_CONTROL MTK_SIP_SMC_CMD(0x514)
--
2.45.2
Add bindings for the MediaTek Dynamic Voltage and Frequency Scaling
Resource Collector (DVFSRC), a hardware module used to collect all the
requests from both software and the various remote processors embedded
into the SoC and decide about a minimum operating voltage and a minimum
DRAM frequency to fulfill those requests in an effort to provide the
best achievable performance per watt.
This hardware IP is capable of transparently performing direct register
R/W on all of the DVFSRC-controlled regulators and SoC bandwidth knobs.
Reviewed-by: Rob Herring (Arm) <[email protected]>
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
.../soc/mediatek/mediatek,mt8183-dvfsrc.yaml | 83 +++++++++++++++++++
1 file changed, 83 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml
new file mode 100644
index 000000000000..1ad5b61b249f
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/mediatek/mediatek,mt8183-dvfsrc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC)
+
+description:
+ The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a
+ Hardware module used to collect all the requests from both software and the
+ various remote processors embedded into the SoC and decide about a minimum
+ operating voltage and a minimum DRAM frequency to fulfill those requests in
+ an effort to provide the best achievable performance per watt.
+ This hardware IP is capable of transparently performing direct register R/W
+ on all of the DVFSRC-controlled regulators and SoC bandwidth knobs.
+
+maintainers:
+ - AngeloGioacchino Del Regno <[email protected]>
+ - Henry Chen <[email protected]>
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt8183-dvfsrc
+ - mediatek,mt8195-dvfsrc
+ - items:
+ - const: mediatek,mt8192-dvfsrc
+ - const: mediatek,mt8195-dvfsrc
+
+ reg:
+ maxItems: 1
+ description: DVFSRC common register address and length.
+
+ regulators:
+ type: object
+ $ref: /schemas/regulator/mediatek,mt6873-dvfsrc-regulator.yaml#
+
+ interconnect:
+ type: object
+ $ref: /schemas/interconnect/mediatek,mt8183-emi.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ system-controller@10012000 {
+ compatible = "mediatek,mt8195-dvfsrc";
+ reg = <0 0x10012000 0 0x1000>;
+
+ regulators {
+ compatible = "mediatek,mt8195-dvfsrc-regulator";
+
+ dvfsrc_vcore: dvfsrc-vcore {
+ regulator-name = "dvfsrc-vcore";
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <750000>;
+ regulator-always-on;
+ };
+
+ dvfsrc_vscp: dvfsrc-vscp {
+ regulator-name = "dvfsrc-vscp";
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <750000>;
+ regulator-always-on;
+ };
+ };
+
+ emi_icc: interconnect {
+ compatible = "mediatek,mt8195-emi";
+ #interconnect-cells = <1>;
+ };
+ };
+ };
--
2.45.2
This driver never worked, and never got even compiled, because it was
missing the DVFSRC driver entirely, including headers it relies on!
In preparation of a full refactoring of this driver, remove it.
The Makefile and Kconfig entries are retained, as those are reused
as-is for the refactored code.
Acked-by: Mark Brown <[email protected]>
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
drivers/regulator/mtk-dvfsrc-regulator.c | 214 -----------------------
1 file changed, 214 deletions(-)
delete mode 100644 drivers/regulator/mtk-dvfsrc-regulator.c
diff --git a/drivers/regulator/mtk-dvfsrc-regulator.c b/drivers/regulator/mtk-dvfsrc-regulator.c
deleted file mode 100644
index f1280d45265d..000000000000
--- a/drivers/regulator/mtk-dvfsrc-regulator.c
+++ /dev/null
@@ -1,214 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright (c) 2020 MediaTek Inc.
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/of_.h>
-#include <linux/regulator/driver.h>
-#include <linux/regulator/of_regulator.h>
-#include <linux/soc/mediatek/mtk_dvfsrc.h>
-
-#define DVFSRC_ID_VCORE 0
-#define DVFSRC_ID_VSCP 1
-
-#define MT_DVFSRC_REGULAR(match, _name, _volt_table) \
-[DVFSRC_ID_##_name] = { \
- .desc = { \
- .name = match, \
- .of_match = of_match_ptr(match), \
- .ops = &dvfsrc_vcore_ops, \
- .type = REGULATOR_VOLTAGE, \
- .id = DVFSRC_ID_##_name, \
- .owner = THIS_MODULE, \
- .n_voltages = ARRAY_SIZE(_volt_table), \
- .volt_table = _volt_table, \
- }, \
-}
-
-/*
- * DVFSRC regulators' information
- *
- * @desc: standard fields of regulator description.
- * @voltage_selector: Selector used for get_voltage_sel() and
- * set_voltage_sel() callbacks
- */
-
-struct dvfsrc_regulator {
- struct regulator_desc desc;
-};
-
-/*
- * MTK DVFSRC regulators' init data
- *
- * @size: num of regulators
- * @regulator_info: regulator info.
- */
-struct dvfsrc_regulator_init_data {
- u32 size;
- struct dvfsrc_regulator *regulator_info;
-};
-
-static inline struct device *to_dvfsrc_dev(struct regulator_dev *rdev)
-{
- return rdev_get_dev(rdev)->parent;
-}
-
-static int dvfsrc_set_voltage_sel(struct regulator_dev *rdev,
- unsigned int selector)
-{
- struct device *dvfsrc_dev = to_dvfsrc_dev(rdev);
- int id = rdev_get_id(rdev);
-
- if (id == DVFSRC_ID_VCORE)
- mtk_dvfsrc_send_request(dvfsrc_dev,
- MTK_DVFSRC_CMD_VCORE_REQUEST,
- selector);
- else if (id == DVFSRC_ID_VSCP)
- mtk_dvfsrc_send_request(dvfsrc_dev,
- MTK_DVFSRC_CMD_VSCP_REQUEST,
- selector);
- else
- return -EINVAL;
-
- return 0;
-}
-
-static int dvfsrc_get_voltage_sel(struct regulator_dev *rdev)
-{
- struct device *dvfsrc_dev = to_dvfsrc_dev(rdev);
- int id = rdev_get_id(rdev);
- int val, ret;
-
- if (id == DVFSRC_ID_VCORE)
- ret = mtk_dvfsrc_query_info(dvfsrc_dev,
- MTK_DVFSRC_CMD_VCORE_LEVEL_QUERY,
- &val);
- else if (id == DVFSRC_ID_VSCP)
- ret = mtk_dvfsrc_query_info(dvfsrc_dev,
- MTK_DVFSRC_CMD_VSCP_LEVEL_QUERY,
- &val);
- else
- return -EINVAL;
-
- if (ret != 0)
- return ret;
-
- return val;
-}
-
-static const struct regulator_ops dvfsrc_vcore_ops = {
- .list_voltage = regulator_list_voltage_table,
- .get_voltage_sel = dvfsrc_get_voltage_sel,
- .set_voltage_sel = dvfsrc_set_voltage_sel,
-};
-
-static const unsigned int mt8183_voltages[] = {
- 725000,
- 800000,
-};
-
-static struct dvfsrc_regulator mt8183_regulators[] = {
- MT_DVFSRC_REGULAR("dvfsrc-vcore", VCORE,
- mt8183_voltages),
-};
-
-static const struct dvfsrc_regulator_init_data regulator_mt8183_data = {
- .size = ARRAY_SIZE(mt8183_regulators),
- .regulator_info = &mt8183_regulators[0],
-};
-
-static const unsigned int mt6873_voltages[] = {
- 575000,
- 600000,
- 650000,
- 725000,
-};
-
-static struct dvfsrc_regulator mt6873_regulators[] = {
- MT_DVFSRC_REGULAR("dvfsrc-vcore", VCORE,
- mt6873_voltages),
- MT_DVFSRC_REGULAR("dvfsrc-vscp", VSCP,
- mt6873_voltages),
-};
-
-static const struct dvfsrc_regulator_init_data regulator_mt6873_data = {
- .size = ARRAY_SIZE(mt6873_regulators),
- .regulator_info = &mt6873_regulators[0],
-};
-
-static const struct of_device_id mtk_dvfsrc_regulator_match[] = {
- {
- .compatible = "mediatek,mt8183-dvfsrc",
- .data = ®ulator_mt8183_data,
- }, {
- .compatible = "mediatek,mt8192-dvfsrc",
- .data = ®ulator_mt6873_data,
- }, {
- .compatible = "mediatek,mt6873-dvfsrc",
- .data = ®ulator_mt6873_data,
- }, {
- /* sentinel */
- },
-};
-MODULE_DEVICE_TABLE(of, mtk_dvfsrc_regulator_match);
-
-static int dvfsrc_vcore_regulator_probe(struct platform_device *pdev)
-{
- const struct of_device_id *match;
- struct device *dev = &pdev->dev;
- struct regulator_config config = { };
- struct regulator_dev *rdev;
- const struct dvfsrc_regulator_init_data *regulator_init_data;
- struct dvfsrc_regulator *mt_regulators;
- int i;
-
- match = of_match_node(mtk_dvfsrc_regulator_match, dev->parent->of_node);
-
- if (!match) {
- dev_err(dev, "invalid compatible string\n");
- return -ENODEV;
- }
-
- regulator_init_data = match->data;
-
- mt_regulators = regulator_init_data->regulator_info;
- for (i = 0; i < regulator_init_data->size; i++) {
- config.dev = dev->parent;
- config.driver_data = (mt_regulators + i);
- rdev = devm_regulator_register(dev, &(mt_regulators + i)->desc,
- &config);
- if (IS_ERR(rdev)) {
- dev_err(dev, "failed to register %s\n",
- (mt_regulators + i)->desc.name);
- return PTR_ERR(rdev);
- }
- }
-
- return 0;
-}
-
-static struct platform_driver mtk_dvfsrc_regulator_driver = {
- .driver = {
- .name = "mtk-dvfsrc-regulator",
- .probe_type = PROBE_PREFER_ASYNCHRONOUS,
- },
- .probe = dvfsrc_vcore_regulator_probe,
-};
-
-static int __init mtk_dvfsrc_regulator_init(void)
-{
- return platform_driver_register(&mtk_dvfsrc_regulator_driver);
-}
-subsys_initcall(mtk_dvfsrc_regulator_init);
-
-static void __exit mtk_dvfsrc_regulator_exit(void)
-{
- platform_driver_unregister(&mtk_dvfsrc_regulator_driver);
-}
-module_exit(mtk_dvfsrc_regulator_exit);
-
-MODULE_AUTHOR("Arvin wang <[email protected]>");
-MODULE_LICENSE("GPL v2");
--
2.45.2
The previous driver never worked, and never got even compiled because
it was missing the DVFSRC driver entirely, including needed neaders.
This is a full (or nearly full) refactoring of the MediaTek DVFSRC
controlled Regulators driver, retaining support for the MT6873, MT8183
and MT8192 SoC, and adding MT8195.
As part of the refactoring, this driver is now probed using its own
devicetree compatible, as this is a child of the main DVFSRC driver
and gets probed as a subnode of that.
Reviewed-by: Mark Brown <[email protected]>
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
drivers/regulator/mtk-dvfsrc-regulator.c | 196 +++++++++++++++++++++++
1 file changed, 196 insertions(+)
create mode 100644 drivers/regulator/mtk-dvfsrc-regulator.c
diff --git a/drivers/regulator/mtk-dvfsrc-regulator.c b/drivers/regulator/mtk-dvfsrc-regulator.c
new file mode 100644
index 000000000000..558efd8124b6
--- /dev/null
+++ b/drivers/regulator/mtk-dvfsrc-regulator.c
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ * Copyright (c) 2024 Collabora Ltd.
+ * AngeloGioacchino Del Regno <[email protected]>
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/soc/mediatek/dvfsrc.h>
+
+enum dvfsrc_regulator_id {
+ DVFSRC_ID_VCORE,
+ DVFSRC_ID_VSCP,
+ DVFSRC_ID_MAX
+};
+
+struct dvfsrc_regulator_pdata {
+ struct regulator_desc *descs;
+ u32 size;
+};
+
+#define MTK_DVFSRC_VREG(match, _name, _volt_table) \
+{ \
+ .name = match, \
+ .of_match = match, \
+ .ops = &dvfsrc_vcore_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = DVFSRC_ID_##_name, \
+ .owner = THIS_MODULE, \
+ .n_voltages = ARRAY_SIZE(_volt_table), \
+ .volt_table = _volt_table, \
+}
+
+static inline struct device *to_dvfs_regulator_dev(struct regulator_dev *rdev)
+{
+ return rdev_get_dev(rdev)->parent;
+}
+
+static inline struct device *to_dvfsrc_dev(struct regulator_dev *rdev)
+{
+ return to_dvfs_regulator_dev(rdev)->parent;
+}
+
+static int dvfsrc_get_cmd(int rdev_id, enum mtk_dvfsrc_cmd *cmd)
+{
+ switch (rdev_id) {
+ case DVFSRC_ID_VCORE:
+ *cmd = MTK_DVFSRC_CMD_VCORE_LEVEL;
+ break;
+ case DVFSRC_ID_VSCP:
+ *cmd = MTK_DVFSRC_CMD_VSCP_LEVEL;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int dvfsrc_set_voltage_sel(struct regulator_dev *rdev,
+ unsigned int selector)
+{
+ struct device *dvfsrc_dev = to_dvfsrc_dev(rdev);
+ enum mtk_dvfsrc_cmd req_cmd;
+ int id = rdev_get_id(rdev);
+ int ret;
+
+ ret = dvfsrc_get_cmd(id, &req_cmd);
+ if (ret)
+ return ret;
+
+ return mtk_dvfsrc_send_request(dvfsrc_dev, req_cmd, selector);
+}
+
+static int dvfsrc_get_voltage_sel(struct regulator_dev *rdev)
+{
+ struct device *dvfsrc_dev = to_dvfsrc_dev(rdev);
+ enum mtk_dvfsrc_cmd query_cmd;
+ int id = rdev_get_id(rdev);
+ int val, ret;
+
+ ret = dvfsrc_get_cmd(id, &query_cmd);
+ if (ret)
+ return ret;
+
+ ret = mtk_dvfsrc_query_info(dvfsrc_dev, query_cmd, &val);
+ if (ret)
+ return ret;
+
+ return val;
+}
+
+static const struct regulator_ops dvfsrc_vcore_ops = {
+ .list_voltage = regulator_list_voltage_table,
+ .get_voltage_sel = dvfsrc_get_voltage_sel,
+ .set_voltage_sel = dvfsrc_set_voltage_sel,
+};
+
+static const unsigned int mt6873_voltages[] = {
+ 575000,
+ 600000,
+ 650000,
+ 725000,
+};
+
+static struct regulator_desc mt6873_regulators[] = {
+ MTK_DVFSRC_VREG("dvfsrc-vcore", VCORE, mt6873_voltages),
+ MTK_DVFSRC_VREG("dvfsrc-vscp", VSCP, mt6873_voltages),
+};
+
+static const struct dvfsrc_regulator_pdata mt6873_data = {
+ .descs = mt6873_regulators,
+ .size = ARRAY_SIZE(mt6873_regulators),
+};
+
+static const unsigned int mt8183_voltages[] = {
+ 725000,
+ 800000,
+};
+
+static struct regulator_desc mt8183_regulators[] = {
+ MTK_DVFSRC_VREG("dvfsrc-vcore", VCORE, mt8183_voltages),
+};
+
+static const struct dvfsrc_regulator_pdata mt8183_data = {
+ .descs = mt8183_regulators,
+ .size = ARRAY_SIZE(mt8183_regulators),
+};
+
+static const unsigned int mt8195_voltages[] = {
+ 550000,
+ 600000,
+ 650000,
+ 750000,
+};
+
+static struct regulator_desc mt8195_regulators[] = {
+ MTK_DVFSRC_VREG("dvfsrc-vcore", VCORE, mt8195_voltages),
+ MTK_DVFSRC_VREG("dvfsrc-vscp", VSCP, mt8195_voltages),
+};
+
+static const struct dvfsrc_regulator_pdata mt8195_data = {
+ .descs = mt8195_regulators,
+ .size = ARRAY_SIZE(mt8195_regulators),
+};
+
+static int dvfsrc_vcore_regulator_probe(struct platform_device *pdev)
+{
+ struct regulator_config config = { .dev = &pdev->dev };
+ const struct dvfsrc_regulator_pdata *pdata;
+ int i;
+
+ pdata = device_get_match_data(&pdev->dev);
+ if (!pdata)
+ return -EINVAL;
+
+ for (i = 0; i < pdata->size; i++) {
+ struct regulator_desc *vrdesc = &pdata->descs[i];
+ struct regulator_dev *rdev;
+
+ rdev = devm_regulator_register(&pdev->dev, vrdesc, &config);
+ if (IS_ERR(rdev))
+ return dev_err_probe(&pdev->dev, PTR_ERR(rdev),
+ "failed to register %s\n", vrdesc->name);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id mtk_dvfsrc_regulator_match[] = {
+ { .compatible = "mediatek,mt6873-dvfsrc-regulator", .data = &mt6873_data },
+ { .compatible = "mediatek,mt8183-dvfsrc-regulator", .data = &mt8183_data },
+ { .compatible = "mediatek,mt8192-dvfsrc-regulator", .data = &mt6873_data },
+ { .compatible = "mediatek,mt8195-dvfsrc-regulator", .data = &mt8195_data },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mtk_dvfsrc_regulator_match);
+
+static struct platform_driver mtk_dvfsrc_regulator_driver = {
+ .driver = {
+ .name = "mtk-dvfsrc-regulator",
+ .of_match_table = mtk_dvfsrc_regulator_match,
+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ },
+ .probe = dvfsrc_vcore_regulator_probe,
+};
+module_platform_driver(mtk_dvfsrc_regulator_driver);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <[email protected]>");
+MODULE_AUTHOR("Arvin wang <[email protected]>");
+MODULE_DESCRIPTION("MediaTek DVFS Resource Collector Regulator driver");
+MODULE_LICENSE("GPL");
--
2.45.2
Add an interconnect driver for the External Memory Interface (EMI),
voting for bus bandwidth over the Dynamic Voltage and Frequency Scaling
Resource Collector (DVFSRC).
ICC provider ICC Nodes
---- ----
--------- |CPU | |--- |VPU |
----- | |----- ---- | ----
|DRAM |--|DRAM | ---- | ----
| |--|scheduler|----- |GPU | |--- |DISP|
| |--|(EMI) | ---- | ----
| |--| | ----- | ----
----- | |----- |MMSYS|--|--- |VDEC|
--------- ----- | ----
/|\ | ----
|change DRAM freq |--- |VENC|
---------- | ----
| DVFSR | |
| | | ----
---------- |--- |IMG |
| ----
| ----
|--- |CAM |
----
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
drivers/interconnect/Kconfig | 1 +
drivers/interconnect/Makefile | 1 +
drivers/interconnect/mediatek/Kconfig | 29 ++
drivers/interconnect/mediatek/Makefile | 5 +
drivers/interconnect/mediatek/icc-emi.c | 153 +++++++++++
drivers/interconnect/mediatek/icc-emi.h | 40 +++
drivers/interconnect/mediatek/mt8183.c | 143 ++++++++++
drivers/interconnect/mediatek/mt8195.c | 339 ++++++++++++++++++++++++
8 files changed, 711 insertions(+)
create mode 100644 drivers/interconnect/mediatek/Kconfig
create mode 100644 drivers/interconnect/mediatek/Makefile
create mode 100644 drivers/interconnect/mediatek/icc-emi.c
create mode 100644 drivers/interconnect/mediatek/icc-emi.h
create mode 100644 drivers/interconnect/mediatek/mt8183.c
create mode 100644 drivers/interconnect/mediatek/mt8195.c
diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig
index 5faa8d2aecff..f2e49bd97d31 100644
--- a/drivers/interconnect/Kconfig
+++ b/drivers/interconnect/Kconfig
@@ -12,6 +12,7 @@ menuconfig INTERCONNECT
if INTERCONNECT
source "drivers/interconnect/imx/Kconfig"
+source "drivers/interconnect/mediatek/Kconfig"
source "drivers/interconnect/qcom/Kconfig"
source "drivers/interconnect/samsung/Kconfig"
diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile
index d0888babb9a1..b0a9a6753b9d 100644
--- a/drivers/interconnect/Makefile
+++ b/drivers/interconnect/Makefile
@@ -5,6 +5,7 @@ icc-core-objs := core.o bulk.o debugfs-client.o
obj-$(CONFIG_INTERCONNECT) += icc-core.o
obj-$(CONFIG_INTERCONNECT_IMX) += imx/
+obj-$(CONFIG_INTERCONNECT_MTK) += mediatek/
obj-$(CONFIG_INTERCONNECT_QCOM) += qcom/
obj-$(CONFIG_INTERCONNECT_SAMSUNG) += samsung/
diff --git a/drivers/interconnect/mediatek/Kconfig b/drivers/interconnect/mediatek/Kconfig
new file mode 100644
index 000000000000..985c849efac3
--- /dev/null
+++ b/drivers/interconnect/mediatek/Kconfig
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config INTERCONNECT_MTK
+ bool "MediaTek interconnect drivers"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ help
+ Support for MediaTek's bus interconnect hardware.
+
+config INTERCONNECT_MTK_DVFSRC_EMI
+ tristate "MediaTek DVFSRC EMI interconnect driver"
+ depends on INTERCONNECT_MTK && MTK_DVFSRC
+ help
+ This is a driver for the MediaTek External Memory Interface
+ interconnect on SoCs equipped with the integrated Dynamic
+ Voltage Frequency Scaling Resource Collector (DVFSRC) MCU
+
+config INTERCONNECT_MTK_MT8183
+ tristate "MediaTek MT8183 interconnect driver"
+ depends on INTERCONNECT_MTK_DVFSRC_EMI
+ help
+ This is a driver for the MediaTek bus interconnect on MT8183-based
+ platforms.
+
+config INTERCONNECT_MTK_MT8195
+ tristate "MediaTek MT8195 interconnect driver"
+ depends on INTERCONNECT_MTK_DVFSRC_EMI
+ help
+ This is a driver for the MediaTek bus interconnect on MT8195-based
+ platforms.
diff --git a/drivers/interconnect/mediatek/Makefile b/drivers/interconnect/mediatek/Makefile
new file mode 100644
index 000000000000..8e2283a9a5b5
--- /dev/null
+++ b/drivers/interconnect/mediatek/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_INTERCONNECT_MTK_DVFSRC_EMI) += icc-emi.o
+obj-$(CONFIG_INTERCONNECT_MTK_MT8183) += mt8183.o
+obj-$(CONFIG_INTERCONNECT_MTK_MT8195) += mt8195.o
diff --git a/drivers/interconnect/mediatek/icc-emi.c b/drivers/interconnect/mediatek/icc-emi.c
new file mode 100644
index 000000000000..d420c55682d0
--- /dev/null
+++ b/drivers/interconnect/mediatek/icc-emi.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek External Memory Interface (EMI) Interconnect driver
+ *
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2024 Collabora Ltd.
+ * AngeloGioacchino Del Regno <[email protected]>
+ */
+
+#include <linux/interconnect.h>
+#include <linux/interconnect-provider.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/dvfsrc.h>
+
+#include "icc-emi.h"
+
+static int mtk_emi_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
+ u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
+{
+ struct mtk_icc_node *in = node->data;
+
+ *agg_avg += avg_bw;
+ *agg_peak = max_t(u32, *agg_peak, peak_bw);
+
+ in->sum_avg = *agg_avg;
+ in->max_peak = *agg_peak;
+
+ return 0;
+}
+
+static int mtk_emi_icc_set(struct icc_node *src, struct icc_node *dst)
+{
+ struct mtk_icc_node *node = dst->data;
+ struct device *dev;
+ int ret;
+
+ if (unlikely(!src->provider))
+ return -EINVAL;
+
+ dev = src->provider->dev;
+
+ switch (node->ep) {
+ case 0:
+ break;
+ case 1:
+ ret = mtk_dvfsrc_send_request(dev, MTK_DVFSRC_CMD_PEAK_BW, node->max_peak);
+ if (ret) {
+ dev_err(dev, "Cannot send peak bw request: %d\n", ret);
+ return ret;
+ }
+
+ ret = mtk_dvfsrc_send_request(dev, MTK_DVFSRC_CMD_BW, node->sum_avg);
+ if (ret) {
+ dev_err(dev, "Cannot send bw request: %d\n", ret);
+ return ret;
+ }
+ break;
+ case 2:
+ ret = mtk_dvfsrc_send_request(dev, MTK_DVFSRC_CMD_HRT_BW, node->sum_avg);
+ if (ret) {
+ dev_err(dev, "Cannot send HRT bw request: %d\n", ret);
+ return ret;
+ }
+ break;
+ default:
+ dev_err(src->provider->dev, "Unknown endpoint %u\n", node->ep);
+ return -EINVAL;
+ };
+
+ return 0;
+}
+
+int mtk_emi_icc_probe(struct platform_device *pdev)
+{
+ const struct mtk_icc_desc *desc;
+ struct device *dev = &pdev->dev;
+ struct icc_node *node;
+ struct icc_onecell_data *data;
+ struct icc_provider *provider;
+ struct mtk_icc_node **mnodes;
+ int i, j, ret;
+
+ desc = of_device_get_match_data(dev);
+ if (!desc)
+ return -EINVAL;
+
+ mnodes = desc->nodes;
+
+ provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL);
+ if (!provider)
+ return -ENOMEM;
+
+ data = devm_kzalloc(dev, struct_size(data, nodes, desc->num_nodes), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ provider->dev = pdev->dev.parent;
+ provider->set = mtk_emi_icc_set;
+ provider->aggregate = mtk_emi_icc_aggregate;
+ provider->xlate = of_icc_xlate_onecell;
+ INIT_LIST_HEAD(&provider->nodes);
+ provider->data = data;
+
+ for (i = 0; i < desc->num_nodes; i++) {
+ if (!mnodes[i])
+ continue;
+
+ node = icc_node_create(mnodes[i]->id);
+ if (IS_ERR(node)) {
+ ret = PTR_ERR(node);
+ goto err;
+ }
+
+ node->name = mnodes[i]->name;
+ node->data = mnodes[i];
+ icc_node_add(node, provider);
+
+ for (j = 0; j < mnodes[i]->num_links; j++)
+ icc_link_create(node, mnodes[i]->links[j]);
+
+ data->nodes[i] = node;
+ }
+ data->num_nodes = desc->num_nodes;
+
+ ret = icc_provider_register(provider);
+ if (ret)
+ goto err;
+
+ platform_set_drvdata(pdev, provider);
+
+ return 0;
+err:
+ icc_nodes_remove(provider);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtk_emi_icc_probe);
+
+void mtk_emi_icc_remove(struct platform_device *pdev)
+{
+ struct icc_provider *provider = platform_get_drvdata(pdev);
+
+ icc_provider_deregister(provider);
+ icc_nodes_remove(provider);
+}
+EXPORT_SYMBOL_GPL(mtk_emi_icc_remove);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <[email protected]>");
+MODULE_AUTHOR("Henry Chen <[email protected]>");
+MODULE_DESCRIPTION("MediaTek External Memory Interface interconnect driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/interconnect/mediatek/icc-emi.h b/drivers/interconnect/mediatek/icc-emi.h
new file mode 100644
index 000000000000..9512a50db6fa
--- /dev/null
+++ b/drivers/interconnect/mediatek/icc-emi.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2024 Collabora Ltd.
+ * AngeloGioacchino Del Regno <[email protected]>
+ */
+
+#ifndef __DRIVERS_INTERCONNECT_MEDIATEK_ICC_EMI_H
+#define __DRIVERS_INTERCONNECT_MEDIATEK_ICC_EMI_H
+
+/**
+ * struct mtk_icc_node - Mediatek EMI Interconnect Node
+ * @name: The interconnect node name which is shown in debugfs
+ * @ep: Type of this endpoint
+ * @id: Unique node identifier
+ * @sum_avg: Current sum aggregate value of all average bw requests in kBps
+ * @max_peak: Current max aggregate value of all peak bw requests in kBps
+ * @num_links: The total number of @links
+ * @links: Array of @id linked to this node
+ */
+struct mtk_icc_node {
+ unsigned char *name;
+ int ep;
+ u16 id;
+ u64 sum_avg;
+ u64 max_peak;
+
+ u16 num_links;
+ u16 links[] __counted_by(num_links);
+};
+
+struct mtk_icc_desc {
+ struct mtk_icc_node **nodes;
+ size_t num_nodes;
+};
+
+int mtk_emi_icc_probe(struct platform_device *pdev);
+void mtk_emi_icc_remove(struct platform_device *pdev);
+
+#endif /* __DRIVERS_INTERCONNECT_MEDIATEK_ICC_EMI_H */
diff --git a/drivers/interconnect/mediatek/mt8183.c b/drivers/interconnect/mediatek/mt8183.c
new file mode 100644
index 000000000000..24245085c7a9
--- /dev/null
+++ b/drivers/interconnect/mediatek/mt8183.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2024 Collabora Ltd.
+ * AngeloGioacchino Del Regno <[email protected]>
+ */
+
+#include <linux/device.h>
+#include <linux/interconnect.h>
+#include <linux/interconnect-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/interconnect/mediatek,mt8183.h>
+
+#include "icc-emi.h"
+
+static struct mtk_icc_node ddr_emi = {
+ .name = "ddr-emi",
+ .id = SLAVE_DDR_EMI,
+ .ep = 1,
+};
+
+static struct mtk_icc_node mcusys = {
+ .name = "mcusys",
+ .id = MASTER_MCUSYS,
+ .ep = 0,
+ .num_links = 1,
+ .links = { SLAVE_DDR_EMI }
+};
+
+static struct mtk_icc_node gpu = {
+ .name = "gpu",
+ .id = MASTER_MFG,
+ .ep = 0,
+ .num_links = 1,
+ .links = { SLAVE_DDR_EMI }
+};
+
+static struct mtk_icc_node mmsys = {
+ .name = "mmsys",
+ .id = MASTER_MMSYS,
+ .ep = 0,
+ .num_links = 1,
+ .links = { SLAVE_DDR_EMI }
+};
+
+static struct mtk_icc_node mm_vpu = {
+ .name = "mm-vpu",
+ .id = MASTER_MM_VPU,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_MMSYS }
+};
+
+static struct mtk_icc_node mm_disp = {
+ .name = "mm-disp",
+ .id = MASTER_MM_DISP,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_MMSYS }
+};
+
+static struct mtk_icc_node mm_vdec = {
+ .name = "mm-vdec",
+ .id = MASTER_MM_VDEC,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_MMSYS }
+};
+
+static struct mtk_icc_node mm_venc = {
+ .name = "mm-venc",
+ .id = MASTER_MM_VENC,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_MMSYS }
+};
+
+static struct mtk_icc_node mm_cam = {
+ .name = "mm-cam",
+ .id = MASTER_MM_CAM,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_MMSYS }
+};
+
+static struct mtk_icc_node mm_img = {
+ .name = "mm-img",
+ .id = MASTER_MM_IMG,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_MMSYS }
+};
+
+static struct mtk_icc_node mm_mdp = {
+ .name = "mm-mdp",
+ .id = MASTER_MM_MDP,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_MMSYS }
+};
+
+static struct mtk_icc_node *mt8183_emi_icc_nodes[] = {
+ [SLAVE_DDR_EMI] = &ddr_emi,
+ [MASTER_MCUSYS] = &mcusys,
+ [MASTER_MFG] = &gpu,
+ [MASTER_MMSYS] = &mmsys,
+ [MASTER_MM_VPU] = &mm_vpu,
+ [MASTER_MM_DISP] = &mm_disp,
+ [MASTER_MM_VDEC] = &mm_vdec,
+ [MASTER_MM_VENC] = &mm_venc,
+ [MASTER_MM_CAM] = &mm_cam,
+ [MASTER_MM_IMG] = &mm_img,
+ [MASTER_MM_MDP] = &mm_mdp
+};
+
+static const struct mtk_icc_desc mt8183_emi_icc = {
+ .nodes = mt8183_emi_icc_nodes,
+ .num_nodes = ARRAY_SIZE(mt8183_emi_icc_nodes),
+};
+
+static const struct of_device_id mtk_mt8183_emi_icc_of_match[] = {
+ { .compatible = "mediatek,mt8183-emi", .data = &mt8183_emi_icc },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, mtk_mt8183_emi_icc_of_match);
+
+static struct platform_driver mtk_emi_icc_mt8183_driver = {
+ .driver = {
+ .name = "emi-icc-mt8183",
+ .of_match_table = mtk_mt8183_emi_icc_of_match,
+ .sync_state = icc_sync_state,
+ },
+ .probe = mtk_emi_icc_probe,
+ .remove_new = mtk_emi_icc_remove,
+
+};
+module_platform_driver(mtk_emi_icc_mt8183_driver);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <[email protected]>");
+MODULE_DESCRIPTION("MediaTek MT8183 EMI ICC driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/interconnect/mediatek/mt8195.c b/drivers/interconnect/mediatek/mt8195.c
new file mode 100644
index 000000000000..710e14c5447c
--- /dev/null
+++ b/drivers/interconnect/mediatek/mt8195.c
@@ -0,0 +1,339 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2024 Collabora Ltd.
+ * AngeloGioacchino Del Regno <[email protected]>
+ */
+
+#include <linux/device.h>
+#include <linux/interconnect.h>
+#include <linux/interconnect-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/interconnect/mediatek,mt8195.h>
+
+#include "icc-emi.h"
+
+static struct mtk_icc_node ddr_emi = {
+ .name = "ddr-emi",
+ .id = SLAVE_DDR_EMI,
+ .ep = 1,
+};
+
+static struct mtk_icc_node mcusys = {
+ .name = "mcusys",
+ .id = MASTER_MCUSYS,
+ .ep = 0,
+ .num_links = 1,
+ .links = { SLAVE_DDR_EMI }
+};
+
+static struct mtk_icc_node gpu = {
+ .name = "gpu",
+ .id = MASTER_GPUSYS,
+ .ep = 0,
+ .num_links = 1,
+ .links = { SLAVE_DDR_EMI }
+};
+
+static struct mtk_icc_node mmsys = {
+ .name = "mmsys",
+ .id = MASTER_MMSYS,
+ .ep = 0,
+ .num_links = 1,
+ .links = { SLAVE_DDR_EMI }
+};
+
+static struct mtk_icc_node mm_vpu = {
+ .name = "mm-vpu",
+ .id = MASTER_MM_VPU,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_MMSYS }
+};
+
+static struct mtk_icc_node mm_disp = {
+ .name = "mm-disp",
+ .id = MASTER_MM_DISP,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_MMSYS }
+};
+
+static struct mtk_icc_node mm_vdec = {
+ .name = "mm-vdec",
+ .id = MASTER_MM_VDEC,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_MMSYS }
+};
+
+static struct mtk_icc_node mm_venc = {
+ .name = "mm-venc",
+ .id = MASTER_MM_VENC,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_MMSYS }
+};
+
+static struct mtk_icc_node mm_cam = {
+ .name = "mm-cam",
+ .id = MASTER_MM_CAM,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_MMSYS }
+};
+
+static struct mtk_icc_node mm_img = {
+ .name = "mm-img",
+ .id = MASTER_MM_IMG,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_MMSYS }
+};
+
+static struct mtk_icc_node mm_mdp = {
+ .name = "mm-mdp",
+ .id = MASTER_MM_MDP,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_MMSYS }
+};
+
+static struct mtk_icc_node vpusys = {
+ .name = "vpusys",
+ .id = MASTER_VPUSYS,
+ .ep = 0,
+ .num_links = 1,
+ .links = { SLAVE_DDR_EMI }
+};
+
+static struct mtk_icc_node vpu_port0 = {
+ .name = "vpu-port0",
+ .id = MASTER_VPU_0,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_VPUSYS }
+};
+
+static struct mtk_icc_node vpu_port1 = {
+ .name = "vpu-port1",
+ .id = MASTER_VPU_1,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_VPUSYS }
+};
+
+static struct mtk_icc_node mdlasys = {
+ .name = "mdlasys",
+ .id = MASTER_MDLASYS,
+ .ep = 0,
+ .num_links = 1,
+ .links = { SLAVE_DDR_EMI }
+};
+
+static struct mtk_icc_node mdla_port0 = {
+ .name = "mdla-port0",
+ .id = MASTER_MDLA_0,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_MDLASYS }
+};
+
+static struct mtk_icc_node ufs = {
+ .name = "ufs",
+ .id = MASTER_UFS,
+ .ep = 0,
+ .num_links = 1,
+ .links = { SLAVE_DDR_EMI }
+};
+
+static struct mtk_icc_node pcie0 = {
+ .name = "pcie0",
+ .id = MASTER_PCIE_0,
+ .ep = 0,
+ .num_links = 1,
+ .links = { SLAVE_DDR_EMI }
+};
+
+static struct mtk_icc_node pcie1 = {
+ .name = "pcie1",
+ .id = MASTER_PCIE_1,
+ .ep = 0,
+ .num_links = 1,
+ .links = { SLAVE_DDR_EMI }
+};
+
+static struct mtk_icc_node usb = {
+ .name = "usb",
+ .id = MASTER_USB,
+ .ep = 0,
+ .num_links = 1,
+ .links = { SLAVE_DDR_EMI }
+};
+
+static struct mtk_icc_node wifi = {
+ .name = "wifi",
+ .id = MASTER_WIFI,
+ .ep = 0,
+ .num_links = 1,
+ .links = { SLAVE_DDR_EMI }
+};
+
+static struct mtk_icc_node bt = {
+ .name = "bt",
+ .id = MASTER_BT,
+ .ep = 0,
+ .num_links = 1,
+ .links = { SLAVE_DDR_EMI }
+};
+
+static struct mtk_icc_node netsys = {
+ .name = "netsys",
+ .id = MASTER_NETSYS,
+ .ep = 0,
+ .num_links = 1,
+ .links = { SLAVE_DDR_EMI }
+};
+
+static struct mtk_icc_node dbgif = {
+ .name = "dbgif",
+ .id = MASTER_DBGIF,
+ .ep = 0,
+ .num_links = 1,
+ .links = { SLAVE_DDR_EMI }
+};
+
+static struct mtk_icc_node hrt_ddr_emi = {
+ .name = "hrt-ddr-emi",
+ .id = SLAVE_HRT_DDR_EMI,
+ .ep = 2,
+};
+
+static struct mtk_icc_node hrt_mmsys = {
+ .name = "hrt-mmsys",
+ .id = MASTER_HRT_MMSYS,
+ .ep = 0,
+ .num_links = 1,
+ .links = { SLAVE_HRT_DDR_EMI }
+};
+
+static struct mtk_icc_node hrt_mm_disp = {
+ .name = "hrt-mm-disp",
+ .id = MASTER_HRT_MM_DISP,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_HRT_MMSYS }
+};
+
+static struct mtk_icc_node hrt_mm_vdec = {
+ .name = "hrt-mm-vdec",
+ .id = MASTER_HRT_MM_VDEC,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_HRT_MMSYS }
+};
+
+static struct mtk_icc_node hrt_mm_venc = {
+ .name = "hrt-mm-venc",
+ .id = MASTER_HRT_MM_VENC,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_HRT_MMSYS }
+};
+
+static struct mtk_icc_node hrt_mm_cam = {
+ .name = "hrt-mm-cam",
+ .id = MASTER_HRT_MM_CAM,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_HRT_MMSYS }
+};
+
+static struct mtk_icc_node hrt_mm_img = {
+ .name = "hrt-mm-img",
+ .id = MASTER_HRT_MM_IMG,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_HRT_MMSYS }
+};
+
+static struct mtk_icc_node hrt_mm_mdp = {
+ .name = "hrt-mm-mdp",
+ .id = MASTER_HRT_MM_MDP,
+ .ep = 0,
+ .num_links = 1,
+ .links = { MASTER_HRT_MMSYS }
+};
+
+static struct mtk_icc_node hrt_dbgif = {
+ .name = "hrt-dbgif",
+ .id = MASTER_HRT_DBGIF,
+ .ep = 0,
+ .num_links = 1,
+ .links = { SLAVE_HRT_DDR_EMI }
+};
+
+static struct mtk_icc_node *mt8195_emi_icc_nodes[] = {
+ [SLAVE_DDR_EMI] = &ddr_emi,
+ [MASTER_MCUSYS] = &mcusys,
+ [MASTER_GPUSYS] = &gpu,
+ [MASTER_MMSYS] = &mmsys,
+ [MASTER_MM_VPU] = &mm_vpu,
+ [MASTER_MM_DISP] = &mm_disp,
+ [MASTER_MM_VDEC] = &mm_vdec,
+ [MASTER_MM_VENC] = &mm_venc,
+ [MASTER_MM_CAM] = &mm_cam,
+ [MASTER_MM_IMG] = &mm_img,
+ [MASTER_MM_MDP] = &mm_mdp,
+ [MASTER_VPUSYS] = &vpusys,
+ [MASTER_VPU_0] = &vpu_port0,
+ [MASTER_VPU_1] = &vpu_port1,
+ [MASTER_MDLASYS] = &mdlasys,
+ [MASTER_MDLA_0] = &mdla_port0,
+ [MASTER_UFS] = &ufs,
+ [MASTER_PCIE_0] = &pcie0,
+ [MASTER_PCIE_1] = &pcie1,
+ [MASTER_USB] = &usb,
+ [MASTER_WIFI] = &wifi,
+ [MASTER_BT] = &bt,
+ [MASTER_NETSYS] = &netsys,
+ [MASTER_DBGIF] = &dbgif,
+ [SLAVE_HRT_DDR_EMI] = &hrt_ddr_emi,
+ [MASTER_HRT_MMSYS] = &hrt_mmsys,
+ [MASTER_HRT_MM_DISP] = &hrt_mm_disp,
+ [MASTER_HRT_MM_VDEC] = &hrt_mm_vdec,
+ [MASTER_HRT_MM_VENC] = &hrt_mm_venc,
+ [MASTER_HRT_MM_CAM] = &hrt_mm_cam,
+ [MASTER_HRT_MM_IMG] = &hrt_mm_img,
+ [MASTER_HRT_MM_MDP] = &hrt_mm_mdp,
+ [MASTER_HRT_DBGIF] = &hrt_dbgif
+};
+
+static struct mtk_icc_desc mt8195_emi_icc = {
+ .nodes = mt8195_emi_icc_nodes,
+ .num_nodes = ARRAY_SIZE(mt8195_emi_icc_nodes),
+};
+
+static const struct of_device_id mtk_mt8195_emi_icc_of_match[] = {
+ { .compatible = "mediatek,mt8195-emi", .data = &mt8195_emi_icc },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, mtk_mt8195_emi_icc_of_match);
+
+static struct platform_driver mtk_emi_icc_mt8195_driver = {
+ .driver = {
+ .name = "emi-icc-mt8195",
+ .of_match_table = mtk_mt8195_emi_icc_of_match,
+ .sync_state = icc_sync_state,
+ },
+ .probe = mtk_emi_icc_probe,
+ .remove_new = mtk_emi_icc_remove,
+
+};
+module_platform_driver(mtk_emi_icc_mt8195_driver);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <[email protected]>");
+MODULE_DESCRIPTION("MediaTek MT8195 EMI ICC driver");
+MODULE_LICENSE("GPL");
--
2.45.2
On 10.06.24 11:57, AngeloGioacchino Del Regno wrote:
> The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a
> Hardware module used to collect all the requests from both software and the
> various remote processors embedded into the SoC and decide about a minimum
> operating voltage and a minimum DRAM frequency to fulfill those requests in
> an effort to provide the best achievable performance per watt.
>
> This hardware IP is capable of transparently performing direct register R/W
> on all of the DVFSRC-controlled regulators and SoC bandwidth knobs.
>
> This driver includes support for MT8183, MT8192 and MT8195.
>
> Co-Developed-by: Dawei Chien <[email protected]>
> [Angelo: Partial refactoring and cleanups]
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Georgi Djakov <[email protected]>
On 10.06.24 11:57, AngeloGioacchino Del Regno wrote:
> Changes in v6:
> - Fixed build with clang (thanks Nathan!)
> - Removed unused mtk_rmw() macro in mtk-dvfsrc.c
> - Added MODULE_DESCRIPTION() to mtk-dvfsrc-regulator.c
>
[..]
>
> AngeloGioacchino Del Regno (7):
> dt-bindings: regulator: Add bindings for MediaTek DVFSRC Regulators
> dt-bindings: interconnect: Add MediaTek EMI Interconnect bindings
> dt-bindings: soc: mediatek: Add DVFSRC bindings for MT8183 and MT8195
> soc: mediatek: Add MediaTek DVFS Resource Collector (DVFSRC) driver
> regulator: Remove mtk-dvfsrc-regulator.c
> regulator: Add refactored mtk-dvfsrc-regulator driver
> interconnect: mediatek: Add MediaTek MT8183/8195 EMI Interconnect
> driver
Thanks Angelo! I have picked patches 2 and 7. Patch 2 is also available
in my icc-mtk stable branch. Feel free to pull it to resolve the schema
dependency for patch 3.
BR,
Georgi
>
> .../interconnect/mediatek,mt8183-emi.yaml | 51 ++
> .../mediatek,mt6873-dvfsrc-regulator.yaml | 43 ++
> .../soc/mediatek/mediatek,mt8183-dvfsrc.yaml | 83 +++
> drivers/interconnect/Kconfig | 1 +
> drivers/interconnect/Makefile | 1 +
> drivers/interconnect/mediatek/Kconfig | 29 +
> drivers/interconnect/mediatek/Makefile | 5 +
> drivers/interconnect/mediatek/icc-emi.c | 153 +++++
> drivers/interconnect/mediatek/icc-emi.h | 40 ++
> drivers/interconnect/mediatek/mt8183.c | 143 +++++
> drivers/interconnect/mediatek/mt8195.c | 339 +++++++++++
> drivers/regulator/mtk-dvfsrc-regulator.c | 248 ++++----
> drivers/soc/mediatek/Kconfig | 11 +
> drivers/soc/mediatek/Makefile | 1 +
> drivers/soc/mediatek/mtk-dvfsrc.c | 545 ++++++++++++++++++
> .../interconnect/mediatek,mt8183.h | 23 +
> .../interconnect/mediatek,mt8195.h | 44 ++
> include/linux/soc/mediatek/dvfsrc.h | 36 ++
> include/linux/soc/mediatek/mtk_sip_svc.h | 3 +
> 19 files changed, 1666 insertions(+), 133 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/interconnect/mediatek,mt8183-emi.yaml
> create mode 100644 Documentation/devicetree/bindings/regulator/mediatek,mt6873-dvfsrc-regulator.yaml
> create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml
> create mode 100644 drivers/interconnect/mediatek/Kconfig
> create mode 100644 drivers/interconnect/mediatek/Makefile
> create mode 100644 drivers/interconnect/mediatek/icc-emi.c
> create mode 100644 drivers/interconnect/mediatek/icc-emi.h
> create mode 100644 drivers/interconnect/mediatek/mt8183.c
> create mode 100644 drivers/interconnect/mediatek/mt8195.c
> create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
> create mode 100644 include/dt-bindings/interconnect/mediatek,mt8183.h
> create mode 100644 include/dt-bindings/interconnect/mediatek,mt8195.h
> create mode 100644 include/linux/soc/mediatek/dvfsrc.h
>
Il 13/06/24 14:38, Georgi Djakov ha scritto:
> On 10.06.24 11:57, AngeloGioacchino Del Regno wrote:
>> Changes in v6:
>> - Fixed build with clang (thanks Nathan!)
>> - Removed unused mtk_rmw() macro in mtk-dvfsrc.c
>> - Added MODULE_DESCRIPTION() to mtk-dvfsrc-regulator.c
>>
> [..]
>>
>> AngeloGioacchino Del Regno (7):
>> dt-bindings: regulator: Add bindings for MediaTek DVFSRC Regulators
>> dt-bindings: interconnect: Add MediaTek EMI Interconnect bindings
>> dt-bindings: soc: mediatek: Add DVFSRC bindings for MT8183 and MT8195
>> soc: mediatek: Add MediaTek DVFS Resource Collector (DVFSRC) driver
>> regulator: Remove mtk-dvfsrc-regulator.c
>> regulator: Add refactored mtk-dvfsrc-regulator driver
>> interconnect: mediatek: Add MediaTek MT8183/8195 EMI Interconnect
>> driver
>
> Thanks Angelo! I have picked patches 2 and 7. Patch 2 is also available
> in my icc-mtk stable branch. Feel free to pull it to resolve the schema
> dependency for patch 3.
>
Thank you Georgi!
I have to wait until Mark takes the regulator bindings and commits, then I will
be able to pick the soc bindings and driver. :-)
Cheers,
Angelo
> BR,
> Georgi
>
>>
>> .../interconnect/mediatek,mt8183-emi.yaml | 51 ++
>> .../mediatek,mt6873-dvfsrc-regulator.yaml | 43 ++
>> .../soc/mediatek/mediatek,mt8183-dvfsrc.yaml | 83 +++
>> drivers/interconnect/Kconfig | 1 +
>> drivers/interconnect/Makefile | 1 +
>> drivers/interconnect/mediatek/Kconfig | 29 +
>> drivers/interconnect/mediatek/Makefile | 5 +
>> drivers/interconnect/mediatek/icc-emi.c | 153 +++++
>> drivers/interconnect/mediatek/icc-emi.h | 40 ++
>> drivers/interconnect/mediatek/mt8183.c | 143 +++++
>> drivers/interconnect/mediatek/mt8195.c | 339 +++++++++++
>> drivers/regulator/mtk-dvfsrc-regulator.c | 248 ++++----
>> drivers/soc/mediatek/Kconfig | 11 +
>> drivers/soc/mediatek/Makefile | 1 +
>> drivers/soc/mediatek/mtk-dvfsrc.c | 545 ++++++++++++++++++
>> .../interconnect/mediatek,mt8183.h | 23 +
>> .../interconnect/mediatek,mt8195.h | 44 ++
>> include/linux/soc/mediatek/dvfsrc.h | 36 ++
>> include/linux/soc/mediatek/mtk_sip_svc.h | 3 +
>> 19 files changed, 1666 insertions(+), 133 deletions(-)
>> create mode 100644
>> Documentation/devicetree/bindings/interconnect/mediatek,mt8183-emi.yaml
>> create mode 100644
>> Documentation/devicetree/bindings/regulator/mediatek,mt6873-dvfsrc-regulator.yaml
>> create mode 100644
>> Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml
>> create mode 100644 drivers/interconnect/mediatek/Kconfig
>> create mode 100644 drivers/interconnect/mediatek/Makefile
>> create mode 100644 drivers/interconnect/mediatek/icc-emi.c
>> create mode 100644 drivers/interconnect/mediatek/icc-emi.h
>> create mode 100644 drivers/interconnect/mediatek/mt8183.c
>> create mode 100644 drivers/interconnect/mediatek/mt8195.c
>> create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
>> create mode 100644 include/dt-bindings/interconnect/mediatek,mt8183.h
>> create mode 100644 include/dt-bindings/interconnect/mediatek,mt8195.h
>> create mode 100644 include/linux/soc/mediatek/dvfsrc.h
>>
>