While testing the linux-next on SM8450-HDK I noticed that one of the
PCIe hosts stays in the deferred state, because the corresponding PHY
isn't probed. A quick debug pointed out that while the patches that
added support for the PIPE AUX clock to the PHY driver have landed,
corresponding DT changes were not picked up for 6.10. Restore the
compatibility with the existing DT files by dropping the second entry in
the clock-output-names array and always generating the corresponding
name on the fly.
To: Vinod Koul <[email protected]>
To: Kishon Vijay Abraham I <[email protected]>
To: Neil Armstrong <[email protected]>
To: Rob Herring <[email protected]>
To: Krzysztof Kozlowski <[email protected]>
To: Conor Dooley <[email protected]>
To: Bjorn Andersson <[email protected]>
To: Konrad Dybcio <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Krzysztof Kozlowski <[email protected]>
Cc: [email protected]
Signed-off-by: Dmitry Baryshkov <[email protected]>
Changes in v3:
- Also added DT bits to remove DT warning
- Link to v2: https://lore.kernel.org/r/[email protected]
Changes in v2:
- Fixed generated AUX clock name (Neil)
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Dmitry Baryshkov (5):
phy: qcom: qmp-pcie: restore compatibility with existing DTs
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: drop second output clock name
arm64: dts: qcom: sm8450: drop second clock name from clock-output-names
arm64: dts: qcom: sm8550: drop second clock name from clock-output-names
arm64: dts: qcom: sm8650: drop second clock name from clock-output-names
.../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 7 +------
arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +-
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 9 +++------
5 files changed, 7 insertions(+), 15 deletions(-)
---
base-commit: 6906a84c482f098d31486df8dc98cead21cce2d0
change-id: 20240521-fix-pcie-phy-compat-b0fd4eb46bda
Best regards,
--
Dmitry Baryshkov <[email protected]>
There is no need to specify exact name for the second (AUX) output
clock. It has never been used for the lookups based on the system clock
name. Partially revert commit 72bea132f368 ("dt-bindings: phy:
qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs"),
returning compatibility with the existing device tree: reduce
clock-output-names to always contain a single entry.
Fixes: 72bea132f368 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs")
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
.../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
index 16634f73bdcf..03dbd02cf9e7 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
@@ -91,8 +91,7 @@ properties:
"#clock-cells": true
clock-output-names:
- minItems: 1
- maxItems: 2
+ maxItems: 1
"#phy-cells":
const: 0
@@ -222,14 +221,10 @@ allOf:
- qcom,sm8650-qmp-gen4x2-pcie-phy
then:
properties:
- clock-output-names:
- minItems: 2
"#clock-cells":
const: 1
else:
properties:
- clock-output-names:
- maxItems: 1
"#clock-cells":
const: 0
--
2.39.2
There is no need to specify exact name for the second (AUX) output
clock. It has never been used for the lookups based on the system
clock name. The driver generates it on its own, in order to remain
compatible with the older DT. Drop the clock name.
Fixes: e76862840660 ("arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc")
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 1e762cc8085a..9bafb3b350ff 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -2087,7 +2087,7 @@ pcie1_phy: phy@1c0e000 {
"rchng",
"pipe";
- clock-output-names = "pcie_1_pipe_clk", "pcie_1_phy_aux_clk";
+ clock-output-names = "pcie_1_pipe_clk";
#clock-cells = <1>;
#phy-cells = <0>;
--
2.39.2
There is no need to specify exact name for the second (AUX) output
clock. It has never been used for the lookups based on the system
clock name. The driver generates it on its own, in order to remain
compatible with the older DT. Drop the clock name.
Fixes: 0cc97d9e3fdf ("arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk")
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 4234c92aafe3..be4f0609c436 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1939,7 +1939,7 @@ pcie1_phy: phy@1c0e000 {
power-domains = <&gcc PCIE_1_PHY_GDSC>;
#clock-cells = <1>;
- clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk";
+ clock-output-names = "pcie1_pipe_clk";
#phy-cells = <0>;
--
2.39.2
Existing device trees specify only a single clock-output-name for the
PCIe PHYs. The function phy_aux_clk_register() expects a second entry in
that property. When it doesn't find it, it returns an error, thus
failing the probe of the PHY and thus breaking support for the
corresponding PCIe host.
Follow the approach of the combo USB+DT PHY and generate the name for
the AUX clocks instead of requiring it in DT.
Fixes: 583ca9ccfa80 ("phy: qcom: qmp-pcie: register second optional PHY AUX clock")
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 8cb91b9114d6..5b36cc7ac78b 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -4033,14 +4033,11 @@ static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np)
{
struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed;
struct clk_init_data init = { };
- int ret;
+ char name[64];
- ret = of_property_read_string_index(np, "clock-output-names", 1, &init.name);
- if (ret) {
- dev_err(qmp->dev, "%pOFn: No clock-output-names index 1\n", np);
- return ret;
- }
+ snprintf(name, sizeof(name), "%s::phy_aux_clk", dev_name(qmp->dev));
+ init.name = name;
init.ops = &clk_fixed_rate_ops;
fixed->fixed_rate = qmp->cfg->aux_clock_rate;
--
2.39.2
There is no need to specify exact name for the second (AUX) output
clock. It has never been used for the lookups based on the system
clock name. The driver generates it on its own, in order to remain
compatible with the older DT. Drop the clock name.
Fixes: d00b42f170df ("arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk")
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 5b8b1d581a13..5df2e00fdb5b 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2474,7 +2474,7 @@ pcie1_phy: phy@1c0e000 {
power-domains = <&gcc PCIE_1_PHY_GDSC>;
#clock-cells = <1>;
- clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk";
+ clock-output-names = "pcie1_pipe_clk";
#phy-cells = <0>;
--
2.39.2
On 14/06/2024 12:18, Dmitry Baryshkov wrote:
> There is no need to specify exact name for the second (AUX) output
> clock. It has never been used for the lookups based on the system
> clock name. The driver generates it on its own, in order to remain
> compatible with the older DT. Drop the clock name.
>
> Fixes: e76862840660 ("arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc")
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 1e762cc8085a..9bafb3b350ff 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -2087,7 +2087,7 @@ pcie1_phy: phy@1c0e000 {
> "rchng",
> "pipe";
>
> - clock-output-names = "pcie_1_pipe_clk", "pcie_1_phy_aux_clk";
> + clock-output-names = "pcie_1_pipe_clk";
> #clock-cells = <1>;
>
> #phy-cells = <0>;
>
Reviewed-by: Neil Armstrong <[email protected]>
On 14/06/2024 12:18, Dmitry Baryshkov wrote:
> There is no need to specify exact name for the second (AUX) output
> clock. It has never been used for the lookups based on the system
> clock name. The driver generates it on its own, in order to remain
> compatible with the older DT. Drop the clock name.
>
> Fixes: 0cc97d9e3fdf ("arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk")
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 4234c92aafe3..be4f0609c436 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1939,7 +1939,7 @@ pcie1_phy: phy@1c0e000 {
> power-domains = <&gcc PCIE_1_PHY_GDSC>;
>
> #clock-cells = <1>;
> - clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk";
> + clock-output-names = "pcie1_pipe_clk";
>
> #phy-cells = <0>;
>
>
Reviewed-by: Neil Armstrong <[email protected]>
On 14/06/2024 12:18, Dmitry Baryshkov wrote:
> There is no need to specify exact name for the second (AUX) output
> clock. It has never been used for the lookups based on the system
> clock name. The driver generates it on its own, in order to remain
> compatible with the older DT. Drop the clock name.
>
> Fixes: d00b42f170df ("arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk")
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index 5b8b1d581a13..5df2e00fdb5b 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -2474,7 +2474,7 @@ pcie1_phy: phy@1c0e000 {
> power-domains = <&gcc PCIE_1_PHY_GDSC>;
>
> #clock-cells = <1>;
> - clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk";
> + clock-output-names = "pcie1_pipe_clk";
>
> #phy-cells = <0>;
>
>
Reviewed-by: Neil Armstrong <[email protected]>
On Fri, 14 Jun 2024 13:18:23 +0300, Dmitry Baryshkov wrote:
> While testing the linux-next on SM8450-HDK I noticed that one of the
> PCIe hosts stays in the deferred state, because the corresponding PHY
> isn't probed. A quick debug pointed out that while the patches that
> added support for the PIPE AUX clock to the PHY driver have landed,
> corresponding DT changes were not picked up for 6.10. Restore the
> compatibility with the existing DT files by dropping the second entry in
> the clock-output-names array and always generating the corresponding
> name on the fly.
>
> [...]
Applied, thanks!
[1/5] phy: qcom: qmp-pcie: restore compatibility with existing DTs
commit: 912cee11c14376a6f707d72fcaf343a40bff48e8
[2/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: drop second output clock name
commit: 7cd3e586068aca123ff244fc259ba62ba96b6d31
[3/5] arm64: dts: qcom: sm8450: drop second clock name from clock-output-names
(no commit info)
[4/5] arm64: dts: qcom: sm8550: drop second clock name from clock-output-names
(no commit info)
[5/5] arm64: dts: qcom: sm8650: drop second clock name from clock-output-names
(no commit info)
Best regards,
--
Vinod Koul <[email protected]>