This series includes RISC-V IOMMU hardware performance monitor and
nested IOMMU support. It also introduces more operations, which are
required for nested IOMMU, such as g-stage flush and iotlb_sync_map.
This patch needs an additional patch from Robin Murphy to support
MSIs through nested domains (e.g., patch 09/10).
This patch set is implemented on top of the RISC-V IOMMU v7 series [1],
and tested on top of more features support [2] with some suggestions
[3]. This patch serie will be submitted as an RFC until the RISC-V
IOMMU has been merged.
Changes from v1:
- Rebase on RISC-V IOMMU v7 series
- Include patch for supporting MSIs through nested domains
- Iterate bond list for g-stage flush
- Use data structure instead of passing individual parameters
- PMU: adds IRQ_ONESHOT and SHARED flags for shared wired interrupt
- PMU: add mask of counter
- hw_info: remove unused check
- hw_info: add padding in data structure
- hw_info: add more comments for data structure
- cache_invalidate_user: remove warning message from userspace
- cache_invalidate_user: lock a riscv iommu device in riscv iommu domain
- cache_invalidate_user: link pass through device to s2 domain's bond
list
[1] link: https://lists.infradead.org/pipermail/linux-riscv/2024-June/055413.html
[2] link: https://github.com/tjeznach/linux/tree/riscv_iommu_v7-rc2
[3] link: https://lists.infradead.org/pipermail/linux-riscv/2024-June/055426.html
Robin Murphy (1):
iommu/dma: Support MSIs through nested domains
Zong Li (9):
iommu/riscv: add RISC-V IOMMU PMU support
iommu/riscv: support HPM and interrupt handling
iommu/riscv: use data structure instead of individual values
iommu/riscv: add iotlb_sync_map operation support
iommu/riscv: support GSCID and GVMA invalidation command
iommu/riscv: support nested iommu for getting iommu hardware
information
iommu/riscv: support nested iommu for creating domains owned by
userspace
iommu/riscv: support nested iommu for flushing cache
iommu:riscv: support nested iommu for get_msi_mapping_domain operation
drivers/iommu/dma-iommu.c | 18 +-
drivers/iommu/riscv/Makefile | 3 +-
drivers/iommu/riscv/iommu-bits.h | 23 ++
drivers/iommu/riscv/iommu-pmu.c | 479 ++++++++++++++++++++++++++++++
drivers/iommu/riscv/iommu.c | 492 ++++++++++++++++++++++++++++++-
drivers/iommu/riscv/iommu.h | 8 +
include/linux/iommu.h | 4 +
include/uapi/linux/iommufd.h | 46 +++
8 files changed, 1054 insertions(+), 19 deletions(-)
create mode 100644 drivers/iommu/riscv/iommu-pmu.c
--
2.17.1
This patch initialize the pmu stuff and uninitialize it when driver
removing. The interrupt handling is also provided, this handler need to
be primary handler instead of thread function, because pt_regs is empty
when threading the IRQ, but pt_regs is necessary by perf_event_overflow.
Signed-off-by: Zong Li <[email protected]>
---
drivers/iommu/riscv/iommu.c | 65 +++++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
index 8b6a64c1ad8d..1716b2251f38 100644
--- a/drivers/iommu/riscv/iommu.c
+++ b/drivers/iommu/riscv/iommu.c
@@ -540,6 +540,62 @@ static irqreturn_t riscv_iommu_fltq_process(int irq, void *data)
return IRQ_HANDLED;
}
+/*
+ * IOMMU Hardware performance monitor
+ */
+
+/* HPM interrupt primary handler */
+static irqreturn_t riscv_iommu_hpm_irq_handler(int irq, void *dev_id)
+{
+ struct riscv_iommu_device *iommu = (struct riscv_iommu_device *)dev_id;
+
+ /* Process pmu irq */
+ riscv_iommu_pmu_handle_irq(&iommu->pmu);
+
+ /* Clear performance monitoring interrupt pending */
+ riscv_iommu_writel(iommu, RISCV_IOMMU_REG_IPSR, RISCV_IOMMU_IPSR_PMIP);
+
+ return IRQ_HANDLED;
+}
+
+/* HPM initialization */
+static int riscv_iommu_hpm_enable(struct riscv_iommu_device *iommu)
+{
+ int rc;
+
+ if (!(iommu->caps & RISCV_IOMMU_CAPABILITIES_HPM))
+ return 0;
+
+ /*
+ * pt_regs is empty when threading the IRQ, but pt_regs is necessary
+ * by perf_event_overflow. Use primary handler instead of thread
+ * function for PM IRQ.
+ *
+ * Set the IRQF_ONESHOT flag because this IRQ might be shared with
+ * other threaded IRQs by other queues.
+ */
+ rc = devm_request_irq(iommu->dev,
+ iommu->irqs[riscv_iommu_queue_vec(iommu, RISCV_IOMMU_IPSR_PMIP)],
+ riscv_iommu_hpm_irq_handler, IRQF_ONESHOT | IRQF_SHARED, NULL, iommu);
+ if (rc)
+ return rc;
+
+ return riscv_iommu_pmu_init(&iommu->pmu, iommu->reg, dev_name(iommu->dev));
+}
+
+/* HPM uninitialization */
+static void riscv_iommu_hpm_disable(struct riscv_iommu_device *iommu)
+{
+ if (!(iommu->caps & RISCV_IOMMU_CAPABILITIES_HPM))
+ return;
+
+ devm_free_irq(iommu->dev,
+ iommu->irqs[riscv_iommu_queue_vec(iommu, RISCV_IOMMU_IPSR_PMIP)],
+ iommu);
+
+ riscv_iommu_pmu_uninit(&iommu->pmu);
+}
+
/* Lookup and initialize device context info structure. */
static struct riscv_iommu_dc *riscv_iommu_get_dc(struct riscv_iommu_device *iommu,
unsigned int devid)
@@ -1612,6 +1668,9 @@ void riscv_iommu_remove(struct riscv_iommu_device *iommu)
riscv_iommu_iodir_set_mode(iommu, RISCV_IOMMU_DDTP_IOMMU_MODE_OFF);
riscv_iommu_queue_disable(&iommu->cmdq);
riscv_iommu_queue_disable(&iommu->fltq);
+
+ if (iommu->caps & RISCV_IOMMU_CAPABILITIES_HPM)
+ riscv_iommu_pmu_uninit(&iommu->pmu);
}
int riscv_iommu_init(struct riscv_iommu_device *iommu)
@@ -1651,6 +1710,10 @@ int riscv_iommu_init(struct riscv_iommu_device *iommu)
if (rc)
goto err_queue_disable;
+ rc = riscv_iommu_hpm_enable(iommu);
+ if (rc)
+ goto err_hpm_disable;
+
rc = iommu_device_sysfs_add(&iommu->iommu, NULL, NULL, "riscv-iommu@%s",
dev_name(iommu->dev));
if (rc) {
@@ -1669,6 +1732,8 @@ int riscv_iommu_init(struct riscv_iommu_device *iommu)
err_remove_sysfs:
iommu_device_sysfs_remove(&iommu->iommu);
err_iodir_off:
+ riscv_iommu_hpm_disable(iommu);
+err_hpm_disable:
riscv_iommu_iodir_set_mode(iommu, RISCV_IOMMU_DDTP_IOMMU_MODE_OFF);
err_queue_disable:
riscv_iommu_queue_disable(&iommu->fltq);
--
2.17.1