Thosre are the only missing parts for PCI to work on HiKey970 and
for USB on HiKey960 and HiKey 970 boards.
-
v2:
- patch 1: fixed port description for the USB hub;
- patch 2: added an ack;
- patch 3: is now dual-licensed, and had some renames;
- patch 4: changed accordingly.
John Stultz (1):
arm64: dts: hisilicon: Add usb mux hub for hikey960
Manivannan Sadhasivam (1):
arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller
hardware
Mauro Carvalho Chehab (4):
dt-bindings: clock: hi3670-clock.txt: add pmctrl compatible
dt-bindings: usb: hisilicon,hi3670-dwc3: add binding for Kirin970
arm64: dts: hisilicon: Add support for Hikey 970 USB3 PHY
arm64: dts: hisilicon: Add usb mux hub for hikey970
Yu Chen (1):
dt-bindings: misc: add schema for USB hub on Kirin devices
.../bindings/clock/hi3670-clock.txt | 1 +
.../bindings/misc/hisilicon,hikey-usb.yaml | 84 +++++++++
.../bindings/usb/hisilicon,hi3670-dwc3.yaml | 105 +++++++++++
.../boot/dts/hisilicon/hi3660-hikey960.dts | 35 +++-
.../boot/dts/hisilicon/hi3670-hikey970.dts | 106 ++++++++++++
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 163 ++++++++++++++++++
6 files changed, 492 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/misc/hisilicon,hikey-usb.yaml
create mode 100644 Documentation/devicetree/bindings/usb/hisilicon,hi3670-dwc3.yaml
--
2.33.1
From: Mauro Carvalho Chehab <[email protected]>
Add dt bindings for Kirin 970 USB HUB. Such board comes with an
integrated USB HUB provided via a TI TUSB8041 4-port USB 3.0 hub.
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
---
See [PATCH v2 0/7] at: https://lore.kernel.org/all/[email protected]/
.../boot/dts/hisilicon/hi3670-hikey970.dts | 23 +++++++++++++++++++
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 10 ++++----
2 files changed, 28 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
index 60594db07041..95ca49f1e455 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
@@ -53,6 +53,29 @@ wlan_en: wlan-en-1-8v {
startup-delay-us = <70000>;
enable-active-high;
};
+
+ usb-hub {
+ compatible = "hisilicon,usbhub";
+ typec-vbus-gpios = <&gpio26 1 0>;
+ otg-switch-gpios = <&gpio4 2 0>;
+ hub-reset-en-gpios = <&gpio0 3 0>;
+ hub-vdd-supply = <&ldo17>;
+ usb-role-switch;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hikey_usb_ep0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dwc3_role_switch>;
+ };
+ hikey_usb_ep1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&rt1711h_ep>;
+ };
+ };
+ };
};
/*
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index b47654b50139..486dc93ab47b 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -915,7 +915,7 @@ usb31_misc_rst: usb31_misc_rst_controller {
hisi,rst-syscon = <&usb3_otg_bc>;
};
- usb3: hisi_dwc3 {
+ usb3: dwc3 {
compatible = "hisilicon,hi3670-dwc3";
#address-cells = <2>;
#size-cells = <2>;
@@ -925,10 +925,10 @@ usb3: hisi_dwc3 {
<&crg_ctrl HI3670_HCLK_GATE_USB3OTG>,
<&crg_ctrl HI3670_CLK_GATE_USB3OTG_REF>,
<&crg_ctrl HI3670_ACLK_GATE_USB3DVFS>;
- clock-names = "clk_gate_abb_usb",
- "hclk_gate_usb3otg",
- "clk_gate_usb3otg_ref",
- "aclk_gate_usb3dvfs";
+ clock-names = "abb",
+ "hclk",
+ "ref",
+ "aclk";
assigned-clocks = <&crg_ctrl HI3670_ACLK_GATE_USB3DVFS>;
assigned-clock-rates = <238000000>;
--
2.33.1
From: Yu Chen <[email protected]>
This patch adds binding documentation to support USB HUB and
USB data role switch of HiSilicon HiKey960 and HiKey970 boards.
[mchehab: updated OF schema and added HiKey970 example]
Signed-off-by: Yu Chen <[email protected]>
Signed-off-by: John Stultz <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
---
See [PATCH v2 0/7] at: https://lore.kernel.org/all/[email protected]/
.../bindings/misc/hisilicon,hikey-usb.yaml | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/hisilicon,hikey-usb.yaml
diff --git a/Documentation/devicetree/bindings/misc/hisilicon,hikey-usb.yaml b/Documentation/devicetree/bindings/misc/hisilicon,hikey-usb.yaml
new file mode 100644
index 000000000000..208c49478f1f
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/hisilicon,hikey-usb.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 Linaro Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/hisilicon,hikey-usb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiKey960/970 onboard USB GPIO Hub
+
+maintainers:
+ - John Stultz <[email protected]>
+
+description: |
+ Supports the onboard USB GPIO hubs found on HiKey960/970.
+ Such hubs require a power supply for the USB I/O. Depending on the
+ exact hub model, after USB I/O is powered up, a reset should be needed.
+
+ It also acts as a role-switch intermediary to detect the state of
+ the USB-C port, to switch the hub into dual-role USB-C or host mode,
+ which enables and powers up the onboard USB-A host ports.
+
+ Schematics about such hubs can be found here:
+ https://github.com/96boards/documentation/raw/master/consumer/hikey/hikey960/hardware-docs/HiKey960_Schematics.pdf
+ https://www.96boards.org/documentation/consumer/hikey/hikey970/hardware-docs/files/hikey970-schematics.pdf
+
+properties:
+ compatible:
+ enum:
+ - hisilicon,usbhub
+
+ typec-vbus-gpios:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: phandle to the typec-vbus gpio
+
+ otg-switch-gpios:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: phandle to the otg-switch gpio
+
+ hub-reset-en-gpios:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: phandle to the hub reset gpio
+
+ usb-role-switch:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Support role switch.
+
+ hub-vdd-supply:
+ description: regulator for hub power
+
+ port:
+ description: |
+ describe a USB port and its endpoints.
+
+required:
+ - compatible
+ - hub-vdd-supply
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ usb-hub {
+ compatible = "hisilicon,usbhub";
+ typec-vbus-gpios = <&gpio25 2 GPIO_ACTIVE_HIGH>;
+ otg-switch-gpios = <&gpio25 6 GPIO_ACTIVE_HIGH>;
+ hub-reset-en-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+ hub-vdd-supply = <&usb_hub_vdd>;
+ usb-role-switch;
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ usb_ep0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dwc3_role_switch>;
+ };
+ usb_ep1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&rt1711h_ep>;
+ };
+ };
+ };
--
2.33.1
From: Mauro Carvalho Chehab <[email protected]>
Add the USB3 bindings for Kirin 970 phy and Hikey 970 board.
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
---
See [PATCH v2 0/7] at: https://lore.kernel.org/all/[email protected]/
.../boot/dts/hisilicon/hi3670-hikey970.dts | 83 +++++++++++++++++++
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 56 +++++++++++++
2 files changed, 139 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
index 7c32f5fd5cc5..60594db07041 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
@@ -430,3 +430,86 @@ &uart6 {
label = "LS-UART1";
status = "okay";
};
+
+&usb_phy {
+ phy-supply = <&ldo17>;
+};
+
+&i2c1 {
+ status = "okay";
+
+ rt1711h: rt1711h@4e {
+ compatible = "richtek,rt1711h";
+ reg = <0x4e>;
+ status = "okay";
+ interrupt-parent = <&gpio27>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_cfg_func>;
+
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+ power-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 500, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 500, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 5000, 1000)>;
+ op-sink-microwatt = <10000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@1 {
+ reg = <1>;
+ usb_con_ss: endpoint {
+ remote-endpoint = <&dwc3_ss>;
+ };
+ };
+ };
+ };
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rt1711h_ep: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&hikey_usb_ep1>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ /* USB HUB is on this bus at address 0x44 */
+ status = "okay";
+};
+
+&dwc3 { /* USB */
+ dr_mode = "otg";
+ maximum-speed = "super-speed";
+ phy_type = "utmi";
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,tx_de_emphasis_quirk;
+ snps,tx_de_emphasis = <1>;
+ snps,dis-split-quirk;
+ snps,gctl-reset-quirk;
+ usb-role-switch;
+ role-switch-default-mode = "host";
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dwc3_role_switch: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&hikey_usb_ep0>;
+ };
+
+ dwc3_ss: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&usb_con_ss>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 636c8817df7e..782e1487666d 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/hi3670-clock.h>
+#include <dt-bindings/usb/pd.h>
/ {
compatible = "hisilicon,hi3670";
@@ -785,5 +786,60 @@ i2c4: i2c@fdf0d000 {
pinctrl-0 = <&i2c4_pmx_func &i2c4_cfg_func>;
status = "disabled";
};
+
+ usb3_otg_bc: usb3_otg_bc@ff200000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x0 0xff200000 0x0 0x1000>;
+
+ usb_phy: usbphy {
+ compatible = "hisilicon,hi3670-usb-phy";
+ #phy-cells = <0>;
+ hisilicon,pericrg-syscon = <&crg_ctrl>;
+ hisilicon,pctrl-syscon = <&pctrl>;
+ hisilicon,sctrl-syscon = <&sctrl>;
+ hisilicon,eye-diagram-param = <0xFDFEE4>;
+ hisilicon,tx-vboost-lvl = <0x5>;
+ };
+ };
+
+ usb31_misc_rst: usb31_misc_rst_controller {
+ compatible = "hisilicon,hi3660-reset";
+ #reset-cells = <2>;
+ hisi,rst-syscon = <&usb3_otg_bc>;
+ };
+
+ usb3: hisi_dwc3 {
+ compatible = "hisilicon,hi3670-dwc3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&crg_ctrl HI3670_CLK_GATE_ABB_USB>,
+ <&crg_ctrl HI3670_HCLK_GATE_USB3OTG>,
+ <&crg_ctrl HI3670_CLK_GATE_USB3OTG_REF>,
+ <&crg_ctrl HI3670_ACLK_GATE_USB3DVFS>;
+ clock-names = "clk_gate_abb_usb",
+ "hclk_gate_usb3otg",
+ "clk_gate_usb3otg_ref",
+ "aclk_gate_usb3dvfs";
+
+ assigned-clocks = <&crg_ctrl HI3670_ACLK_GATE_USB3DVFS>;
+ assigned-clock-rates = <238000000>;
+ resets = <&crg_rst 0x90 6>,
+ <&crg_rst 0x90 7>,
+ <&usb31_misc_rst 0xA0 8>,
+ <&usb31_misc_rst 0xA0 9>;
+
+ dwc3: usb@ff100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff100000 0x0 0x100000>;
+
+ interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>,
+ <0 161 IRQ_TYPE_LEVEL_HIGH>;
+
+ phys = <&usb_phy>;
+ phy-names = "usb3-phy";
+ };
+ };
};
};
--
2.33.1
From: Manivannan Sadhasivam <[email protected]>
Add DTS bindings for the HiKey 970 board's PCIe hardware.
Co-developed-by: Mauro Carvalho Chehab <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
---
See [PATCH v2 0/7] at: https://lore.kernel.org/all/[email protected]/
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 107 ++++++++++++++++++++++
1 file changed, 107 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 782e1487666d..b47654b50139 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 {
#clock-cells = <1>;
};
+ pmctrl: pmctrl@fff31000 {
+ compatible = "hisilicon,hi3670-pmctrl", "syscon";
+ reg = <0x0 0xfff31000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
iomcu: iomcu@ffd7e000 {
compatible = "hisilicon,hi3670-iomcu", "syscon";
reg = <0x0 0xffd7e000 0x0 0x1000>;
@@ -660,6 +666,107 @@ gpio28: gpio@fff1d000 {
clock-names = "apb_pclk";
};
+ pcie_phy: pcie-phy@fc000000 {
+ compatible = "hisilicon,hi970-pcie-phy";
+ reg = <0x0 0xfc000000 0x0 0x80000>;
+
+ phy-supply = <&ldo33>;
+
+ clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>,
+ <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3670_ACLK_GATE_PCIE>;
+ clock-names = "phy_ref", "aux",
+ "apb_phy", "apb_sys",
+ "aclk";
+
+ /* vboost iboost pre post main */
+ hisilicon,eye-diagram-param = <0xffffffff 0xffffffff
+ 0xffffffff 0xffffffff
+ 0xffffffff>;
+
+ #phy-cells = <0>;
+ };
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin970-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000000>,
+ <0x0 0xfc180000 0x0 0x1000>,
+ <0x0 0xf5000000 0x0 0x2000>;
+ reg-names = "dbi", "apb", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ phys = <&pcie_phy>;
+ ranges = <0x02000000 0x0 0x00000000
+ 0x0 0xf6000000
+ 0x0 0x02000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0x0 0 0 1
+ &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 2
+ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 3
+ &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 4
+ &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ reset-gpios = <&gpio7 0 0>;
+ hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>,
+ <&gpio20 6 0>;
+ pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0
+ reg = <0 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ pcie@0,0 { // Lane 0: upstream
+ reg = <0 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ pcie@1,0 { // Lane 4: M.2
+ reg = <0x0800 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reset-gpios = <&gpio3 1 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+
+ pcie@5,0 { // Lane 5: Mini PCIe
+ reg = <0x2800 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reset-gpios = <&gpio27 4 0 >;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+
+ pcie@7,0 { // Lane 6: Ethernet
+ reg = <0x3800 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reset-gpios = <&gpio25 2 0 >;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+ };
+ };
+
/* UFS */
ufs: ufs@ff3c0000 {
compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
--
2.33.1