This patchset adds PWM-DAC audio support for the StarFive JH7110 SoC.
The PWM-DAC module does not require a hardware codec, so add a dummy codec
driver for it.
The fourth patch depends on the patch [1].
The fifth patch depends on the patchset [2], patch [3].
[1] https://lore.kernel.org/all/[email protected]/
[2] https://lore.kernel.org/all/[email protected]/
[3] https://lore.kernel.org/all/[email protected]/
Hal Feng (5):
ASoC: dt-bindings: Add StarFive JH7110 dummy PWM-DAC transmitter
ASoC: codecs: Add StarFive JH7110 dummy PWM-DAC transmitter driver
ASoC: dt-bindings: Add StarFive JH7110 PWM-DAC controller
ASoC: starfive: Add JH7110 PWM-DAC driver
riscv: dts: starfive: Add JH7110 PWM-DAC support
.../sound/starfive,jh7110-pwmdac-dit.yaml | 38 +
.../sound/starfive,jh7110-pwmdac.yaml | 76 ++
MAINTAINERS | 8 +
.../jh7110-starfive-visionfive-2.dtsi | 50 ++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 13 +
sound/soc/codecs/Kconfig | 4 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/jh7110_pwmdac_transmitter.c | 74 ++
sound/soc/starfive/Kconfig | 9 +
sound/soc/starfive/Makefile | 1 +
sound/soc/starfive/jh7110_pwmdac.c | 787 ++++++++++++++++++
11 files changed, 1062 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/starfive,jh7110-pwmdac-dit.yaml
create mode 100644 Documentation/devicetree/bindings/sound/starfive,jh7110-pwmdac.yaml
create mode 100644 sound/soc/codecs/jh7110_pwmdac_transmitter.c
create mode 100644 sound/soc/starfive/jh7110_pwmdac.c
base-commit: 45a3e24f65e90a047bef86f927ebdc4c710edaa1
prerequisite-patch-id: 8c735dffc6d5388a35a76b16e914a2f9722ad979
prerequisite-patch-id: ffa1f5831e75722c9f41603f009f762c9fd525e2
prerequisite-patch-id: 36e69700dfc0375b950b0e23086ed3b722cb84a4
prerequisite-patch-id: 0b49b996d7a404ea548e1734c12933ec749e92b9
prerequisite-patch-id: 81f7c65712c4901a7a178ddcd98ffc55f3b473ff
prerequisite-patch-id: f342fbf594014b072378528bea94c01fb2186e1a
prerequisite-patch-id: 39e1be2a3d1593577ab997f55f59367cba665aa7
prerequisite-patch-id: 0159f09bb0a1ff711a00ae17ef5b12662c9c7d3d
prerequisite-patch-id: 2ddada18ab6ea5cd1da14212aaf59632f5203d40
prerequisite-patch-id: d5abfba63fc07ff97b5023911513c260bb7a53e1
prerequisite-patch-id: b37ac15032973e1fcd918f157c82a0606775c9e9
prerequisite-patch-id: 6abf359fa445f4104432ddee27044dfbfb128417
prerequisite-patch-id: 2f7aca99e714a4c590a91baa015080ac0902814d
prerequisite-patch-id: 32cabbc4e7a97ec14d5c28a477fa483784f86709
prerequisite-patch-id: d449b1957dd77c2537c38585daa75974c94c529a
--
2.38.1
Add PWM-DAC driver support for the StarFive JH7110 SoC.
Signed-off-by: Hal Feng <[email protected]>
---
MAINTAINERS | 8 +
sound/soc/starfive/Kconfig | 9 +
sound/soc/starfive/Makefile | 1 +
sound/soc/starfive/jh7110_pwmdac.c | 787 +++++++++++++++++++++++++++++
4 files changed, 805 insertions(+)
create mode 100644 sound/soc/starfive/jh7110_pwmdac.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 1dc12c5c02f7..a936ba4d5f1d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20125,6 +20125,14 @@ S: Supported
F: Documentation/devicetree/bindings/mmc/starfive*
F: drivers/mmc/host/dw_mmc-starfive.c
+STARFIVE JH7110 PWMDAC DRIVER
+M: Hal Feng <[email protected]>
+M: Xingyu Wu <[email protected]>
+S: Supported
+F: Documentation/devicetree/bindings/sound/starfive,jh7110-pwmdac*
+F: sound/soc/codecs/jh7110_pwmdac_transmitter.c
+F: sound/soc/starfive/jh7110_pwmdac.c
+
STARFIVE JH71X0 CLOCK DRIVERS
M: Emil Renner Berthing <[email protected]>
M: Hal Feng <[email protected]>
diff --git a/sound/soc/starfive/Kconfig b/sound/soc/starfive/Kconfig
index fafb681f8c0a..fabef377db8c 100644
--- a/sound/soc/starfive/Kconfig
+++ b/sound/soc/starfive/Kconfig
@@ -7,6 +7,15 @@ config SND_SOC_STARFIVE
the Starfive SoCs' Audio interfaces. You will also need to
select the audio interfaces to support below.
+config SND_SOC_JH7110_PWMDAC
+ tristate "JH7110 PWM-DAC device driver"
+ depends on HAVE_CLK && SND_SOC_STARFIVE
+ select SND_SOC_GENERIC_DMAENGINE_PCM
+ select SND_SOC_JH7110_PWMDAC_DIT
+ help
+ Say Y or M if you want to add support for StarFive JH7110
+ PWM-DAC driver.
+
config SND_SOC_JH7110_TDM
tristate "JH7110 TDM device driver"
depends on HAVE_CLK && SND_SOC_STARFIVE
diff --git a/sound/soc/starfive/Makefile b/sound/soc/starfive/Makefile
index f7d960211d72..9e958f70ef51 100644
--- a/sound/soc/starfive/Makefile
+++ b/sound/soc/starfive/Makefile
@@ -1,2 +1,3 @@
# StarFive Platform Support
+obj-$(CONFIG_SND_SOC_JH7110_PWMDAC) += jh7110_pwmdac.o
obj-$(CONFIG_SND_SOC_JH7110_TDM) += jh7110_tdm.o
diff --git a/sound/soc/starfive/jh7110_pwmdac.c b/sound/soc/starfive/jh7110_pwmdac.c
new file mode 100644
index 000000000000..c3123bd6ea45
--- /dev/null
+++ b/sound/soc/starfive/jh7110_pwmdac.c
@@ -0,0 +1,787 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * jh7110_pwmdac.c -- StarFive JH7110 PWM-DAC driver
+ *
+ * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
+ *
+ * Authors: Jenny Zhang
+ * Curry Zhang
+ * Xingyu Wu <[email protected]>
+ * Hal Feng <[email protected]>
+ */
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <sound/dmaengine_pcm.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#define JH7110_PWMDAC_WDATA 0x00
+#define JH7110_PWMDAC_CTRL 0x04
+ #define JH7110_PWMDAC_ENABLE BIT(0)
+ #define JH7110_PWMDAC_SHIFT BIT(1)
+ #define JH7110_PWMDAC_DUTY_CYCLE_SHIFT 2
+ #define JH7110_PWMDAC_DUTY_CYCLE_MASK GENMASK(3, 2)
+ #define JH7110_PWMDAC_CNT_N_SHIFT 4
+ #define JH7110_PWMDAC_CNT_N_MASK GENMASK(12, 4)
+ #define JH7110_PWMDAC_DATA_CHANGE BIT(13)
+ #define JH7110_PWMDAC_DATA_MODE BIT(14)
+ #define JH7110_PWMDAC_DATA_SHIFT_SHIFT 15
+ #define JH7110_PWMDAC_DATA_SHIFT_MASK GENMASK(17, 15)
+
+enum JH7110_PWMDAC_SHIFT_VAL {
+ PWMDAC_SHIFT_8 = 0,
+ PWMDAC_SHIFT_10,
+};
+
+enum JH7110_PWMDAC_DUTY_CYCLE_VAL {
+ PWMDAC_CYCLE_LEFT = 0,
+ PWMDAC_CYCLE_RIGHT,
+ PWMDAC_CYCLE_CENTER,
+};
+
+enum JH7110_PWMDAC_CNT_N_VAL {
+ PWMDAC_SAMPLE_CNT_1 = 1,
+ PWMDAC_SAMPLE_CNT_2,
+ PWMDAC_SAMPLE_CNT_3,
+ PWMDAC_SAMPLE_CNT_512 = 512, /* max */
+};
+
+enum JH7110_PWMDAC_DATA_CHANGE_VAL {
+ NO_CHANGE = 0,
+ CHANGE,
+};
+
+enum JH7110_PWMDAC_DATA_MODE_VAL {
+ UNSIGNED_DATA = 0,
+ INVERTER_DATA_MSB,
+};
+
+enum JH7110_PWMDAC_DATA_SHIFT_VAL {
+ PWMDAC_DATA_LEFT_SHIFT_BIT_0 = 0,
+ PWMDAC_DATA_LEFT_SHIFT_BIT_1,
+ PWMDAC_DATA_LEFT_SHIFT_BIT_2,
+ PWMDAC_DATA_LEFT_SHIFT_BIT_3,
+ PWMDAC_DATA_LEFT_SHIFT_BIT_4,
+ PWMDAC_DATA_LEFT_SHIFT_BIT_5,
+ PWMDAC_DATA_LEFT_SHIFT_BIT_6,
+ PWMDAC_DATA_LEFT_SHIFT_BIT_7,
+};
+
+struct jh7110_pwmdac_dev {
+ void __iomem *base;
+ resource_size_t mapbase;
+ u8 shift;
+ u8 duty_cycle;
+ u8 cnt_n;
+ u8 data_change;
+ u8 data_mode;
+ u8 data_shift;
+
+ struct clk_bulk_data clks[2];
+ struct reset_control *rst_apb;
+ struct device *dev;
+ struct snd_dmaengine_dai_dma_data play_dma_data;
+ u32 saved_ctrl;
+};
+
+enum jh7110_ct_pwmdac_name {
+ PWMDAC_CT_SHIFT = 0,
+ PWMDAC_CT_DUTY_CYCLE,
+ PWMDAC_CT_DATA_CHANGE,
+ PWMDAC_CT_DATA_MODE,
+ PWMDAC_CT_DATA_SHIFT,
+};
+
+struct jh7110_ct_pwmdac {
+ char *name;
+ unsigned int vals;
+};
+
+static const struct jh7110_ct_pwmdac pwmdac_ct_shift[] = {
+ { .name = "8bit", .vals = PWMDAC_SHIFT_8 },
+ { .name = "10bit", .vals = PWMDAC_SHIFT_10 }
+};
+
+static const struct jh7110_ct_pwmdac pwmdac_ct_duty_cycle[] = {
+ { .name = "left", .vals = PWMDAC_CYCLE_LEFT },
+ { .name = "right", .vals = PWMDAC_CYCLE_RIGHT },
+ { .name = "center", .vals = PWMDAC_CYCLE_CENTER }
+};
+
+static const struct jh7110_ct_pwmdac pwmdac_ct_data_change[] = {
+ { .name = "no_change", .vals = NO_CHANGE },
+ { .name = "change", .vals = CHANGE }
+};
+
+static const struct jh7110_ct_pwmdac pwmdac_ct_data_mode[] = {
+ { .name = "unsigned", .vals = UNSIGNED_DATA },
+ { .name = "inverter", .vals = INVERTER_DATA_MSB }
+};
+
+static const struct jh7110_ct_pwmdac pwmdac_ct_data_shift[] = {
+ { .name = "left 0 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_0 },
+ { .name = "left 1 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_1 },
+ { .name = "left 2 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_2 },
+ { .name = "left 3 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_3 },
+ { .name = "left 4 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_4 },
+ { .name = "left 5 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_5 },
+ { .name = "left 6 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_6 },
+ { .name = "left 7 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_7 }
+};
+
+static int jh7110_pwmdac_info(struct snd_ctl_elem_info *uinfo, int pwmdac_ct)
+{
+ unsigned int items;
+
+ if (pwmdac_ct == PWMDAC_CT_SHIFT) {
+ items = ARRAY_SIZE(pwmdac_ct_shift);
+ strcpy(uinfo->value.enumerated.name,
+ pwmdac_ct_shift[uinfo->value.enumerated.item].name);
+ } else if (pwmdac_ct == PWMDAC_CT_DUTY_CYCLE) {
+ items = ARRAY_SIZE(pwmdac_ct_duty_cycle);
+ strcpy(uinfo->value.enumerated.name,
+ pwmdac_ct_duty_cycle[uinfo->value.enumerated.item].name);
+ } else if (pwmdac_ct == PWMDAC_CT_DATA_CHANGE) {
+ items = ARRAY_SIZE(pwmdac_ct_data_change);
+ strcpy(uinfo->value.enumerated.name,
+ pwmdac_ct_data_change[uinfo->value.enumerated.item].name);
+ } else if (pwmdac_ct == PWMDAC_CT_DATA_MODE) {
+ items = ARRAY_SIZE(pwmdac_ct_data_mode);
+ strcpy(uinfo->value.enumerated.name,
+ pwmdac_ct_data_mode[uinfo->value.enumerated.item].name);
+ } else if (pwmdac_ct == PWMDAC_CT_DATA_SHIFT) {
+ items = ARRAY_SIZE(pwmdac_ct_data_shift);
+ strcpy(uinfo->value.enumerated.name,
+ pwmdac_ct_data_shift[uinfo->value.enumerated.item].name);
+ }
+
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+ uinfo->count = 1;
+ uinfo->value.enumerated.items = items;
+ if (uinfo->value.enumerated.item >= items)
+ uinfo->value.enumerated.item = items - 1;
+
+ return 0;
+}
+
+static int jh7110_pwmdac_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol,
+ int pwmdac_ct)
+{
+ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+ struct jh7110_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
+
+ if (pwmdac_ct == PWMDAC_CT_SHIFT)
+ ucontrol->value.enumerated.item[0] = dev->shift;
+ else if (pwmdac_ct == PWMDAC_CT_DUTY_CYCLE)
+ ucontrol->value.enumerated.item[0] = dev->duty_cycle;
+ else if (pwmdac_ct == PWMDAC_CT_DATA_CHANGE)
+ ucontrol->value.enumerated.item[0] = dev->data_change;
+ else if (pwmdac_ct == PWMDAC_CT_DATA_MODE)
+ ucontrol->value.enumerated.item[0] = dev->data_mode;
+ else if (pwmdac_ct == PWMDAC_CT_DATA_SHIFT)
+ ucontrol->value.enumerated.item[0] = dev->data_shift;
+
+ return 0;
+}
+
+static int jh7110_pwmdac_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol,
+ int pwmdac_ct)
+{
+ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+ struct jh7110_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
+ int sel = ucontrol->value.enumerated.item[0];
+ unsigned int items;
+
+ if (pwmdac_ct == PWMDAC_CT_SHIFT)
+ items = ARRAY_SIZE(pwmdac_ct_shift);
+ else if (pwmdac_ct == PWMDAC_CT_DUTY_CYCLE)
+ items = ARRAY_SIZE(pwmdac_ct_duty_cycle);
+ else if (pwmdac_ct == PWMDAC_CT_DATA_CHANGE)
+ items = ARRAY_SIZE(pwmdac_ct_data_change);
+ else if (pwmdac_ct == PWMDAC_CT_DATA_MODE)
+ items = ARRAY_SIZE(pwmdac_ct_data_mode);
+ else if (pwmdac_ct == PWMDAC_CT_DATA_SHIFT)
+ items = ARRAY_SIZE(pwmdac_ct_data_shift);
+
+ if (sel >= items)
+ return -EINVAL;
+
+ if (pwmdac_ct == PWMDAC_CT_SHIFT)
+ dev->shift = pwmdac_ct_shift[sel].vals;
+ else if (pwmdac_ct == PWMDAC_CT_DUTY_CYCLE)
+ dev->duty_cycle = pwmdac_ct_duty_cycle[sel].vals;
+ else if (pwmdac_ct == PWMDAC_CT_DATA_CHANGE)
+ dev->data_change = pwmdac_ct_data_change[sel].vals;
+ else if (pwmdac_ct == PWMDAC_CT_DATA_MODE)
+ dev->data_mode = pwmdac_ct_data_mode[sel].vals;
+ else if (pwmdac_ct == PWMDAC_CT_DATA_SHIFT)
+ dev->data_shift = pwmdac_ct_data_shift[sel].vals;
+
+ return 0;
+}
+
+static int jh7110_pwmdac_shift_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ return jh7110_pwmdac_info(uinfo, PWMDAC_CT_SHIFT);
+}
+
+static int jh7110_pwmdac_shift_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return jh7110_pwmdac_get(kcontrol, ucontrol, PWMDAC_CT_SHIFT);
+}
+
+static int jh7110_pwmdac_shift_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return jh7110_pwmdac_put(kcontrol, ucontrol, PWMDAC_CT_SHIFT);
+}
+
+static int jh7110_pwmdac_duty_cycle_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ return jh7110_pwmdac_info(uinfo, PWMDAC_CT_DUTY_CYCLE);
+}
+
+static int jh7110_pwmdac_duty_cycle_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return jh7110_pwmdac_get(kcontrol, ucontrol, PWMDAC_CT_DUTY_CYCLE);
+}
+
+static int jh7110_pwmdac_duty_cycle_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return jh7110_pwmdac_put(kcontrol, ucontrol, PWMDAC_CT_DUTY_CYCLE);
+}
+
+static int jh7110_pwmdac_data_change_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ return jh7110_pwmdac_info(uinfo, PWMDAC_CT_DATA_CHANGE);
+}
+
+static int jh7110_pwmdac_data_change_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return jh7110_pwmdac_get(kcontrol, ucontrol, PWMDAC_CT_DATA_CHANGE);
+}
+
+static int jh7110_pwmdac_data_change_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return jh7110_pwmdac_put(kcontrol, ucontrol, PWMDAC_CT_DATA_CHANGE);
+}
+
+static int jh7110_pwmdac_data_mode_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ return jh7110_pwmdac_info(uinfo, PWMDAC_CT_DATA_MODE);
+}
+
+static int jh7110_pwmdac_data_mode_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return jh7110_pwmdac_get(kcontrol, ucontrol, PWMDAC_CT_DATA_MODE);
+}
+
+static int jh7110_pwmdac_data_mode_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return jh7110_pwmdac_put(kcontrol, ucontrol, PWMDAC_CT_DATA_MODE);
+}
+
+static int jh7110_pwmdac_data_shift_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ return jh7110_pwmdac_info(uinfo, PWMDAC_CT_DATA_SHIFT);
+}
+
+static int jh7110_pwmdac_data_shift_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return jh7110_pwmdac_get(kcontrol, ucontrol, PWMDAC_CT_DATA_SHIFT);
+}
+
+static int jh7110_pwmdac_data_shift_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return jh7110_pwmdac_put(kcontrol, ucontrol, PWMDAC_CT_DATA_SHIFT);
+}
+
+static inline void jh7110_pwmdac_write_reg(void __iomem *io_base, int reg, u32 val)
+{
+ writel(val, io_base + reg);
+}
+
+static inline u32 jh7110_pwmdac_read_reg(void __iomem *io_base, int reg)
+{
+ return readl(io_base + reg);
+}
+
+static void jh7110_pwmdac_set_enable(struct jh7110_pwmdac_dev *dev, bool enable)
+{
+ u32 value;
+
+ value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL);
+ if (enable)
+ value |= JH7110_PWMDAC_ENABLE;
+ else
+ value &= ~JH7110_PWMDAC_ENABLE;
+
+ jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value);
+}
+
+static void jh7110_pwmdac_set_shift(struct jh7110_pwmdac_dev *dev)
+{
+ u32 value;
+
+ value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL);
+ if (dev->shift == PWMDAC_SHIFT_8)
+ value &= ~JH7110_PWMDAC_SHIFT;
+ else if (dev->shift == PWMDAC_SHIFT_10)
+ value |= JH7110_PWMDAC_SHIFT;
+
+ jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value);
+}
+
+static void jh7110_pwmdac_set_duty_cycle(struct jh7110_pwmdac_dev *dev)
+{
+ u32 value;
+
+ value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL);
+ value &= ~JH7110_PWMDAC_DUTY_CYCLE_MASK;
+ value |= (dev->duty_cycle & 0x3) << JH7110_PWMDAC_DUTY_CYCLE_SHIFT;
+
+ jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value);
+}
+
+static void jh7110_pwmdac_set_cnt_n(struct jh7110_pwmdac_dev *dev)
+{
+ u32 value;
+
+ value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL);
+ value &= ~JH7110_PWMDAC_CNT_N_MASK;
+ value |= ((dev->cnt_n - 1) & 0x1ff) << JH7110_PWMDAC_CNT_N_SHIFT;
+
+ jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value);
+}
+
+static void jh7110_pwmdac_set_data_change(struct jh7110_pwmdac_dev *dev)
+{
+ u32 value;
+
+ value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL);
+ if (dev->data_change == NO_CHANGE)
+ value &= ~JH7110_PWMDAC_DATA_CHANGE;
+ else if (dev->data_change == CHANGE)
+ value |= JH7110_PWMDAC_DATA_CHANGE;
+
+ jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value);
+}
+
+static void jh7110_pwmdac_set_data_mode(struct jh7110_pwmdac_dev *dev)
+{
+ u32 value;
+
+ value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL);
+ if (dev->data_mode == UNSIGNED_DATA)
+ value &= ~JH7110_PWMDAC_DATA_MODE;
+ else if (dev->data_mode == INVERTER_DATA_MSB)
+ value |= JH7110_PWMDAC_DATA_MODE;
+
+ jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value);
+}
+
+static void jh7110_pwmdac_set_data_shift(struct jh7110_pwmdac_dev *dev)
+{
+ u32 value;
+
+ value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL);
+ value &= ~JH7110_PWMDAC_DATA_SHIFT_MASK;
+ value |= (dev->data_shift & 0x7) << JH7110_PWMDAC_DATA_SHIFT_SHIFT;
+
+ jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value);
+}
+
+static void jh7110_pwmdac_set(struct jh7110_pwmdac_dev *dev)
+{
+ jh7110_pwmdac_set_shift(dev);
+ jh7110_pwmdac_set_duty_cycle(dev);
+ jh7110_pwmdac_set_cnt_n(dev);
+ jh7110_pwmdac_set_enable(dev, true);
+
+ jh7110_pwmdac_set_data_change(dev);
+ jh7110_pwmdac_set_data_mode(dev);
+ jh7110_pwmdac_set_data_shift(dev);
+}
+
+static void jh7110_pwmdac_stop(struct jh7110_pwmdac_dev *dev)
+{
+ jh7110_pwmdac_set_enable(dev, false);
+}
+
+static int jh7110_pwmdac_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai_link *dai_link = rtd->dai_link;
+
+ dai_link->stop_dma_first = 1;
+
+ return 0;
+}
+
+static int jh7110_pwmdac_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ unsigned long core_clk_rate;
+ int ret;
+ struct jh7110_pwmdac_dev *dev = dev_get_drvdata(dai->dev);
+
+ switch (params_rate(params)) {
+ case 8000:
+ dev->cnt_n = PWMDAC_SAMPLE_CNT_3;
+ core_clk_rate = 6144000;
+ break;
+ case 11025:
+ dev->cnt_n = PWMDAC_SAMPLE_CNT_2;
+ core_clk_rate = 5644800;
+ break;
+ case 16000:
+ dev->cnt_n = PWMDAC_SAMPLE_CNT_3;
+ core_clk_rate = 12288000;
+ break;
+ case 22050:
+ dev->cnt_n = PWMDAC_SAMPLE_CNT_1;
+ core_clk_rate = 5644800;
+ break;
+ case 32000:
+ dev->cnt_n = PWMDAC_SAMPLE_CNT_1;
+ core_clk_rate = 8192000;
+ break;
+ case 44100:
+ dev->cnt_n = PWMDAC_SAMPLE_CNT_1;
+ core_clk_rate = 11289600;
+ break;
+ case 48000:
+ dev->cnt_n = PWMDAC_SAMPLE_CNT_1;
+ core_clk_rate = 12288000;
+ break;
+ default:
+ dev_err(dai->dev, "%d rate not supported\n",
+ params_rate(params));
+ return -EINVAL;
+ }
+
+ switch (params_channels(params)) {
+ case 1:
+ dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+ break;
+ case 2:
+ dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ break;
+ default:
+ dev_err(dai->dev, "%d channels not supported\n",
+ params_channels(params));
+ return -EINVAL;
+ }
+
+ /*
+ * The clock rate always rounds down when using clk_set_rate()
+ * so increase the rate a bit
+ */
+ core_clk_rate += 64;
+ jh7110_pwmdac_set(dev);
+
+ ret = clk_set_rate(dev->clks[1].clk, core_clk_rate);
+ if (ret) {
+ dev_err(dai->dev,
+ "failed to set rate %lu for core clock\n",
+ core_clk_rate);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int jh7110_pwmdac_trigger(struct snd_pcm_substream *substream, int cmd,
+ struct snd_soc_dai *dai)
+{
+ struct jh7110_pwmdac_dev *dev = snd_soc_dai_get_drvdata(dai);
+ int ret = 0;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ jh7110_pwmdac_set(dev);
+ break;
+
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ jh7110_pwmdac_stop(dev);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+static int jh7110_pwmdac_crg_enable(struct jh7110_pwmdac_dev *dev, bool enable)
+{
+ int ret;
+
+ if (enable) {
+ ret = clk_bulk_prepare_enable(ARRAY_SIZE(dev->clks), dev->clks);
+ if (ret) {
+ dev_err(dev->dev, "failed to enable pwmdac clocks\n");
+ return ret;
+ }
+
+ ret = reset_control_deassert(dev->rst_apb);
+ if (ret) {
+ dev_err(dev->dev, "failed to deassert pwmdac apb reset\n");
+ goto err_rst_apb;
+ }
+ } else {
+ clk_bulk_disable_unprepare(ARRAY_SIZE(dev->clks), dev->clks);
+ }
+
+ return 0;
+
+err_rst_apb:
+ clk_bulk_disable_unprepare(ARRAY_SIZE(dev->clks), dev->clks);
+
+ return ret;
+}
+
+static int jh7110_pwmdac_dai_probe(struct snd_soc_dai *dai)
+{
+ struct jh7110_pwmdac_dev *dev = dev_get_drvdata(dai->dev);
+
+ dev->play_dma_data.addr = dev->mapbase + JH7110_PWMDAC_WDATA;
+ dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ dev->play_dma_data.fifo_size = 1;
+ dev->play_dma_data.maxburst = 16;
+
+ snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, NULL);
+ snd_soc_dai_set_drvdata(dai, dev);
+
+ return 0;
+}
+
+#define JH7110_PWMDAC_ENUM_DECL(xname, xinfo, xget, xput) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+ .info = xinfo, .get = xget, .put = xput,}
+
+static const struct snd_kcontrol_new jh7110_pwmdac_snd_controls[] = {
+ JH7110_PWMDAC_ENUM_DECL("shift", jh7110_pwmdac_shift_info,
+ jh7110_pwmdac_shift_get,
+ jh7110_pwmdac_shift_put),
+ JH7110_PWMDAC_ENUM_DECL("duty_cycle", jh7110_pwmdac_duty_cycle_info,
+ jh7110_pwmdac_duty_cycle_get,
+ jh7110_pwmdac_duty_cycle_put),
+ JH7110_PWMDAC_ENUM_DECL("data_change", jh7110_pwmdac_data_change_info,
+ jh7110_pwmdac_data_change_get,
+ jh7110_pwmdac_data_change_put),
+ JH7110_PWMDAC_ENUM_DECL("data_mode", jh7110_pwmdac_data_mode_info,
+ jh7110_pwmdac_data_mode_get,
+ jh7110_pwmdac_data_mode_put),
+ JH7110_PWMDAC_ENUM_DECL("data_shift", jh7110_pwmdac_data_shift_info,
+ jh7110_pwmdac_data_shift_get,
+ jh7110_pwmdac_data_shift_put),
+};
+
+static int jh7110_pwmdac_component_probe(struct snd_soc_component *component)
+{
+ snd_soc_add_component_controls(component, jh7110_pwmdac_snd_controls,
+ ARRAY_SIZE(jh7110_pwmdac_snd_controls));
+ return 0;
+}
+
+static const struct snd_soc_dai_ops jh7110_pwmdac_dai_ops = {
+ .startup = jh7110_pwmdac_startup,
+ .hw_params = jh7110_pwmdac_hw_params,
+ .trigger = jh7110_pwmdac_trigger,
+};
+
+static const struct snd_soc_component_driver jh7110_pwmdac_component = {
+ .name = "jh7110-pwmdac",
+ .probe = jh7110_pwmdac_component_probe,
+};
+
+static struct snd_soc_dai_driver jh7110_pwmdac_dai = {
+ .name = "jh7110-pwmdac",
+ .id = 0,
+ .probe = jh7110_pwmdac_dai_probe,
+ .playback = {
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_8000_48000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ },
+ .ops = &jh7110_pwmdac_dai_ops,
+};
+
+static int jh7110_pwmdac_runtime_suspend(struct device *dev)
+{
+ struct jh7110_pwmdac_dev *pwmdac = dev_get_drvdata(dev);
+
+ return jh7110_pwmdac_crg_enable(pwmdac, false);
+}
+
+static int jh7110_pwmdac_runtime_resume(struct device *dev)
+{
+ struct jh7110_pwmdac_dev *pwmdac = dev_get_drvdata(dev);
+
+ return jh7110_pwmdac_crg_enable(pwmdac, true);
+}
+
+static int jh7110_pwmdac_system_suspend(struct device *dev)
+{
+ struct jh7110_pwmdac_dev *pwmdac = dev_get_drvdata(dev);
+
+ /* save the CTRL register value */
+ pwmdac->saved_ctrl = jh7110_pwmdac_read_reg(pwmdac->base,
+ JH7110_PWMDAC_CTRL);
+ return pm_runtime_force_suspend(dev);
+}
+
+static int jh7110_pwmdac_system_resume(struct device *dev)
+{
+ struct jh7110_pwmdac_dev *pwmdac = dev_get_drvdata(dev);
+ int ret;
+
+ ret = pm_runtime_force_resume(dev);
+ if (ret)
+ return ret;
+
+ /* restore the CTRL register value */
+ jh7110_pwmdac_write_reg(pwmdac->base, JH7110_PWMDAC_CTRL,
+ pwmdac->saved_ctrl);
+ return 0;
+}
+
+static const struct dev_pm_ops jh7110_pwmdac_pm_ops = {
+ RUNTIME_PM_OPS(jh7110_pwmdac_runtime_suspend,
+ jh7110_pwmdac_runtime_resume, NULL)
+ SYSTEM_SLEEP_PM_OPS(jh7110_pwmdac_system_suspend,
+ jh7110_pwmdac_system_resume)
+};
+
+static int jh7110_pwmdac_probe(struct platform_device *pdev)
+{
+ struct jh7110_pwmdac_dev *dev;
+ struct resource *res;
+ int ret;
+
+ dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
+ if (!dev)
+ return -ENOMEM;
+
+ dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(dev->base))
+ return PTR_ERR(dev->base);
+
+ dev->mapbase = res->start;
+
+ dev->clks[0].id = "apb";
+ dev->clks[1].id = "core";
+
+ ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(dev->clks), dev->clks);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to get pwmdac clocks\n");
+ return ret;
+ }
+
+ dev->rst_apb = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(dev->rst_apb)) {
+ dev_err(&pdev->dev, "failed to get pwmdac apb reset\n");
+ return PTR_ERR(dev->rst_apb);
+ }
+
+ dev->dev = &pdev->dev;
+ dev->shift = PWMDAC_SHIFT_8;
+ dev->duty_cycle = PWMDAC_CYCLE_CENTER;
+ dev->cnt_n = PWMDAC_SAMPLE_CNT_1;
+ dev->data_change = NO_CHANGE;
+ dev->data_mode = INVERTER_DATA_MSB;
+ dev->data_shift = PWMDAC_DATA_LEFT_SHIFT_BIT_0;
+
+ dev_set_drvdata(&pdev->dev, dev);
+ ret = devm_snd_soc_register_component(&pdev->dev,
+ &jh7110_pwmdac_component,
+ &jh7110_pwmdac_dai, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register dai\n");
+ return ret;
+ }
+
+ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register pcm\n");
+ return ret;
+ }
+
+ pm_runtime_enable(dev->dev);
+ if (!pm_runtime_enabled(&pdev->dev)) {
+ ret = jh7110_pwmdac_runtime_resume(&pdev->dev);
+ if (ret)
+ goto err_pm_disable;
+ }
+
+ return 0;
+
+err_pm_disable:
+ pm_runtime_disable(&pdev->dev);
+
+ return ret;
+}
+
+static int jh7110_pwmdac_remove(struct platform_device *pdev)
+{
+ pm_runtime_disable(&pdev->dev);
+ return 0;
+}
+
+static const struct of_device_id jh7110_pwmdac_of_match[] = {
+ { .compatible = "starfive,jh7110-pwmdac" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jh7110_pwmdac_of_match);
+
+static struct platform_driver jh7110_pwmdac_driver = {
+ .driver = {
+ .name = "jh7110-pwmdac",
+ .of_match_table = jh7110_pwmdac_of_match,
+ .pm = pm_ptr(&jh7110_pwmdac_pm_ops),
+ },
+ .probe = jh7110_pwmdac_probe,
+ .remove = jh7110_pwmdac_remove,
+};
+module_platform_driver(jh7110_pwmdac_driver);
+
+MODULE_AUTHOR("Jenny Zhang");
+MODULE_AUTHOR("Curry Zhang");
+MODULE_AUTHOR("Xingyu Wu <[email protected]>");
+MODULE_AUTHOR("Hal Feng <[email protected]>");
+MODULE_DESCRIPTION("StarFive JH7110 PWM-DAC driver");
+MODULE_LICENSE("GPL");
--
2.38.1
Add a dummy transmitter driver for StarFive JH7110 PWM-DAC module.
StarFive JH7110 PWM-DAC controller uses this driver.
Signed-off-by: Hal Feng <[email protected]>
---
sound/soc/codecs/Kconfig | 4 ++
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/jh7110_pwmdac_transmitter.c | 74 ++++++++++++++++++++
3 files changed, 80 insertions(+)
create mode 100644 sound/soc/codecs/jh7110_pwmdac_transmitter.c
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 8020097d4e4c..f2cd8f999649 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -115,6 +115,7 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_IDT821034
imply SND_SOC_INNO_RK3036
imply SND_SOC_ISABELLE
+ imply SND_SOC_JH7110_PWMDAC_DIT
imply SND_SOC_JZ4740_CODEC
imply SND_SOC_JZ4725B_CODEC
imply SND_SOC_JZ4760_CODEC
@@ -903,6 +904,9 @@ config SND_SOC_CX2072X
help
Enable support for Conexant CX20721 and CX20723 codec chips.
+config SND_SOC_JH7110_PWMDAC_DIT
+ tristate "StarFive JH7110 dummy PWM-DAC transmitter"
+
config SND_SOC_JZ4740_CODEC
depends on MACH_INGENIC || COMPILE_TEST
depends on OF
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 5cdbae88e6e3..8e0e12d7b959 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -122,6 +122,7 @@ snd-soc-ics43432-objs := ics43432.o
snd-soc-idt821034-objs := idt821034.o
snd-soc-inno-rk3036-objs := inno_rk3036.o
snd-soc-isabelle-objs := isabelle.o
+snd-soc-jh7110-pwmdac-dit-objs := jh7110_pwmdac_transmitter.o
snd-soc-jz4740-codec-objs := jz4740.o
snd-soc-jz4725b-codec-objs := jz4725b.o
snd-soc-jz4760-codec-objs := jz4760.o
@@ -496,6 +497,7 @@ obj-$(CONFIG_SND_SOC_ICS43432) += snd-soc-ics43432.o
obj-$(CONFIG_SND_SOC_IDT821034) += snd-soc-idt821034.o
obj-$(CONFIG_SND_SOC_INNO_RK3036) += snd-soc-inno-rk3036.o
obj-$(CONFIG_SND_SOC_ISABELLE) += snd-soc-isabelle.o
+obj-$(CONFIG_SND_SOC_JH7110_PWMDAC_DIT) += snd-soc-jh7110-pwmdac-dit.o
obj-$(CONFIG_SND_SOC_JZ4740_CODEC) += snd-soc-jz4740-codec.o
obj-$(CONFIG_SND_SOC_JZ4725B_CODEC) += snd-soc-jz4725b-codec.o
obj-$(CONFIG_SND_SOC_JZ4760_CODEC) += snd-soc-jz4760-codec.o
diff --git a/sound/soc/codecs/jh7110_pwmdac_transmitter.c b/sound/soc/codecs/jh7110_pwmdac_transmitter.c
new file mode 100644
index 000000000000..69077be840c7
--- /dev/null
+++ b/sound/soc/codecs/jh7110_pwmdac_transmitter.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Dummy PWM-DAC transmitter driver for the StarFive JH7110 SoC
+ *
+ * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+#include <sound/initval.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+
+#define DRV_NAME "pwmdac-dit"
+
+static const struct snd_soc_dapm_widget dit_widgets[] = {
+ SND_SOC_DAPM_OUTPUT("pwmdac-out"),
+};
+
+static const struct snd_soc_dapm_route dit_routes[] = {
+ { "pwmdac-out", NULL, "Playback" },
+};
+
+static const struct snd_soc_component_driver soc_codec_pwmdac_dit = {
+ .dapm_widgets = dit_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(dit_widgets),
+ .dapm_routes = dit_routes,
+ .num_dapm_routes = ARRAY_SIZE(dit_routes),
+ .idle_bias_on = 1,
+ .use_pmdown_time = 1,
+ .endianness = 1,
+};
+
+static struct snd_soc_dai_driver dit_stub_dai = {
+ .name = "pwmdac-dit-hifi",
+ .playback = {
+ .stream_name = "Playback",
+ .channels_min = 1,
+ .channels_max = 384,
+ .rates = SNDRV_PCM_RATE_8000_48000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ },
+};
+
+static int pwmdac_dit_probe(struct platform_device *pdev)
+{
+ return devm_snd_soc_register_component(&pdev->dev,
+ &soc_codec_pwmdac_dit,
+ &dit_stub_dai, 1);
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id pwmdac_dit_dt_ids[] = {
+ { .compatible = "starfive,jh7110-pwmdac-dit", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, pwmdac_dit_dt_ids);
+#endif
+
+static struct platform_driver pwmdac_dit_driver = {
+ .probe = pwmdac_dit_probe,
+ .driver = {
+ .name = DRV_NAME,
+ .of_match_table = of_match_ptr(pwmdac_dit_dt_ids),
+ },
+};
+
+module_platform_driver(pwmdac_dit_driver);
+
+MODULE_DESCRIPTION("StarFive JH7110 dummy PWM-DAC transmitter driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRV_NAME);
--
2.38.1
Add PWM-DAC support for StarFive JH7110 SoC.
Signed-off-by: Hal Feng <[email protected]>
---
.../jh7110-starfive-visionfive-2.dtsi | 50 +++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 13 +++++
2 files changed, 63 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 19b5954ee72d..5ca66a65e722 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -36,6 +36,34 @@ gpio-restart {
gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
priority = <224>;
};
+
+ pwmdac_dit: pwmdac-dit {
+ compatible = "starfive,jh7110-pwmdac-dit";
+ #sound-dai-cells = <0>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ simple-audio-card,dai-link@0 {
+ reg = <0>;
+ format = "left_j";
+ bitclock-master = <&sndcpu0>;
+ frame-master = <&sndcpu0>;
+ status = "okay";
+
+ sndcpu0: cpu {
+ sound-dai = <&pwmdac>;
+ };
+
+ codec {
+ sound-dai = <&pwmdac_dit>;
+ };
+ };
+ };
};
&dvp_clk {
@@ -191,6 +219,22 @@ GPOEN_SYS_I2C6_DATA,
};
};
+ pwmdac_pins: pwmdac-0 {
+ pwmdac-pins {
+ pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
+ GPOEN_ENABLE,
+ GPI_NONE)>,
+ <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-disable;
+ drive-strength = <2>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
uart0_pins: uart0-0 {
tx-pins {
pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
@@ -250,6 +294,12 @@ GPOEN_DISABLE,
};
};
+&pwmdac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwmdac_pins>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index cfda6fb0d91b..bbb3f65e6f80 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -387,6 +387,19 @@ tdm: tdm@10090000 {
status = "disabled";
};
+ pwmdac: pwmdac@100b0000 {
+ compatible = "starfive,jh7110-pwmdac";
+ reg = <0x0 0x100b0000 0x0 0x1000>;
+ clocks = <&syscrg JH7110_SYSCLK_PWMDAC_APB>,
+ <&syscrg JH7110_SYSCLK_PWMDAC_CORE>;
+ clock-names = "apb", "core";
+ resets = <&syscrg JH7110_SYSRST_PWMDAC_APB>;
+ dmas = <&dma 22>;
+ dma-names = "tx";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
stgcrg: clock-controller@10230000 {
compatible = "starfive,jh7110-stgcrg";
reg = <0x0 0x10230000 0x0 0x10000>;
--
2.38.1
On 2023/6/26 19:09, Hal Feng wrote:
> Add PWM-DAC support for StarFive JH7110 SoC.
>
> Signed-off-by: Hal Feng <[email protected]>
Reviewed-by: Walker Chen <[email protected]>
> ---
> .../jh7110-starfive-visionfive-2.dtsi | 50 +++++++++++++++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 13 +++++
> 2 files changed, 63 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index 19b5954ee72d..5ca66a65e722 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -36,6 +36,34 @@ gpio-restart {
> gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
> priority = <224>;
> };
> +
> + pwmdac_dit: pwmdac-dit {
> + compatible = "starfive,jh7110-pwmdac-dit";
> + #sound-dai-cells = <0>;
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + simple-audio-card,dai-link@0 {
> + reg = <0>;
> + format = "left_j";
> + bitclock-master = <&sndcpu0>;
> + frame-master = <&sndcpu0>;
> + status = "okay";
> +
> + sndcpu0: cpu {
> + sound-dai = <&pwmdac>;
> + };
> +
> + codec {
> + sound-dai = <&pwmdac_dit>;
> + };
> + };
> + };
> };
>
> &dvp_clk {
> @@ -191,6 +219,22 @@ GPOEN_SYS_I2C6_DATA,
> };
> };
>
> + pwmdac_pins: pwmdac-0 {
> + pwmdac-pins {
> + pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
> + GPOEN_ENABLE,
> + GPI_NONE)>,
> + <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
> + GPOEN_ENABLE,
> + GPI_NONE)>;
> + bias-disable;
> + drive-strength = <2>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + };
> +
> uart0_pins: uart0-0 {
> tx-pins {
> pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
> @@ -250,6 +294,12 @@ GPOEN_DISABLE,
> };
> };
>
> +&pwmdac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwmdac_pins>;
> + status = "okay";
> +};
> +
> &uart0 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart0_pins>;
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index cfda6fb0d91b..bbb3f65e6f80 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -387,6 +387,19 @@ tdm: tdm@10090000 {
> status = "disabled";
> };
>
> + pwmdac: pwmdac@100b0000 {
> + compatible = "starfive,jh7110-pwmdac";
> + reg = <0x0 0x100b0000 0x0 0x1000>;
> + clocks = <&syscrg JH7110_SYSCLK_PWMDAC_APB>,
> + <&syscrg JH7110_SYSCLK_PWMDAC_CORE>;
> + clock-names = "apb", "core";
> + resets = <&syscrg JH7110_SYSRST_PWMDAC_APB>;
> + dmas = <&dma 22>;
> + dma-names = "tx";
> + #sound-dai-cells = <0>;
> + status = "disabled";
> + };
> +
> stgcrg: clock-controller@10230000 {
> compatible = "starfive,jh7110-stgcrg";
> reg = <0x0 0x10230000 0x0 0x10000>;
On 2023/6/26 19:09, Hal Feng wrote:
> Add PWM-DAC driver support for the StarFive JH7110 SoC.
>
> Signed-off-by: Hal Feng <[email protected]>
Thanks!
Reviewed-by: Walker Chen <[email protected]>
> ---
> MAINTAINERS | 8 +
> sound/soc/starfive/Kconfig | 9 +
> sound/soc/starfive/Makefile | 1 +
> sound/soc/starfive/jh7110_pwmdac.c | 787 +++++++++++++++++++++++++++++
> 4 files changed, 805 insertions(+)
> create mode 100644 sound/soc/starfive/jh7110_pwmdac.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1dc12c5c02f7..a936ba4d5f1d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20125,6 +20125,14 @@ S: Supported
> F: Documentation/devicetree/bindings/mmc/starfive*
> F: drivers/mmc/host/dw_mmc-starfive.c
>
> +STARFIVE JH7110 PWMDAC DRIVER
> +M: Hal Feng <[email protected]>
> +M: Xingyu Wu <[email protected]>
> +S: Supported
> +F: Documentation/devicetree/bindings/sound/starfive,jh7110-pwmdac*
> +F: sound/soc/codecs/jh7110_pwmdac_transmitter.c
> +F: sound/soc/starfive/jh7110_pwmdac.c
> +
> STARFIVE JH71X0 CLOCK DRIVERS
> M: Emil Renner Berthing <[email protected]>
> M: Hal Feng <[email protected]>
> diff --git a/sound/soc/starfive/Kconfig b/sound/soc/starfive/Kconfig
> index fafb681f8c0a..fabef377db8c 100644
> --- a/sound/soc/starfive/Kconfig
> +++ b/sound/soc/starfive/Kconfig
> @@ -7,6 +7,15 @@ config SND_SOC_STARFIVE
> the Starfive SoCs' Audio interfaces. You will also need to
> select the audio interfaces to support below.
>
> +config SND_SOC_JH7110_PWMDAC
> + tristate "JH7110 PWM-DAC device driver"
> + depends on HAVE_CLK && SND_SOC_STARFIVE
> + select SND_SOC_GENERIC_DMAENGINE_PCM
> + select SND_SOC_JH7110_PWMDAC_DIT
> + help
> + Say Y or M if you want to add support for StarFive JH7110
> + PWM-DAC driver.
> +
> config SND_SOC_JH7110_TDM
> tristate "JH7110 TDM device driver"
> depends on HAVE_CLK && SND_SOC_STARFIVE
> diff --git a/sound/soc/starfive/Makefile b/sound/soc/starfive/Makefile
> index f7d960211d72..9e958f70ef51 100644
> --- a/sound/soc/starfive/Makefile
> +++ b/sound/soc/starfive/Makefile
> @@ -1,2 +1,3 @@
> # StarFive Platform Support
> +obj-$(CONFIG_SND_SOC_JH7110_PWMDAC) += jh7110_pwmdac.o
> obj-$(CONFIG_SND_SOC_JH7110_TDM) += jh7110_tdm.o
> diff --git a/sound/soc/starfive/jh7110_pwmdac.c b/sound/soc/starfive/jh7110_pwmdac.c
> new file mode 100644
> index 000000000000..c3123bd6ea45
> --- /dev/null
> +++ b/sound/soc/starfive/jh7110_pwmdac.c
> @@ -0,0 +1,787 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * jh7110_pwmdac.c -- StarFive JH7110 PWM-DAC driver
> + *
> + * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
> + *
> + * Authors: Jenny Zhang
> + * Curry Zhang
> + * Xingyu Wu <[email protected]>
> + * Hal Feng <[email protected]>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/device.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +#include <linux/types.h>
> +#include <sound/dmaengine_pcm.h>
> +#include <sound/pcm.h>
> +#include <sound/pcm_params.h>
> +#include <sound/soc.h>
> +
> +#define JH7110_PWMDAC_WDATA 0x00
> +#define JH7110_PWMDAC_CTRL 0x04
> + #define JH7110_PWMDAC_ENABLE BIT(0)
> + #define JH7110_PWMDAC_SHIFT BIT(1)
> + #define JH7110_PWMDAC_DUTY_CYCLE_SHIFT 2
> + #define JH7110_PWMDAC_DUTY_CYCLE_MASK GENMASK(3, 2)
> + #define JH7110_PWMDAC_CNT_N_SHIFT 4
> + #define JH7110_PWMDAC_CNT_N_MASK GENMASK(12, 4)
> + #define JH7110_PWMDAC_DATA_CHANGE BIT(13)
> + #define JH7110_PWMDAC_DATA_MODE BIT(14)
> + #define JH7110_PWMDAC_DATA_SHIFT_SHIFT 15
> + #define JH7110_PWMDAC_DATA_SHIFT_MASK GENMASK(17, 15)
> +
> +enum JH7110_PWMDAC_SHIFT_VAL {
> + PWMDAC_SHIFT_8 = 0,
> + PWMDAC_SHIFT_10,
> +};
> +
> +enum JH7110_PWMDAC_DUTY_CYCLE_VAL {
> + PWMDAC_CYCLE_LEFT = 0,
> + PWMDAC_CYCLE_RIGHT,
> + PWMDAC_CYCLE_CENTER,
> +};
> +
> +enum JH7110_PWMDAC_CNT_N_VAL {
> + PWMDAC_SAMPLE_CNT_1 = 1,
> + PWMDAC_SAMPLE_CNT_2,
> + PWMDAC_SAMPLE_CNT_3,
> + PWMDAC_SAMPLE_CNT_512 = 512, /* max */
> +};
> +
> +enum JH7110_PWMDAC_DATA_CHANGE_VAL {
> + NO_CHANGE = 0,
> + CHANGE,
> +};
> +
> +enum JH7110_PWMDAC_DATA_MODE_VAL {
> + UNSIGNED_DATA = 0,
> + INVERTER_DATA_MSB,
> +};
> +
> +enum JH7110_PWMDAC_DATA_SHIFT_VAL {
> + PWMDAC_DATA_LEFT_SHIFT_BIT_0 = 0,
> + PWMDAC_DATA_LEFT_SHIFT_BIT_1,
> + PWMDAC_DATA_LEFT_SHIFT_BIT_2,
> + PWMDAC_DATA_LEFT_SHIFT_BIT_3,
> + PWMDAC_DATA_LEFT_SHIFT_BIT_4,
> + PWMDAC_DATA_LEFT_SHIFT_BIT_5,
> + PWMDAC_DATA_LEFT_SHIFT_BIT_6,
> + PWMDAC_DATA_LEFT_SHIFT_BIT_7,
> +};
> +
> +struct jh7110_pwmdac_dev {
> + void __iomem *base;
> + resource_size_t mapbase;
> + u8 shift;
> + u8 duty_cycle;
> + u8 cnt_n;
> + u8 data_change;
> + u8 data_mode;
> + u8 data_shift;
> +
> + struct clk_bulk_data clks[2];
> + struct reset_control *rst_apb;
> + struct device *dev;
> + struct snd_dmaengine_dai_dma_data play_dma_data;
> + u32 saved_ctrl;
> +};
> +
> +enum jh7110_ct_pwmdac_name {
> + PWMDAC_CT_SHIFT = 0,
> + PWMDAC_CT_DUTY_CYCLE,
> + PWMDAC_CT_DATA_CHANGE,
> + PWMDAC_CT_DATA_MODE,
> + PWMDAC_CT_DATA_SHIFT,
> +};
> +
> +struct jh7110_ct_pwmdac {
> + char *name;
> + unsigned int vals;
> +};
> +
> +static const struct jh7110_ct_pwmdac pwmdac_ct_shift[] = {
> + { .name = "8bit", .vals = PWMDAC_SHIFT_8 },
> + { .name = "10bit", .vals = PWMDAC_SHIFT_10 }
> +};
> +
> +static const struct jh7110_ct_pwmdac pwmdac_ct_duty_cycle[] = {
> + { .name = "left", .vals = PWMDAC_CYCLE_LEFT },
> + { .name = "right", .vals = PWMDAC_CYCLE_RIGHT },
> + { .name = "center", .vals = PWMDAC_CYCLE_CENTER }
> +};
> +
> +static const struct jh7110_ct_pwmdac pwmdac_ct_data_change[] = {
> + { .name = "no_change", .vals = NO_CHANGE },
> + { .name = "change", .vals = CHANGE }
> +};
> +
> +static const struct jh7110_ct_pwmdac pwmdac_ct_data_mode[] = {
> + { .name = "unsigned", .vals = UNSIGNED_DATA },
> + { .name = "inverter", .vals = INVERTER_DATA_MSB }
> +};
> +
> +static const struct jh7110_ct_pwmdac pwmdac_ct_data_shift[] = {
> + { .name = "left 0 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_0 },
> + { .name = "left 1 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_1 },
> + { .name = "left 2 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_2 },
> + { .name = "left 3 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_3 },
> + { .name = "left 4 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_4 },
> + { .name = "left 5 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_5 },
> + { .name = "left 6 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_6 },
> + { .name = "left 7 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_7 }
> +};
> +
> +static int jh7110_pwmdac_info(struct snd_ctl_elem_info *uinfo, int pwmdac_ct)
> +{
> + unsigned int items;
> +
> + if (pwmdac_ct == PWMDAC_CT_SHIFT) {
> + items = ARRAY_SIZE(pwmdac_ct_shift);
> + strcpy(uinfo->value.enumerated.name,
> + pwmdac_ct_shift[uinfo->value.enumerated.item].name);
> + } else if (pwmdac_ct == PWMDAC_CT_DUTY_CYCLE) {
> + items = ARRAY_SIZE(pwmdac_ct_duty_cycle);
> + strcpy(uinfo->value.enumerated.name,
> + pwmdac_ct_duty_cycle[uinfo->value.enumerated.item].name);
> + } else if (pwmdac_ct == PWMDAC_CT_DATA_CHANGE) {
> + items = ARRAY_SIZE(pwmdac_ct_data_change);
> + strcpy(uinfo->value.enumerated.name,
> + pwmdac_ct_data_change[uinfo->value.enumerated.item].name);
> + } else if (pwmdac_ct == PWMDAC_CT_DATA_MODE) {
> + items = ARRAY_SIZE(pwmdac_ct_data_mode);
> + strcpy(uinfo->value.enumerated.name,
> + pwmdac_ct_data_mode[uinfo->value.enumerated.item].name);
> + } else if (pwmdac_ct == PWMDAC_CT_DATA_SHIFT) {
> + items = ARRAY_SIZE(pwmdac_ct_data_shift);
> + strcpy(uinfo->value.enumerated.name,
> + pwmdac_ct_data_shift[uinfo->value.enumerated.item].name);
> + }
> +
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
> + uinfo->count = 1;
> + uinfo->value.enumerated.items = items;
> + if (uinfo->value.enumerated.item >= items)
> + uinfo->value.enumerated.item = items - 1;
> +
> + return 0;
> +}
> +
> +static int jh7110_pwmdac_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol,
> + int pwmdac_ct)
> +{
> + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
> + struct jh7110_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
> +
> + if (pwmdac_ct == PWMDAC_CT_SHIFT)
> + ucontrol->value.enumerated.item[0] = dev->shift;
> + else if (pwmdac_ct == PWMDAC_CT_DUTY_CYCLE)
> + ucontrol->value.enumerated.item[0] = dev->duty_cycle;
> + else if (pwmdac_ct == PWMDAC_CT_DATA_CHANGE)
> + ucontrol->value.enumerated.item[0] = dev->data_change;
> + else if (pwmdac_ct == PWMDAC_CT_DATA_MODE)
> + ucontrol->value.enumerated.item[0] = dev->data_mode;
> + else if (pwmdac_ct == PWMDAC_CT_DATA_SHIFT)
> + ucontrol->value.enumerated.item[0] = dev->data_shift;
> +
> + return 0;
> +}
> +
> +static int jh7110_pwmdac_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol,
> + int pwmdac_ct)
> +{
> + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
> + struct jh7110_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
> + int sel = ucontrol->value.enumerated.item[0];
> + unsigned int items;
> +
> + if (pwmdac_ct == PWMDAC_CT_SHIFT)
> + items = ARRAY_SIZE(pwmdac_ct_shift);
> + else if (pwmdac_ct == PWMDAC_CT_DUTY_CYCLE)
> + items = ARRAY_SIZE(pwmdac_ct_duty_cycle);
> + else if (pwmdac_ct == PWMDAC_CT_DATA_CHANGE)
> + items = ARRAY_SIZE(pwmdac_ct_data_change);
> + else if (pwmdac_ct == PWMDAC_CT_DATA_MODE)
> + items = ARRAY_SIZE(pwmdac_ct_data_mode);
> + else if (pwmdac_ct == PWMDAC_CT_DATA_SHIFT)
> + items = ARRAY_SIZE(pwmdac_ct_data_shift);
> +
> + if (sel >= items)
> + return -EINVAL;
> +
> + if (pwmdac_ct == PWMDAC_CT_SHIFT)
> + dev->shift = pwmdac_ct_shift[sel].vals;
> + else if (pwmdac_ct == PWMDAC_CT_DUTY_CYCLE)
> + dev->duty_cycle = pwmdac_ct_duty_cycle[sel].vals;
> + else if (pwmdac_ct == PWMDAC_CT_DATA_CHANGE)
> + dev->data_change = pwmdac_ct_data_change[sel].vals;
> + else if (pwmdac_ct == PWMDAC_CT_DATA_MODE)
> + dev->data_mode = pwmdac_ct_data_mode[sel].vals;
> + else if (pwmdac_ct == PWMDAC_CT_DATA_SHIFT)
> + dev->data_shift = pwmdac_ct_data_shift[sel].vals;
> +
> + return 0;
> +}
> +
> +static int jh7110_pwmdac_shift_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + return jh7110_pwmdac_info(uinfo, PWMDAC_CT_SHIFT);
> +}
> +
> +static int jh7110_pwmdac_shift_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return jh7110_pwmdac_get(kcontrol, ucontrol, PWMDAC_CT_SHIFT);
> +}
> +
> +static int jh7110_pwmdac_shift_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return jh7110_pwmdac_put(kcontrol, ucontrol, PWMDAC_CT_SHIFT);
> +}
> +
> +static int jh7110_pwmdac_duty_cycle_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + return jh7110_pwmdac_info(uinfo, PWMDAC_CT_DUTY_CYCLE);
> +}
> +
> +static int jh7110_pwmdac_duty_cycle_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return jh7110_pwmdac_get(kcontrol, ucontrol, PWMDAC_CT_DUTY_CYCLE);
> +}
> +
> +static int jh7110_pwmdac_duty_cycle_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return jh7110_pwmdac_put(kcontrol, ucontrol, PWMDAC_CT_DUTY_CYCLE);
> +}
> +
> +static int jh7110_pwmdac_data_change_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + return jh7110_pwmdac_info(uinfo, PWMDAC_CT_DATA_CHANGE);
> +}
> +
> +static int jh7110_pwmdac_data_change_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return jh7110_pwmdac_get(kcontrol, ucontrol, PWMDAC_CT_DATA_CHANGE);
> +}
> +
> +static int jh7110_pwmdac_data_change_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return jh7110_pwmdac_put(kcontrol, ucontrol, PWMDAC_CT_DATA_CHANGE);
> +}
> +
> +static int jh7110_pwmdac_data_mode_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + return jh7110_pwmdac_info(uinfo, PWMDAC_CT_DATA_MODE);
> +}
> +
> +static int jh7110_pwmdac_data_mode_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return jh7110_pwmdac_get(kcontrol, ucontrol, PWMDAC_CT_DATA_MODE);
> +}
> +
> +static int jh7110_pwmdac_data_mode_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return jh7110_pwmdac_put(kcontrol, ucontrol, PWMDAC_CT_DATA_MODE);
> +}
> +
> +static int jh7110_pwmdac_data_shift_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + return jh7110_pwmdac_info(uinfo, PWMDAC_CT_DATA_SHIFT);
> +}
> +
> +static int jh7110_pwmdac_data_shift_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return jh7110_pwmdac_get(kcontrol, ucontrol, PWMDAC_CT_DATA_SHIFT);
> +}
> +
> +static int jh7110_pwmdac_data_shift_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return jh7110_pwmdac_put(kcontrol, ucontrol, PWMDAC_CT_DATA_SHIFT);
> +}
> +
> +static inline void jh7110_pwmdac_write_reg(void __iomem *io_base, int reg, u32 val)
> +{
> + writel(val, io_base + reg);
> +}
> +
> +static inline u32 jh7110_pwmdac_read_reg(void __iomem *io_base, int reg)
> +{
> + return readl(io_base + reg);
> +}
> +
> +static void jh7110_pwmdac_set_enable(struct jh7110_pwmdac_dev *dev, bool enable)
> +{
> + u32 value;
> +
> + value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL);
> + if (enable)
> + value |= JH7110_PWMDAC_ENABLE;
> + else
> + value &= ~JH7110_PWMDAC_ENABLE;
> +
> + jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value);
> +}
> +
> +static void jh7110_pwmdac_set_shift(struct jh7110_pwmdac_dev *dev)
> +{
> + u32 value;
> +
> + value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL);
> + if (dev->shift == PWMDAC_SHIFT_8)
> + value &= ~JH7110_PWMDAC_SHIFT;
> + else if (dev->shift == PWMDAC_SHIFT_10)
> + value |= JH7110_PWMDAC_SHIFT;
> +
> + jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value);
> +}
> +
> +static void jh7110_pwmdac_set_duty_cycle(struct jh7110_pwmdac_dev *dev)
> +{
> + u32 value;
> +
> + value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL);
> + value &= ~JH7110_PWMDAC_DUTY_CYCLE_MASK;
> + value |= (dev->duty_cycle & 0x3) << JH7110_PWMDAC_DUTY_CYCLE_SHIFT;
> +
> + jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value);
> +}
> +
> +static void jh7110_pwmdac_set_cnt_n(struct jh7110_pwmdac_dev *dev)
> +{
> + u32 value;
> +
> + value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL);
> + value &= ~JH7110_PWMDAC_CNT_N_MASK;
> + value |= ((dev->cnt_n - 1) & 0x1ff) << JH7110_PWMDAC_CNT_N_SHIFT;
> +
> + jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value);
> +}
> +
> +static void jh7110_pwmdac_set_data_change(struct jh7110_pwmdac_dev *dev)
> +{
> + u32 value;
> +
> + value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL);
> + if (dev->data_change == NO_CHANGE)
> + value &= ~JH7110_PWMDAC_DATA_CHANGE;
> + else if (dev->data_change == CHANGE)
> + value |= JH7110_PWMDAC_DATA_CHANGE;
> +
> + jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value);
> +}
> +
> +static void jh7110_pwmdac_set_data_mode(struct jh7110_pwmdac_dev *dev)
> +{
> + u32 value;
> +
> + value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL);
> + if (dev->data_mode == UNSIGNED_DATA)
> + value &= ~JH7110_PWMDAC_DATA_MODE;
> + else if (dev->data_mode == INVERTER_DATA_MSB)
> + value |= JH7110_PWMDAC_DATA_MODE;
> +
> + jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value);
> +}
> +
> +static void jh7110_pwmdac_set_data_shift(struct jh7110_pwmdac_dev *dev)
> +{
> + u32 value;
> +
> + value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL);
> + value &= ~JH7110_PWMDAC_DATA_SHIFT_MASK;
> + value |= (dev->data_shift & 0x7) << JH7110_PWMDAC_DATA_SHIFT_SHIFT;
> +
> + jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value);
> +}
> +
> +static void jh7110_pwmdac_set(struct jh7110_pwmdac_dev *dev)
> +{
> + jh7110_pwmdac_set_shift(dev);
> + jh7110_pwmdac_set_duty_cycle(dev);
> + jh7110_pwmdac_set_cnt_n(dev);
> + jh7110_pwmdac_set_enable(dev, true);
> +
> + jh7110_pwmdac_set_data_change(dev);
> + jh7110_pwmdac_set_data_mode(dev);
> + jh7110_pwmdac_set_data_shift(dev);
> +}
> +
> +static void jh7110_pwmdac_stop(struct jh7110_pwmdac_dev *dev)
> +{
> + jh7110_pwmdac_set_enable(dev, false);
> +}
> +
> +static int jh7110_pwmdac_startup(struct snd_pcm_substream *substream,
> + struct snd_soc_dai *dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
> + struct snd_soc_dai_link *dai_link = rtd->dai_link;
> +
> + dai_link->stop_dma_first = 1;
> +
> + return 0;
> +}
> +
> +static int jh7110_pwmdac_hw_params(struct snd_pcm_substream *substream,
> + struct snd_pcm_hw_params *params,
> + struct snd_soc_dai *dai)
> +{
> + unsigned long core_clk_rate;
> + int ret;
> + struct jh7110_pwmdac_dev *dev = dev_get_drvdata(dai->dev);
> +
> + switch (params_rate(params)) {
> + case 8000:
> + dev->cnt_n = PWMDAC_SAMPLE_CNT_3;
> + core_clk_rate = 6144000;
> + break;
> + case 11025:
> + dev->cnt_n = PWMDAC_SAMPLE_CNT_2;
> + core_clk_rate = 5644800;
> + break;
> + case 16000:
> + dev->cnt_n = PWMDAC_SAMPLE_CNT_3;
> + core_clk_rate = 12288000;
> + break;
> + case 22050:
> + dev->cnt_n = PWMDAC_SAMPLE_CNT_1;
> + core_clk_rate = 5644800;
> + break;
> + case 32000:
> + dev->cnt_n = PWMDAC_SAMPLE_CNT_1;
> + core_clk_rate = 8192000;
> + break;
> + case 44100:
> + dev->cnt_n = PWMDAC_SAMPLE_CNT_1;
> + core_clk_rate = 11289600;
> + break;
> + case 48000:
> + dev->cnt_n = PWMDAC_SAMPLE_CNT_1;
> + core_clk_rate = 12288000;
> + break;
> + default:
> + dev_err(dai->dev, "%d rate not supported\n",
> + params_rate(params));
> + return -EINVAL;
> + }
> +
> + switch (params_channels(params)) {
> + case 1:
> + dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
> + break;
> + case 2:
> + dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> + break;
> + default:
> + dev_err(dai->dev, "%d channels not supported\n",
> + params_channels(params));
> + return -EINVAL;
> + }
> +
> + /*
> + * The clock rate always rounds down when using clk_set_rate()
> + * so increase the rate a bit
> + */
> + core_clk_rate += 64;
> + jh7110_pwmdac_set(dev);
> +
> + ret = clk_set_rate(dev->clks[1].clk, core_clk_rate);
> + if (ret) {
> + dev_err(dai->dev,
> + "failed to set rate %lu for core clock\n",
> + core_clk_rate);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int jh7110_pwmdac_trigger(struct snd_pcm_substream *substream, int cmd,
> + struct snd_soc_dai *dai)
> +{
> + struct jh7110_pwmdac_dev *dev = snd_soc_dai_get_drvdata(dai);
> + int ret = 0;
> +
> + switch (cmd) {
> + case SNDRV_PCM_TRIGGER_START:
> + case SNDRV_PCM_TRIGGER_RESUME:
> + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
> + jh7110_pwmdac_set(dev);
> + break;
> +
> + case SNDRV_PCM_TRIGGER_STOP:
> + case SNDRV_PCM_TRIGGER_SUSPEND:
> + case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
> + jh7110_pwmdac_stop(dev);
> + break;
> + default:
> + ret = -EINVAL;
> + break;
> + }
> +
> + return ret;
> +}
> +
> +static int jh7110_pwmdac_crg_enable(struct jh7110_pwmdac_dev *dev, bool enable)
> +{
> + int ret;
> +
> + if (enable) {
> + ret = clk_bulk_prepare_enable(ARRAY_SIZE(dev->clks), dev->clks);
> + if (ret) {
> + dev_err(dev->dev, "failed to enable pwmdac clocks\n");
> + return ret;
> + }
> +
> + ret = reset_control_deassert(dev->rst_apb);
> + if (ret) {
> + dev_err(dev->dev, "failed to deassert pwmdac apb reset\n");
> + goto err_rst_apb;
> + }
> + } else {
> + clk_bulk_disable_unprepare(ARRAY_SIZE(dev->clks), dev->clks);
> + }
> +
> + return 0;
> +
> +err_rst_apb:
> + clk_bulk_disable_unprepare(ARRAY_SIZE(dev->clks), dev->clks);
> +
> + return ret;
> +}
> +
> +static int jh7110_pwmdac_dai_probe(struct snd_soc_dai *dai)
> +{
> + struct jh7110_pwmdac_dev *dev = dev_get_drvdata(dai->dev);
> +
> + dev->play_dma_data.addr = dev->mapbase + JH7110_PWMDAC_WDATA;
> + dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> + dev->play_dma_data.fifo_size = 1;
> + dev->play_dma_data.maxburst = 16;
> +
> + snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, NULL);
> + snd_soc_dai_set_drvdata(dai, dev);
> +
> + return 0;
> +}
> +
> +#define JH7110_PWMDAC_ENUM_DECL(xname, xinfo, xget, xput) \
> +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
> + .info = xinfo, .get = xget, .put = xput,}
> +
> +static const struct snd_kcontrol_new jh7110_pwmdac_snd_controls[] = {
> + JH7110_PWMDAC_ENUM_DECL("shift", jh7110_pwmdac_shift_info,
> + jh7110_pwmdac_shift_get,
> + jh7110_pwmdac_shift_put),
> + JH7110_PWMDAC_ENUM_DECL("duty_cycle", jh7110_pwmdac_duty_cycle_info,
> + jh7110_pwmdac_duty_cycle_get,
> + jh7110_pwmdac_duty_cycle_put),
> + JH7110_PWMDAC_ENUM_DECL("data_change", jh7110_pwmdac_data_change_info,
> + jh7110_pwmdac_data_change_get,
> + jh7110_pwmdac_data_change_put),
> + JH7110_PWMDAC_ENUM_DECL("data_mode", jh7110_pwmdac_data_mode_info,
> + jh7110_pwmdac_data_mode_get,
> + jh7110_pwmdac_data_mode_put),
> + JH7110_PWMDAC_ENUM_DECL("data_shift", jh7110_pwmdac_data_shift_info,
> + jh7110_pwmdac_data_shift_get,
> + jh7110_pwmdac_data_shift_put),
> +};
> +
> +static int jh7110_pwmdac_component_probe(struct snd_soc_component *component)
> +{
> + snd_soc_add_component_controls(component, jh7110_pwmdac_snd_controls,
> + ARRAY_SIZE(jh7110_pwmdac_snd_controls));
> + return 0;
> +}
> +
> +static const struct snd_soc_dai_ops jh7110_pwmdac_dai_ops = {
> + .startup = jh7110_pwmdac_startup,
> + .hw_params = jh7110_pwmdac_hw_params,
> + .trigger = jh7110_pwmdac_trigger,
> +};
> +
> +static const struct snd_soc_component_driver jh7110_pwmdac_component = {
> + .name = "jh7110-pwmdac",
> + .probe = jh7110_pwmdac_component_probe,
> +};
> +
> +static struct snd_soc_dai_driver jh7110_pwmdac_dai = {
> + .name = "jh7110-pwmdac",
> + .id = 0,
> + .probe = jh7110_pwmdac_dai_probe,
> + .playback = {
> + .channels_min = 1,
> + .channels_max = 2,
> + .rates = SNDRV_PCM_RATE_8000_48000,
> + .formats = SNDRV_PCM_FMTBIT_S16_LE,
> + },
> + .ops = &jh7110_pwmdac_dai_ops,
> +};
> +
> +static int jh7110_pwmdac_runtime_suspend(struct device *dev)
> +{
> + struct jh7110_pwmdac_dev *pwmdac = dev_get_drvdata(dev);
> +
> + return jh7110_pwmdac_crg_enable(pwmdac, false);
> +}
> +
> +static int jh7110_pwmdac_runtime_resume(struct device *dev)
> +{
> + struct jh7110_pwmdac_dev *pwmdac = dev_get_drvdata(dev);
> +
> + return jh7110_pwmdac_crg_enable(pwmdac, true);
> +}
> +
> +static int jh7110_pwmdac_system_suspend(struct device *dev)
> +{
> + struct jh7110_pwmdac_dev *pwmdac = dev_get_drvdata(dev);
> +
> + /* save the CTRL register value */
> + pwmdac->saved_ctrl = jh7110_pwmdac_read_reg(pwmdac->base,
> + JH7110_PWMDAC_CTRL);
> + return pm_runtime_force_suspend(dev);
> +}
> +
> +static int jh7110_pwmdac_system_resume(struct device *dev)
> +{
> + struct jh7110_pwmdac_dev *pwmdac = dev_get_drvdata(dev);
> + int ret;
> +
> + ret = pm_runtime_force_resume(dev);
> + if (ret)
> + return ret;
> +
> + /* restore the CTRL register value */
> + jh7110_pwmdac_write_reg(pwmdac->base, JH7110_PWMDAC_CTRL,
> + pwmdac->saved_ctrl);
> + return 0;
> +}
> +
> +static const struct dev_pm_ops jh7110_pwmdac_pm_ops = {
> + RUNTIME_PM_OPS(jh7110_pwmdac_runtime_suspend,
> + jh7110_pwmdac_runtime_resume, NULL)
> + SYSTEM_SLEEP_PM_OPS(jh7110_pwmdac_system_suspend,
> + jh7110_pwmdac_system_resume)
> +};
> +
> +static int jh7110_pwmdac_probe(struct platform_device *pdev)
> +{
> + struct jh7110_pwmdac_dev *dev;
> + struct resource *res;
> + int ret;
> +
> + dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
> + if (!dev)
> + return -ENOMEM;
> +
> + dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
> + if (IS_ERR(dev->base))
> + return PTR_ERR(dev->base);
> +
> + dev->mapbase = res->start;
> +
> + dev->clks[0].id = "apb";
> + dev->clks[1].id = "core";
> +
> + ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(dev->clks), dev->clks);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to get pwmdac clocks\n");
> + return ret;
> + }
> +
> + dev->rst_apb = devm_reset_control_get_exclusive(&pdev->dev, NULL);
> + if (IS_ERR(dev->rst_apb)) {
> + dev_err(&pdev->dev, "failed to get pwmdac apb reset\n");
> + return PTR_ERR(dev->rst_apb);
> + }
> +
> + dev->dev = &pdev->dev;
> + dev->shift = PWMDAC_SHIFT_8;
> + dev->duty_cycle = PWMDAC_CYCLE_CENTER;
> + dev->cnt_n = PWMDAC_SAMPLE_CNT_1;
> + dev->data_change = NO_CHANGE;
> + dev->data_mode = INVERTER_DATA_MSB;
> + dev->data_shift = PWMDAC_DATA_LEFT_SHIFT_BIT_0;
> +
> + dev_set_drvdata(&pdev->dev, dev);
> + ret = devm_snd_soc_register_component(&pdev->dev,
> + &jh7110_pwmdac_component,
> + &jh7110_pwmdac_dai, 1);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to register dai\n");
> + return ret;
> + }
> +
> + ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to register pcm\n");
> + return ret;
> + }
> +
> + pm_runtime_enable(dev->dev);
> + if (!pm_runtime_enabled(&pdev->dev)) {
> + ret = jh7110_pwmdac_runtime_resume(&pdev->dev);
> + if (ret)
> + goto err_pm_disable;
> + }
> +
> + return 0;
> +
> +err_pm_disable:
> + pm_runtime_disable(&pdev->dev);
> +
> + return ret;
> +}
> +
> +static int jh7110_pwmdac_remove(struct platform_device *pdev)
> +{
> + pm_runtime_disable(&pdev->dev);
> + return 0;
> +}
> +
> +static const struct of_device_id jh7110_pwmdac_of_match[] = {
> + { .compatible = "starfive,jh7110-pwmdac" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, jh7110_pwmdac_of_match);
> +
> +static struct platform_driver jh7110_pwmdac_driver = {
> + .driver = {
> + .name = "jh7110-pwmdac",
> + .of_match_table = jh7110_pwmdac_of_match,
> + .pm = pm_ptr(&jh7110_pwmdac_pm_ops),
> + },
> + .probe = jh7110_pwmdac_probe,
> + .remove = jh7110_pwmdac_remove,
> +};
> +module_platform_driver(jh7110_pwmdac_driver);
> +
> +MODULE_AUTHOR("Jenny Zhang");
> +MODULE_AUTHOR("Curry Zhang");
> +MODULE_AUTHOR("Xingyu Wu <[email protected]>");
> +MODULE_AUTHOR("Hal Feng <[email protected]>");
> +MODULE_DESCRIPTION("StarFive JH7110 PWM-DAC driver");
> +MODULE_LICENSE("GPL");
On 26/06/2023 13:09, Hal Feng wrote:
> Add PWM-DAC support for StarFive JH7110 SoC.
>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> .../jh7110-starfive-visionfive-2.dtsi | 50 +++++++++++++++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 13 +++++
> 2 files changed, 63 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index 19b5954ee72d..5ca66a65e722 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -36,6 +36,34 @@ gpio-restart {
> gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
> priority = <224>;
> };
> +
> + pwmdac_dit: pwmdac-dit {
> + compatible = "starfive,jh7110-pwmdac-dit";
> + #sound-dai-cells = <0>;
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + simple-audio-card,dai-link@0 {
> + reg = <0>;
> + format = "left_j";
> + bitclock-master = <&sndcpu0>;
> + frame-master = <&sndcpu0>;
> + status = "okay";
Drop
> +
> + sndcpu0: cpu {
> + sound-dai = <&pwmdac>;
> + };
> +
> + codec {
> + sound-dai = <&pwmdac_dit>;
You said it is a transmitter, not a codec...
Best regards,
Krzysztof
On 26/06/2023 13:09, Hal Feng wrote:
> Add a dummy transmitter driver for StarFive JH7110 PWM-DAC module.
> StarFive JH7110 PWM-DAC controller uses this driver.
>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> sound/soc/codecs/Kconfig | 4 ++
> sound/soc/codecs/Makefile | 2 +
> sound/soc/codecs/jh7110_pwmdac_transmitter.c | 74 ++++++++++++++++++++
> 3 files changed, 80 insertions(+)
> create mode 100644 sound/soc/codecs/jh7110_pwmdac_transmitter.c
>
...
> +
> +static struct platform_driver pwmdac_dit_driver = {
> + .probe = pwmdac_dit_probe,
> + .driver = {
> + .name = DRV_NAME,
> + .of_match_table = of_match_ptr(pwmdac_dit_dt_ids),
> + },
> +};
> +
> +module_platform_driver(pwmdac_dit_driver);
> +
> +MODULE_DESCRIPTION("StarFive JH7110 dummy PWM-DAC transmitter driver");
> +MODULE_LICENSE("GPL");
> +MODULE_ALIAS("platform:" DRV_NAME);
Drop. You don't need it. If you need it, it means you miss proper ID table.
Best regards,
Krzysztof
On Mon, 26 Jun 2023 17:33:57 +0200, Krzysztof Kozlowski wrote:
> On 26/06/2023 13:09, Hal Feng wrote:
>> Add a dummy transmitter driver for StarFive JH7110 PWM-DAC module.
>> StarFive JH7110 PWM-DAC controller uses this driver.
>>
>> Signed-off-by: Hal Feng <[email protected]>
>> ---
>> sound/soc/codecs/Kconfig | 4 ++
>> sound/soc/codecs/Makefile | 2 +
>> sound/soc/codecs/jh7110_pwmdac_transmitter.c | 74 ++++++++++++++++++++
>> 3 files changed, 80 insertions(+)
>> create mode 100644 sound/soc/codecs/jh7110_pwmdac_transmitter.c
>>
>
> ...
>
>> +
>> +static struct platform_driver pwmdac_dit_driver = {
>> + .probe = pwmdac_dit_probe,
>> + .driver = {
>> + .name = DRV_NAME,
>> + .of_match_table = of_match_ptr(pwmdac_dit_dt_ids),
>> + },
>> +};
>> +
>> +module_platform_driver(pwmdac_dit_driver);
>> +
>> +MODULE_DESCRIPTION("StarFive JH7110 dummy PWM-DAC transmitter driver");
>> +MODULE_LICENSE("GPL");
>> +MODULE_ALIAS("platform:" DRV_NAME);
>
> Drop. You don't need it. If you need it, it means you miss proper ID table.
OK. I will drop it in the next version. Thanks.
Best regards,
Hal
On Mon, 26 Jun 2023 17:37:35 +0200, Krzysztof Kozlowski wrote:
> On 26/06/2023 13:09, Hal Feng wrote:
>> Add PWM-DAC support for StarFive JH7110 SoC.
>>
>> Signed-off-by: Hal Feng <[email protected]>
>> ---
>> .../jh7110-starfive-visionfive-2.dtsi | 50 +++++++++++++++++++
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 13 +++++
>> 2 files changed, 63 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> index 19b5954ee72d..5ca66a65e722 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -36,6 +36,34 @@ gpio-restart {
>> gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
>> priority = <224>;
>> };
>> +
>> + pwmdac_dit: pwmdac-dit {
>> + compatible = "starfive,jh7110-pwmdac-dit";
>> + #sound-dai-cells = <0>;
>> + };
>> +
>> + sound {
>> + compatible = "simple-audio-card";
>> + simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + simple-audio-card,dai-link@0 {
>> + reg = <0>;
>> + format = "left_j";
>> + bitclock-master = <&sndcpu0>;
>> + frame-master = <&sndcpu0>;
>> + status = "okay";
>
> Drop
OK.
>
>> +
>> + sndcpu0: cpu {
>> + sound-dai = <&pwmdac>;
>> + };
>> +
>> + codec {
>> + sound-dai = <&pwmdac_dit>;
>
> You said it is a transmitter, not a codec...
It is a dummy codec, also known as a dummy transmitter.
Best regards,
Hal