This series hooks up the individual clocks for each pin controller in the
gs101 DTS.
On Google Tensor gs101 there are separate bus clocks / gates each for each
pinctrl instance. To be able to access each pinctrl instance's registers,
this bus clock needs to be running, otherwise register access will hang.
The driver update to support this extra clock has been proposed in
https://lore.kernel.org/r/[email protected]
This series depends on:
* hsi2 series:
https://lore.kernel.org/r/[email protected]
* pin controller clock support:
https://lore.kernel.org/r/[email protected]
Signed-off-by: André Draszik <[email protected]>
---
Changes in v2:
- use <0> instead of a placeholder clock (Krzysztof)
- Link to v1: https://lore.kernel.org/r/20240429-samsung-pinctrl-busclock-dts-v1-0-5e935179f3ca@linaro.org
---
André Draszik (4):
arm64: dts: exynos: gs101: specify bus clock for pinctrl (far) alive
arm64: dts: exynos: gs101: specify bus clock for pinctrl_peric[01]
arm64: dts: exynos: gs101: specify bus clock for pinctrl_hsi2
arm64: dts: exynos: gs101: specify empty clocks for remaining pinctrl
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
---
base-commit: d04466706db5e241ee026f17b5f920e50dee26b5
change-id: 20240429-samsung-pinctrl-busclock-dts-46b223471541
Best regards,
--
André Draszik <[email protected]>
This bus clock is needed for pinctrl register access to work. Add it.
Signed-off-by: André Draszik <[email protected]>
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index e3b068c1a2c1..f2c7c2a4ce1c 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1348,6 +1348,8 @@ pmu_system_controller: system-controller@17460000 {
pinctrl_gpio_alive: pinctrl@174d0000 {
compatible = "google,gs101-pinctrl";
reg = <0x174d0000 0x00001000>;
+ clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK>;
+ clock-names = "pclk";
wakeup-interrupt-controller {
compatible = "google,gs101-wakeup-eint",
@@ -1359,6 +1361,8 @@ wakeup-interrupt-controller {
pinctrl_far_alive: pinctrl@174e0000 {
compatible = "google,gs101-pinctrl";
reg = <0x174e0000 0x00001000>;
+ clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK>;
+ clock-names = "pclk";
wakeup-interrupt-controller {
compatible = "google,gs101-wakeup-eint",
--
2.44.0.769.g3c40516874-goog
This bus clock is needed for pinctrl register access to work. Add it.
Signed-off-by: André Draszik <[email protected]>
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 8d4216cbab2e..f8fcbbb06e7b 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1327,6 +1327,8 @@ cmu_hsi2: clock-controller@14400000 {
pinctrl_hsi2: pinctrl@14440000 {
compatible = "google,gs101-pinctrl";
reg = <0x14440000 0x00001000>;
+ clocks = <&cmu_hsi2 CLK_GOUT_HSI2_GPIO_HSI2_PCLK>;
+ clock-names = "pclk";
interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
};
--
2.44.0.769.g3c40516874-goog
The pinctrl instances hsi1, gsactrl, and gsacore need a clock for
register access to work.
Since we haven't implemented the relevant CMUs for the clocks required
by these instances just add empty clocks for now so as to make the DT
pass the validation checks.
Once the clocks are implmented in the gs101 clock driver, these should
be updated then.
Signed-off-by: André Draszik <[email protected]>
---
v2: use empty clock instead of placeholder
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index f8fcbbb06e7b..c8a5eb8c7d45 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1309,6 +1309,9 @@ usbdrd31_dwc3: usb@0 {
pinctrl_hsi1: pinctrl@11840000 {
compatible = "google,gs101-pinctrl";
reg = <0x11840000 0x00001000>;
+ /* TODO: update once support for this CMU exists */
+ clocks = <0>;
+ clock-names = "pclk";
interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
};
@@ -1380,11 +1383,17 @@ wakeup-interrupt-controller {
pinctrl_gsactrl: pinctrl@17940000 {
compatible = "google,gs101-pinctrl";
reg = <0x17940000 0x00001000>;
+ /* TODO: update once support for this CMU exists */
+ clocks = <0>;
+ clock-names = "pclk";
};
pinctrl_gsacore: pinctrl@17a80000 {
compatible = "google,gs101-pinctrl";
reg = <0x17a80000 0x00001000>;
+ /* TODO: update once support for this CMU exists */
+ clocks = <0>;
+ clock-names = "pclk";
};
cmu_top: clock-controller@1e080000 {
--
2.44.0.769.g3c40516874-goog
This bus clock is needed for pinctrl register access to work. Add it.
Signed-off-by: André Draszik <[email protected]>
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index f2c7c2a4ce1c..8d4216cbab2e 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -370,6 +370,8 @@ sysreg_peric0: syscon@10820000 {
pinctrl_peric0: pinctrl@10840000 {
compatible = "google,gs101-pinctrl";
reg = <0x10840000 0x00001000>;
+ clocks = <&cmu_peric0 CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK>;
+ clock-names = "pclk";
interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
};
@@ -914,6 +916,8 @@ sysreg_peric1: syscon@10c20000 {
pinctrl_peric1: pinctrl@10c40000 {
compatible = "google,gs101-pinctrl";
reg = <0x10c40000 0x00001000>;
+ clocks = <&cmu_peric1 CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK>;
+ clock-names = "pclk";
interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
};
--
2.44.0.769.g3c40516874-goog
Reviewed-by: Tudor Ambarus <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
All 4 patches could have been squashed in a single patch as they do the
same thing, but I'm fine either way:
Reviewed-by: Tudor Ambarus <[email protected]>
On Thu, 2024-05-02 at 07:51 +0100, Tudor Ambarus wrote:
>
> All 4 patches could have been squashed in a single patch as they do the
> same thing, but I'm fine either way:
>
> Reviewed-by: Tudor Ambarus <[email protected]>
I guess the patches had accumulated gradually over a period of time while
more CMU support was being implemented.
I'm happy to squash them if that's the preference? Krzysztof?
Cheers,
Andre'
On 02/05/2024 12:44, André Draszik wrote:
> On Thu, 2024-05-02 at 07:51 +0100, Tudor Ambarus wrote:
>>
>> All 4 patches could have been squashed in a single patch as they do the
>> same thing, but I'm fine either way:
>>
>> Reviewed-by: Tudor Ambarus <[email protected]>
>
> I guess the patches had accumulated gradually over a period of time while
> more CMU support was being implemented.
>
> I'm happy to squash them if that's the preference? Krzysztof?
It's fine.
Best regards,
Krzysztof
On Tue, 30 Apr 2024 10:49:45 +0100, André Draszik wrote:
> This series hooks up the individual clocks for each pin controller in the
> gs101 DTS.
>
> On Google Tensor gs101 there are separate bus clocks / gates each for each
> pinctrl instance. To be able to access each pinctrl instance's registers,
> this bus clock needs to be running, otherwise register access will hang.
>
> [...]
Applied, thanks!
[1/4] arm64: dts: exynos: gs101: specify bus clock for pinctrl (far) alive
https://git.kernel.org/krzk/linux/c/1665b303a00c1acb2fe126486c6256c755f0b7c4
[2/4] arm64: dts: exynos: gs101: specify bus clock for pinctrl_peric[01]
https://git.kernel.org/krzk/linux/c/42e3f188b238b7fb1c42dee8b4dc4107cbb321e2
[3/4] arm64: dts: exynos: gs101: specify bus clock for pinctrl_hsi2
https://git.kernel.org/krzk/linux/c/8120dc4656aedf86c24e1b5776f84fdd9f8ece80
[4/4] arm64: dts: exynos: gs101: specify empty clocks for remaining pinctrl
https://git.kernel.org/krzk/linux/c/4db286b0a29aa3576a401b637ac5910dac22117f
Best regards,
--
Krzysztof Kozlowski <[email protected]>