The purpose of this series is to add the display support for the mt8365-evk.
This is the list of HWs / IPs support added:
- Connectors (HW):
- HDMI
- MIPI DSI (Mobile Industry Processor Interface Display Serial Interface)
- HDMI bridge (it66121)
- DSI pannel (startek,kd070fhfid015)
- SoC display blocks (IP):
- OVL0 (Overlay)
- RDMA0 (Data Path Read DMA)
- Color0
- CCorr0 (Color Correction)
- AAL0 (Adaptive Ambient Light)
- GAMMA0
- Dither0
- DSI0 (Display Serial Interface)
- RDMA1 (Data Path Read DMA)
- DPI0 (Display Parallel Interface)
The Mediatek DSI, DPI and DRM drivers are also improved.
Regards,
Alex
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Changes in v2:
- s/binding/compatible/ in commit messages/titles.
- Improve commit messages as Conor suggest.
- pwm-disp: Set power domain property for MT8365. This one is optionnal
and can be used for other SoC.
- Fix mediatek,dsi.yaml issue.
- Remove the extra clock in the DPI node/driver and fix the dpi clock
parenting to be consistent with the DPI clock assignement.
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Alexandre Mergnat (16):
dt-bindings: display: mediatek: aal: add compatible for MT8365 SoC
dt-bindings: display: mediatek: ccorr: add compatible for MT8365 SoC
dt-bindings: display: mediatek: color: add compatible for MT8365 SoC
dt-bindings: display: mediatek: dither: add compatible for MT8365 SoC
dt-bindings: display: mediatek: dsi: add compatible for MT8365 SoC
dt-bindings: display: mediatek: dpi: add compatible for MT8365
dt-bindings: display: mediatek: gamma: add compatible for MT8365 SoC
dt-bindings: display: mediatek: ovl: add compatible for MT8365 SoC
dt-bindings: display: mediatek: rdma: add compatible for MT8365 SoC
dt-bindings: pwm: mediatek,pwm-disp: add power-domains property
dt-bindings: pwm: mediatek,pwm-disp: add compatible for mt8365 SoC
drm/mediatek: dsi: Improves the DSI lane setup robustness
drm/mediatek: add mt8365 dpi support
arm64: defconfig: enable display connector support
arm64: dts: mediatek: add display blocks support for the MT8365 SoC
arm64: dts: mediatek: add display support for mt8365-evk
Fabien Parent (2):
dt-bindings: display: mediatek: dpi: add power-domains property
drm/mediatek: add MT8365 SoC support
.../bindings/display/mediatek/mediatek,aal.yaml | 1 +
.../bindings/display/mediatek/mediatek,ccorr.yaml | 3 +
.../bindings/display/mediatek/mediatek,color.yaml | 1 +
.../bindings/display/mediatek/mediatek,dither.yaml | 1 +
.../bindings/display/mediatek/mediatek,dpi.yaml | 6 +
.../bindings/display/mediatek/mediatek,dsi.yaml | 1 +
.../bindings/display/mediatek/mediatek,gamma.yaml | 1 +
.../bindings/display/mediatek/mediatek,ovl.yaml | 1 +
.../bindings/display/mediatek/mediatek,rdma.yaml | 1 +
.../devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 7 +
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 182 +++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 146 +++++++++++++++++
arch/arm64/configs/defconfig | 1 +
drivers/clk/mediatek/clk-mt8365-mm.c | 2 +-
drivers/gpu/drm/mediatek/mtk_dpi.c | 18 ++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 30 ++++
drivers/gpu/drm/mediatek/mtk_dsi.c | 2 +
17 files changed, 403 insertions(+), 1 deletion(-)
---
base-commit: 890c94ce8a456aa4d7ead5f5fd2603b98dfe7b7e
change-id: 20231023-display-support-c6418b30e419
Best regards,
--
Alexandre Mergnat <[email protected]>
Document the display Color Correction on MT8365, which is compatible
with that of the MT8183.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
index 8c2a737237f2..9f8366763831 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
@@ -24,6 +24,9 @@ properties:
- enum:
- mediatek,mt8183-disp-ccorr
- mediatek,mt8192-disp-ccorr
+ - items:
+ - const: mediatek,mt8365-disp-ccorr
+ - const: mediatek,mt8183-disp-ccorr
- items:
- enum:
- mediatek,mt8186-disp-ccorr
--
2.25.1
Document the Display Serial Interface on MT8365, which is compatible
with that of the MT8183.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
index 8611319bed2e..a7aa8fcb0dd1 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
@@ -37,6 +37,7 @@ properties:
- items:
- enum:
- mediatek,mt8195-dsi
+ - mediatek,mt8365-dsi
- const: mediatek,mt8183-dsi
reg:
--
2.25.1
Document the display Overlay on MT8365, which is compatible
with that of the MT8192.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
index c471a181d125..d55611c7ce5e 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
@@ -44,6 +44,7 @@ properties:
- items:
- enum:
- mediatek,mt8186-disp-ovl
+ - mediatek,mt8365-disp-ovl
- const: mediatek,mt8192-disp-ovl
reg:
--
2.25.1
Add a compatible string for MediaTek Genio 350 MT8365's display PWM
block: this is the same as MT8183.
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
index f8988af05287..180dd8366935 100644
--- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
+++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
@@ -31,6 +31,7 @@ properties:
- mediatek,mt8188-disp-pwm
- mediatek,mt8192-disp-pwm
- mediatek,mt8195-disp-pwm
+ - mediatek,mt8365-disp-pwm
- const: mediatek,mt8183-disp-pwm
reg:
--
2.25.1
- Add compatibles and platform data into the Mediatek DPI driver.
- Fix the DPI0 parent clock to be consistent.
This SoC is compatible with the mt8183 calculate factor.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
drivers/clk/mediatek/clk-mt8365-mm.c | 2 +-
drivers/gpu/drm/mediatek/mtk_dpi.c | 18 ++++++++++++++++++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mt8365-mm.c b/drivers/clk/mediatek/clk-mt8365-mm.c
index 01a2ef8f594e..3f62ec750733 100644
--- a/drivers/clk/mediatek/clk-mt8365-mm.c
+++ b/drivers/clk/mediatek/clk-mt8365-mm.c
@@ -53,7 +53,7 @@ static const struct mtk_gate mm_clks[] = {
GATE_MM0(CLK_MM_MM_DSI0, "mm_dsi0", "mm_sel", 17),
GATE_MM0(CLK_MM_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 18),
GATE_MM0(CLK_MM_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 19),
- GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "vpll_dpix", 20),
+ GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "dpi0_sel", 20),
GATE_MM0(CLK_MM_MM_FAKE, "mm_fake", "mm_sel", 21),
GATE_MM0(CLK_MM_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 22),
GATE_MM0(CLK_MM_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 23),
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index beb7d9d08e97..a4f9376ee472 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -997,6 +997,23 @@ static const struct mtk_dpi_conf mt8195_dpintf_conf = {
.csc_enable_bit = DPINTF_CSC_ENABLE,
};
+static const struct mtk_dpi_conf mt8365_conf = {
+ .cal_factor = mt8183_calculate_factor,
+ .reg_h_fre_con = 0xe0,
+ .max_clock_khz = 150000,
+ .output_fmts = mt8183_output_fmts,
+ .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
+ .pixels_per_iter = 1,
+ .is_ck_de_pol = true,
+ .swap_input_support = true,
+ .support_direct_pin = true,
+ .dimension_mask = HPW_MASK,
+ .hvsize_mask = HSIZE_MASK,
+ .channel_swap_shift = CH_SWAP,
+ .yuv422_en_bit = YUV422_EN,
+ .csc_enable_bit = CSC_ENABLE,
+};
+
static int mtk_dpi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -1092,6 +1109,7 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
{ .compatible = "mediatek,mt8188-dp-intf", .data = &mt8195_dpintf_conf },
{ .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf },
{ .compatible = "mediatek,mt8195-dp-intf", .data = &mt8195_dpintf_conf },
+ { .compatible = "mediatek,mt8365-dpi", .data = &mt8365_conf },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
--
2.25.1
- Add aliases for each display components to help display drivers.
- Add the Display Pulse Width Modulation (DISP_PWM) to provide PWM signals
for the LED driver of mobile LCM.
- Add the MIPI Display Serial Interface (DSI) PHY support. (up to 4-lane
output)
- Add the display mutex support.
- Add the following display component support:
- OVL0 (Overlay)
- RDMA0 (Data Path Read DMA)
- Color0
- CCorr0 (Color Correction)
- AAL0 (Adaptive Ambient Light)
- GAMMA0
- Dither0
- DSI0 (Display Serial Interface)
- RDMA1 (Data Path Read DMA)
- DPI0 (Display Parallel Interface)
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 146 +++++++++++++++++++++++++++++++
1 file changed, 146 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index 24581f7410aa..a95f90da4491 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mediatek,mt8365-larb-port.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mediatek,mt8365-power.h>
@@ -17,6 +18,19 @@ / {
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ aal0 = &aal0;
+ ccorr0 = &ccorr0;
+ color0 = &color0;
+ dither0 = &dither0;
+ dpi0 = &dpi0;
+ dsi0 = &dsi0;
+ gamma0 = &gamma0;
+ ovl0 = &ovl0;
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -607,6 +621,17 @@ spi: spi@1100a000 {
status = "disabled";
};
+ disp_pwm: pwm@1100e000 {
+ compatible = "mediatek,mt8365-disp-pwm",
+ "mediatek,mt8183-disp-pwm";
+ reg = <0 0x1100e000 0 0x1000>;
+ clock-names = "main", "mm";
+ clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
+ <&infracfg CLK_IFR_DISP_PWM>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ #pwm-cells = <2>;
+ };
+
i2c3: i2c@1100f000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>;
@@ -703,6 +728,15 @@ ethernet: ethernet@112a0000 {
status = "disabled";
};
+ mipi_tx0: dsi-phy@11c00000 {
+ compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx";
+ reg = <0 0x11c00000 0 0x800>;
+ clock-output-names = "mipi_tx0_pll";
+ clocks = <&clk26m>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+
u3phy: t-phy@11cc0000 {
compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
#address-cells = <1>;
@@ -732,6 +766,13 @@ mmsys: syscon@14000000 {
#clock-cells = <1>;
};
+ mutex: mutex@14001000 {
+ compatible = "mediatek,mt8365-disp-mutex";
+ reg = <0 0x14001000 0 0x1000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
smi_common: smi@14002000 {
compatible = "mediatek,mt8365-smi-common";
reg = <0 0x14002000 0 0x1000>;
@@ -755,6 +796,111 @@ larb0: larb@14003000 {
mediatek,larb-id = <0>;
};
+ ovl0: ovl@1400b000 {
+ compatible = "mediatek,mt8365-disp-ovl",
+ "mediatek,mt8192-disp-ovl";
+ reg = <0 0x1400b000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_OVL0>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_DISP_OVL0>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ rdma0: rdma@1400d000 {
+ compatible = "mediatek,mt8365-disp-rdma",
+ "mediatek,mt8183-disp-rdma";
+ reg = <0 0x1400d000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_RDMA0>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA0>;
+ mediatek,rdma-fifo-size = <5120>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ color0: color@1400f000 {
+ compatible = "mediatek,mt8365-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x1400f000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ ccorr0: ccorr@14010000 {
+ compatible = "mediatek,mt8365-disp-ccorr",
+ "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x14010000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ aal0: aal@14011000 {
+ compatible = "mediatek,mt8365-disp-aal",
+ "mediatek,mt8183-disp-aal";
+ reg = <0 0x14011000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_AAL0>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ gamma0: gamma@14012000 {
+ compatible = "mediatek,mt8365-disp-gamma",
+ "mediatek,mt8183-disp-gamma";
+ reg = <0 0x14012000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ dither0: dither@14013000 {
+ compatible = "mediatek,mt8365-disp-dither",
+ "mediatek,mt8183-disp-dither";
+ reg = <0 0x14013000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ dsi0: dsi@14014000 {
+ compatible = "mediatek,mt8365-dsi",
+ "mediatek,mt8183-dsi";
+ reg = <0 0x14014000 0 0x1000>;
+ clock-names = "engine", "digital", "hs";
+ clocks = <&mmsys CLK_MM_MM_DSI0>,
+ <&mmsys CLK_MM_DSI0_DIG_DSI>,
+ <&mipi_tx0>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
+ phy-names = "dphy";
+ phys = <&mipi_tx0>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ rdma1: rdma@14016000 {
+ compatible = "mediatek,mt8365-disp-rdma",
+ "mediatek,mt8183-disp-rdma";
+ reg = <0 0x14016000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_RDMA1>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA1>;
+ mediatek,rdma-fifo-size = <2048>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ dpi0: dpi@14018000 {
+ compatible = "mediatek,mt8365-dpi";
+ reg = <0 0x14018000 0 0x1000>;
+ assigned-clocks = <&mmsys CLK_MM_DPI0_DPI0>;
+ assigned-clock-parents = <&topckgen CLK_TOP_LVDSPLL_D4>;
+ clocks = <&mmsys CLK_MM_DPI0_DPI0>,
+ <&mmsys CLK_MM_MM_DPI0>,
+ <&apmixedsys CLK_APMIXED_LVDSPLL>;
+ clock-names = "pixel", "engine", "pll";
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ status = "disabled";
+ };
+
camsys: syscon@15000000 {
compatible = "mediatek,mt8365-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
--
2.25.1
MIPI DSI:
- Add "vsys_lcm_reg" regulator support and setup the "mt6357_vsim1_reg",
to power the pannel plugged to the DSI connector.
- Setup the Display Parallel Interface.
- Add the startek kd070fhfid015 pannel support.
HDMI:
- Add HDMI connector support.
- Add the "ite,it66121" HDMI bridge support, driven by I2C1.
- Setup the Display Parallel Interface.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 182 ++++++++++++++++++++++++++++
1 file changed, 182 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
index 50cbaefa1a99..4afdcbefc481 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -26,6 +26,18 @@ chosen {
stdout-path = "serial0:921600n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "d";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_connector_out>;
+ };
+ };
+ };
+
firmware {
optee {
compatible = "linaro,optee-tz";
@@ -86,6 +98,56 @@ optee_reserved: optee@43200000 {
reg = <0 0x43200000 0 0x00c00000>;
};
};
+
+ vsys_lcm_reg: regulator-vsys-lcm {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&pio 129 GPIO_ACTIVE_HIGH>;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "vsys_lcm";
+ };
+};
+
+&dpi0 {
+ pinctrl-0 = <&dpi_default_pins>;
+ pinctrl-1 = <&dpi_idle_pins>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+
+ port {
+ dpi_out: endpoint {
+ remote-endpoint = <&it66121_in>;
+ };
+ };
+};
+
+&dsi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ panel@0 {
+ compatible = "startek,kd070fhfid015";
+ status = "okay";
+ reg = <0>;
+ enable-gpios = <&pio 67 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
+ iovcc-supply = <&mt6357_vsim1_reg>;
+ power-supply = <&vsys_lcm_reg>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+
+ port {
+ dsi_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
};
&cpu0 {
@@ -138,6 +200,50 @@ &i2c0 {
status = "okay";
};
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-div = <2>;
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ it66121hdmitx: it66121hdmitx@4c {
+ #sound-dai-cells = <0>;
+ compatible = "ite,it66121";
+ interrupt-parent = <&pio>;
+ interrupts = <68 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&ite_pins>;
+ pinctrl-names = "default";
+ reg = <0x4c>;
+ reset-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
+ vcn18-supply = <&mt6357_vsim2_reg>;
+ vcn33-supply = <&mt6357_vibr_reg>;
+ vrf12-supply = <&mt6357_vrf12_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ it66121_in: endpoint {
+ bus-width = <12>;
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ hdmi_connector_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+};
+
&mmc0 {
assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
@@ -180,7 +286,55 @@ &mt6357_pmic {
#interrupt-cells = <2>;
};
+&mt6357_vsim1_reg {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+};
+
&pio {
+ dpi_default_pins: dpi-default-pins {
+ pins {
+ pinmux = <MT8365_PIN_0_GPIO0__FUNC_DPI_D0>,
+ <MT8365_PIN_1_GPIO1__FUNC_DPI_D1>,
+ <MT8365_PIN_2_GPIO2__FUNC_DPI_D2>,
+ <MT8365_PIN_3_GPIO3__FUNC_DPI_D3>,
+ <MT8365_PIN_4_GPIO4__FUNC_DPI_D4>,
+ <MT8365_PIN_5_GPIO5__FUNC_DPI_D5>,
+ <MT8365_PIN_6_GPIO6__FUNC_DPI_D6>,
+ <MT8365_PIN_7_GPIO7__FUNC_DPI_D7>,
+ <MT8365_PIN_8_GPIO8__FUNC_DPI_D8>,
+ <MT8365_PIN_9_GPIO9__FUNC_DPI_D9>,
+ <MT8365_PIN_10_GPIO10__FUNC_DPI_D10>,
+ <MT8365_PIN_11_GPIO11__FUNC_DPI_D11>,
+ <MT8365_PIN_12_GPIO12__FUNC_DPI_DE>,
+ <MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC>,
+ <MT8365_PIN_14_GPIO14__FUNC_DPI_CK>,
+ <MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC>;
+ drive-strength = <MTK_DRIVE_4mA>;
+ };
+ };
+
+ dpi_idle_pins: dpi-idle-pins {
+ pins {
+ pinmux = <MT8365_PIN_0_GPIO0__FUNC_GPIO0>,
+ <MT8365_PIN_1_GPIO1__FUNC_GPIO1>,
+ <MT8365_PIN_2_GPIO2__FUNC_GPIO2>,
+ <MT8365_PIN_3_GPIO3__FUNC_GPIO3>,
+ <MT8365_PIN_4_GPIO4__FUNC_GPIO4>,
+ <MT8365_PIN_5_GPIO5__FUNC_GPIO5>,
+ <MT8365_PIN_6_GPIO6__FUNC_GPIO6>,
+ <MT8365_PIN_7_GPIO7__FUNC_GPIO7>,
+ <MT8365_PIN_8_GPIO8__FUNC_GPIO8>,
+ <MT8365_PIN_9_GPIO9__FUNC_GPIO9>,
+ <MT8365_PIN_10_GPIO10__FUNC_GPIO10>,
+ <MT8365_PIN_11_GPIO11__FUNC_GPIO11>,
+ <MT8365_PIN_12_GPIO12__FUNC_GPIO12>,
+ <MT8365_PIN_13_GPIO13__FUNC_GPIO13>,
+ <MT8365_PIN_14_GPIO14__FUNC_GPIO14>,
+ <MT8365_PIN_15_GPIO15__FUNC_GPIO15>;
+ };
+ };
+
ethernet_pins: ethernet-pins {
phy_reset_pins {
pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
@@ -222,6 +376,34 @@ pins {
};
};
+ i2c1_pins: i2c1-pins {
+ pins {
+ pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>,
+ <MT8365_PIN_60_SCL1__FUNC_SCL1_0>;
+ bias-pull-up;
+ };
+ };
+
+ ite_pins: ite-pins {
+
+ irq_ite_pins {
+ pinmux = <MT8365_PIN_68_CMDAT0__FUNC_GPIO68>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pwr_pins {
+ pinmux = <MT8365_PIN_70_CMDAT2__FUNC_GPIO70>,
+ <MT8365_PIN_71_CMDAT3__FUNC_GPIO71>;
+ output-high;
+ };
+
+ rst_ite_pins {
+ pinmux = <MT8365_PIN_69_CMDAT1__FUNC_GPIO69>;
+ output-high;
+ };
+ };
+
mmc0_default_pins: mmc0-default-pins {
clk-pins {
pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
--
2.25.1
From: Fabien Parent <[email protected]>
DPI is part of the display / multimedia block in MediaTek SoCs, and
always have a power-domain (at least in the upstream device-trees).
Add the power-domains property to the binding documentation.
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index 803c00f26206..e126486e8eac 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -64,6 +64,9 @@ properties:
Output port node. This port should be connected to the input port of an
attached HDMI, LVDS or DisplayPort encoder chip.
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
@@ -78,11 +81,13 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
dpi0: dpi@1401d000 {
compatible = "mediatek,mt8173-dpi";
reg = <0x1401d000 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DPI_PIXEL>,
<&mmsys CLK_MM_DPI_ENGINE>,
<&apmixedsys CLK_APMIXED_TVDPLL>;
--
2.25.1
Document the display Adaptive Ambient Light on MT8365, which is compatible
with that of the MT8183.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
index b4c28e96dd55..cf24434854ff 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
@@ -36,6 +36,7 @@ properties:
- mediatek,mt8188-disp-aal
- mediatek,mt8192-disp-aal
- mediatek,mt8195-disp-aal
+ - mediatek,mt8365-disp-aal
- const: mediatek,mt8183-disp-aal
reg:
--
2.25.1
Document the display Color on MT8365, which is compatible
with that of the MT8173.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
index b886ca0d89ea..7df786bbad20 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
@@ -40,6 +40,7 @@ properties:
- mediatek,mt8188-disp-color
- mediatek,mt8192-disp-color
- mediatek,mt8195-disp-color
+ - mediatek,mt8365-disp-color
- const: mediatek,mt8173-disp-color
reg:
maxItems: 1
--
2.25.1
Document the display Dither on MT8365, which is compatible
with that of the MT8183.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
index 1588b3f7cec7..6fceb1f95d2a 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
@@ -30,6 +30,7 @@ properties:
- mediatek,mt8188-disp-dither
- mediatek,mt8192-disp-dither
- mediatek,mt8195-disp-dither
+ - mediatek,mt8365-disp-dither
- const: mediatek,mt8183-disp-dither
reg:
--
2.25.1
Document the display Gamma on MT8365, which is compatible
with that of the MT8183.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
index c6641acd75d6..f447f4320e8b 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
@@ -34,6 +34,7 @@ properties:
- mediatek,mt8188-disp-gamma
- mediatek,mt8192-disp-gamma
- mediatek,mt8195-disp-gamma
+ - mediatek,mt8365-disp-gamma
- const: mediatek,mt8183-disp-gamma
reg:
--
2.25.1
Enable this feature for the i350-evk HDMI connector support.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index fce98a150014..1df337882835 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -872,6 +872,7 @@ CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=m
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m
CONFIG_DRM_FSL_LDB=m
+CONFIG_DRM_DISPLAY_CONNECTOR=m
CONFIG_DRM_LONTIUM_LT8912B=m
CONFIG_DRM_LONTIUM_LT9611=m
CONFIG_DRM_LONTIUM_LT9611UXC=m
--
2.25.1
Currently, mtk_dsi_lane_ready (which setup the DSI lane) is triggered
before mtk_dsi_poweron. lanes_ready flag toggle to true during
mtk_dsi_lane_ready function, and the DSI module is set up during
mtk_dsi_poweron.
Later, during panel driver init, mtk_dsi_lane_ready is triggered but does
nothing because lanes are considered ready. Unfortunately, when the panel
driver try to communicate, the DSI returns a timeout.
The solution found here is to put lanes_ready flag to false after the DSI
module setup into mtk_dsi_poweron to init the DSI lanes after the power /
setup of the DSI module.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 9501f4019199..b3f33d4d3d5c 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -642,6 +642,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
mtk_dsi_config_vdo_timing(dsi);
mtk_dsi_set_interrupt_enable(dsi);
+ dsi->lanes_ready = false;
+
return 0;
err_disable_engine_clk:
clk_disable_unprepare(dsi->engine_clk);
--
2.25.1
Add dt-binding documentation of dpi for MediaTek MT8365 SoC.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index e126486e8eac..ebb61bc4eab7 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -27,6 +27,7 @@ properties:
- mediatek,mt8188-dp-intf
- mediatek,mt8192-dpi
- mediatek,mt8195-dp-intf
+ - mediatek,mt8365-dpi
- items:
- enum:
- mediatek,mt6795-dpi
--
2.25.1
According to the Mediatek MT8365 datasheet, the display PWM block has
a power domain.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
index afcdeed4e88a..f8988af05287 100644
--- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
+++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
@@ -52,6 +52,12 @@ properties:
- const: main
- const: mm
+ power-domains:
+ maxItems: 1
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
required:
- compatible
- reg
--
2.25.1
From: Fabien Parent <[email protected]>
Add DRM support for MT8365 SoC.
Signed-off-by: Fabien Parent <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 74832c213092..427b601309c4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -230,6 +230,22 @@ static const unsigned int mt8195_mtk_ddp_ext[] = {
DDP_COMPONENT_DP_INTF1,
};
+static const unsigned int mt8365_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_DITHER0,
+ DDP_COMPONENT_DSI0,
+};
+
+static const unsigned int mt8365_mtk_ddp_ext[] = {
+ DDP_COMPONENT_RDMA1,
+ DDP_COMPONENT_DPI0,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -317,6 +333,14 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.mmsys_dev_num = 2,
};
+static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
+ .main_path = mt8365_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8365_mtk_ddp_main),
+ .ext_path = mt8365_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8365_mtk_ddp_ext),
+ .mmsys_dev_num = 1,
+};
+
static const struct of_device_id mtk_drm_of_ids[] = {
{ .compatible = "mediatek,mt2701-mmsys",
.data = &mt2701_mmsys_driver_data},
@@ -344,6 +368,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = &mt8195_vdosys0_driver_data},
{ .compatible = "mediatek,mt8195-vdosys1",
.data = &mt8195_vdosys1_driver_data},
+ { .compatible = "mediatek,mt8365-mmsys",
+ .data = &mt8365_mmsys_driver_data},
{ }
};
MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
@@ -729,6 +755,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8195-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8365-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
{ .compatible = "mediatek,mt2701-disp-ovl",
@@ -793,6 +821,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8188-dsi",
.data = (void *)MTK_DSI },
+ { .compatible = "mediatek,mt8365-dpi",
+ .data = (void *)MTK_DPI },
{ }
};
--
2.25.1
Document the display Data Path Read DMA on MT8365, which is compatible
with that of the MT8183.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
index 39dbb5c8bcf8..4cadb245d028 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
@@ -45,6 +45,7 @@ properties:
- enum:
- mediatek,mt8186-disp-rdma
- mediatek,mt8192-disp-rdma
+ - mediatek,mt8365-disp-rdma
- const: mediatek,mt8183-disp-rdma
reg:
--
2.25.1
Hello,
On Tue, Apr 16, 2024 at 05:53:01PM +0200, Alexandre Mergnat wrote:
> Alexandre Mergnat (16):
> [...]
> dt-bindings: pwm: mediatek,pwm-disp: add power-domains property
> dt-bindings: pwm: mediatek,pwm-disp: add compatible for mt8365 SoC
> [...]
> base-commit: 890c94ce8a456aa4d7ead5f5fd2603b98dfe7b7e
> change-id: 20231023-display-support-c6418b30e419
I cannot find 890c94ce8a456aa4d7ead5f5fd2603b98dfe7b7e, neither in next
nor in stable nor in drm-misc nor in Linus' repository.
For sure it's not based on next, because otherwise you'd have noticed
that the power-domains property is already documented there. (Currently
as fb7c3d8ba039df877886fd457538d8b24ca9c84b.)
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | https://www.pengutronix.de/ |
Hello,
On Tue, Apr 16, 2024 at 05:53:13PM +0200, Alexandre Mergnat wrote:
> Add a compatible string for MediaTek Genio 350 MT8365's display PWM
> block: this is the same as MT8183.
>
> Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
> Acked-by: Uwe Kleine-K?nig <[email protected]>
> Signed-off-by: Alexandre Mergnat <[email protected]>
I already asked in reply to v1 what the merge plan is here. There are
changes in my pwm tree to the mediatek,pwm-disp binding already. I don't
think they conflict with this patch, but maybe it's still easier to take
this via pwm?!
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | https://www.pengutronix.de/ |
On 17/04/2024 10:01, Uwe Kleine-König wrote:
> Hello,
>
> On Tue, Apr 16, 2024 at 05:53:12PM +0200, Alexandre Mergnat wrote:
>> According to the Mediatek MT8365 datasheet, the display PWM block has
>> a power domain.
>>
>> Signed-off-by: Alexandre Mergnat <[email protected]>
>
> I already pointed that out in reply to the cover letter, so just to make
> it more easily to spot for people considering to apply this patch:
>
> This is already fixed in next.
>
Hello,
Sorry I've misunderstood the previous message.
I will remove this patch for the next revision and notify it in the cover letter.
Thanks
> Best regards
> Uwe
>
--
Regards,
Alexandre
Hello,
On Tue, Apr 16, 2024 at 05:53:12PM +0200, Alexandre Mergnat wrote:
> According to the Mediatek MT8365 datasheet, the display PWM block has
> a power domain.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
I already pointed that out in reply to the cover letter, so just to make
it more easily to spot for people considering to apply this patch:
This is already fixed in next.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | https://www.pengutronix.de/ |
On 17/04/2024 09:58, Uwe Kleine-König wrote:
> Hello,
>
> On Tue, Apr 16, 2024 at 05:53:01PM +0200, Alexandre Mergnat wrote:
>> Alexandre Mergnat (16):
>> [...]
>> dt-bindings: pwm: mediatek,pwm-disp: add power-domains property
>> dt-bindings: pwm: mediatek,pwm-disp: add compatible for mt8365 SoC
>> [...]
>> base-commit: 890c94ce8a456aa4d7ead5f5fd2603b98dfe7b7e
>> change-id: 20231023-display-support-c6418b30e419
>
> I cannot find 890c94ce8a456aa4d7ead5f5fd2603b98dfe7b7e, neither in next
> nor in stable nor in drm-misc nor in Linus' repository.
>
> For sure it's not based on next, because otherwise you'd have noticed
> that the power-domains property is already documented there. (Currently
> as fb7c3d8ba039df877886fd457538d8b24ca9c84b.)
You're right, this V2 is based on v6.9-rc3
>
> Best regards
> Uwe
>
--
Regards,
Alexandre
Il 16/04/24 17:53, Alexandre Mergnat ha scritto:
> Add dt-binding documentation of dpi for MediaTek MT8365 SoC.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> index e126486e8eac..ebb61bc4eab7 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> @@ -27,6 +27,7 @@ properties:
> - mediatek,mt8188-dp-intf
> - mediatek,mt8192-dpi
> - mediatek,mt8195-dp-intf
> + - mediatek,mt8365-dpi
> - items:
> - enum:
> - mediatek,mt6795-dpi
>
MT8365 and MT8192 are identical. I'll make it easy for you:
- items:
- enum:
- mediatek,mt8365-dpi
- const: mediatek,mt8192-dpi
Cheers,
Angelo
Il 16/04/24 17:53, [email protected] ha scritto:
> From: Fabien Parent <[email protected]>
>
> DPI is part of the display / multimedia block in MediaTek SoCs, and
> always have a power-domain (at least in the upstream device-trees).
> Add the power-domains property to the binding documentation.
>
> Signed-off-by: Fabien Parent <[email protected]>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Please add the relevant Fixes tag and resubmit.
After which:
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 16/04/24 17:53, Alexandre Mergnat ha scritto:
> According to the Mediatek MT8365 datasheet, the display PWM block has
> a power domain.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
It's the same for at least MT8195, MT8183 and I think MT8192 as well... so
not having that from the beginning is actually a mistake.
Please add a Fixes tag and resend, after which:
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 16/04/24 17:53, Alexandre Mergnat ha scritto:
> Document the display Overlay on MT8365, which is compatible
> with that of the MT8192.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 16/04/24 17:53, Alexandre Mergnat ha scritto:
> Document the display Adaptive Ambient Light on MT8365, which is compatible
> with that of the MT8183.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 16/04/24 17:53, Alexandre Mergnat ha scritto:
> Document the display Color on MT8365, which is compatible
> with that of the MT8173.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 16/04/24 17:53, Alexandre Mergnat ha scritto:
> Document the display Dither on MT8365, which is compatible
> with that of the MT8183.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 16/04/24 17:53, Alexandre Mergnat ha scritto:
> Document the Display Serial Interface on MT8365, which is compatible
> with that of the MT8183.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 16/04/24 17:53, Alexandre Mergnat ha scritto:
> Document the display Color Correction on MT8365, which is compatible
> with that of the MT8183.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 16/04/24 17:53, Alexandre Mergnat ha scritto:
> Document the display Data Path Read DMA on MT8365, which is compatible
> with that of the MT8183.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 16/04/24 17:53, Alexandre Mergnat ha scritto:
> Document the display Gamma on MT8365, which is compatible
> with that of the MT8183.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 16/04/24 17:53, Alexandre Mergnat ha scritto:
> MIPI DSI:
> - Add "vsys_lcm_reg" regulator support and setup the "mt6357_vsim1_reg",
> to power the pannel plugged to the DSI connector.
> - Setup the Display Parallel Interface.
> - Add the startek kd070fhfid015 pannel support.
>
> HDMI:
> - Add HDMI connector support.
> - Add the "ite,it66121" HDMI bridge support, driven by I2C1.
> - Setup the Display Parallel Interface.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 182 ++++++++++++++++++++++++++++
> 1 file changed, 182 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> index 50cbaefa1a99..4afdcbefc481 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> @@ -26,6 +26,18 @@ chosen {
> stdout-path = "serial0:921600n8";
> };
>
> + connector {
> + compatible = "hdmi-connector";
> + label = "hdmi";
> + type = "d";
> +
> + port {
> + hdmi_connector_in: endpoint {
> + remote-endpoint = <&hdmi_connector_out>;
> + };
> + };
> + };
> +
> firmware {
> optee {
> compatible = "linaro,optee-tz";
> @@ -86,6 +98,56 @@ optee_reserved: optee@43200000 {
> reg = <0 0x43200000 0 0x00c00000>;
> };
> };
> +
> + vsys_lcm_reg: regulator-vsys-lcm {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&pio 129 GPIO_ACTIVE_HIGH>;
> + regulator-max-microvolt = <5000000>;
> + regulator-min-microvolt = <5000000>;
> + regulator-name = "vsys_lcm";
> + };
> +};
> +
> +&dpi0 {
> + pinctrl-0 = <&dpi_default_pins>;
> + pinctrl-1 = <&dpi_idle_pins>;
> + pinctrl-names = "default", "sleep";
> + status = "okay";
> +
> + port {
> + dpi_out: endpoint {
> + remote-endpoint = <&it66121_in>;
> + };
> + };
> +};
> +
> +&dsi0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + panel@0 {
> + compatible = "startek,kd070fhfid015";
> + status = "okay";
status is always okay, unless it's disabled.
> + reg = <0>;
> + enable-gpios = <&pio 67 GPIO_ACTIVE_HIGH>;
> + reset-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
> + iovcc-supply = <&mt6357_vsim1_reg>;
> + power-supply = <&vsys_lcm_reg>;
> +
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <&dsi_out>;
> + };
> + };
> + };
> +
> + port {
> + dsi_out: endpoint {
> + remote-endpoint = <&panel_in>;
> + };
> + };
> };
>
> &cpu0 {
> @@ -138,6 +200,50 @@ &i2c0 {
> status = "okay";
> };
>
> +&i2c1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-div = <2>;
> + clock-frequency = <100000>;
> + pinctrl-0 = <&i2c1_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + it66121hdmitx: it66121hdmitx@4c {
Can we please get an actually readable name for this node?
Just a suggestion (you're free to rename however you want)
it66121_hdmi: hdmi@4c {
> + #sound-dai-cells = <0>;
> + compatible = "ite,it66121";
> + interrupt-parent = <&pio>;
> + interrupts = <68 IRQ_TYPE_LEVEL_LOW>;
> + pinctrl-0 = <&ite_pins>;
> + pinctrl-names = "default";
> + reg = <0x4c>;
> + reset-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
> + vcn18-supply = <&mt6357_vsim2_reg>;
> + vcn33-supply = <&mt6357_vibr_reg>;
> + vrf12-supply = <&mt6357_vrf12_reg>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + it66121_in: endpoint {
> + bus-width = <12>;
> + remote-endpoint = <&dpi_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + hdmi_connector_out: endpoint {
> + remote-endpoint = <&hdmi_connector_in>;
> + };
> + };
> + };
> + };
> +};
> +
> &mmc0 {
> assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
> assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
> @@ -180,7 +286,55 @@ &mt6357_pmic {
> #interrupt-cells = <2>;
> };
>
> +&mt6357_vsim1_reg {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +};
> +
> &pio {
> + dpi_default_pins: dpi-default-pins {
> + pins {
> + pinmux = <MT8365_PIN_0_GPIO0__FUNC_DPI_D0>,
> + <MT8365_PIN_1_GPIO1__FUNC_DPI_D1>,
> + <MT8365_PIN_2_GPIO2__FUNC_DPI_D2>,
> + <MT8365_PIN_3_GPIO3__FUNC_DPI_D3>,
> + <MT8365_PIN_4_GPIO4__FUNC_DPI_D4>,
> + <MT8365_PIN_5_GPIO5__FUNC_DPI_D5>,
> + <MT8365_PIN_6_GPIO6__FUNC_DPI_D6>,
> + <MT8365_PIN_7_GPIO7__FUNC_DPI_D7>,
> + <MT8365_PIN_8_GPIO8__FUNC_DPI_D8>,
> + <MT8365_PIN_9_GPIO9__FUNC_DPI_D9>,
> + <MT8365_PIN_10_GPIO10__FUNC_DPI_D10>,
> + <MT8365_PIN_11_GPIO11__FUNC_DPI_D11>,
> + <MT8365_PIN_12_GPIO12__FUNC_DPI_DE>,
> + <MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC>,
> + <MT8365_PIN_14_GPIO14__FUNC_DPI_CK>,
> + <MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC>;
> + drive-strength = <MTK_DRIVE_4mA>;
drive-strength = <4> is just fine....! :-)
> + };
> + };
> +
> + dpi_idle_pins: dpi-idle-pins {
> + pins {
> + pinmux = <MT8365_PIN_0_GPIO0__FUNC_GPIO0>,
> + <MT8365_PIN_1_GPIO1__FUNC_GPIO1>,
> + <MT8365_PIN_2_GPIO2__FUNC_GPIO2>,
> + <MT8365_PIN_3_GPIO3__FUNC_GPIO3>,
> + <MT8365_PIN_4_GPIO4__FUNC_GPIO4>,
> + <MT8365_PIN_5_GPIO5__FUNC_GPIO5>,
> + <MT8365_PIN_6_GPIO6__FUNC_GPIO6>,
> + <MT8365_PIN_7_GPIO7__FUNC_GPIO7>,
> + <MT8365_PIN_8_GPIO8__FUNC_GPIO8>,
> + <MT8365_PIN_9_GPIO9__FUNC_GPIO9>,
> + <MT8365_PIN_10_GPIO10__FUNC_GPIO10>,
> + <MT8365_PIN_11_GPIO11__FUNC_GPIO11>,
> + <MT8365_PIN_12_GPIO12__FUNC_GPIO12>,
> + <MT8365_PIN_13_GPIO13__FUNC_GPIO13>,
> + <MT8365_PIN_14_GPIO14__FUNC_GPIO14>,
> + <MT8365_PIN_15_GPIO15__FUNC_GPIO15>;
> + };
> + };
> +
> ethernet_pins: ethernet-pins {
> phy_reset_pins {
> pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
> @@ -222,6 +376,34 @@ pins {
> };
> };
>
> + i2c1_pins: i2c1-pins {
> + pins {
> + pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>,
> + <MT8365_PIN_60_SCL1__FUNC_SCL1_0>;
> + bias-pull-up;
> + };
> + };
> +
> + ite_pins: ite-pins {
> +
extra blank line, please remove.
> + irq_ite_pins {
Did you run dtbs_check?!? :-)
Cheers,
Angelo
> + pinmux = <MT8365_PIN_68_CMDAT0__FUNC_GPIO68>;
> + input-enable;
> + bias-pull-up;
> + };
> +
> + pwr_pins {
> + pinmux = <MT8365_PIN_70_CMDAT2__FUNC_GPIO70>,
> + <MT8365_PIN_71_CMDAT3__FUNC_GPIO71>;
> + output-high;
> + };
> +
> + rst_ite_pins {
> + pinmux = <MT8365_PIN_69_CMDAT1__FUNC_GPIO69>;
> + output-high;
> + };
> + };
> +
> mmc0_default_pins: mmc0-default-pins {
> clk-pins {
> pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
>
Hello,
On Wed, Apr 17, 2024 at 12:19:19PM +0200, AngeloGioacchino Del Regno wrote:
> Il 16/04/24 17:53, Alexandre Mergnat ha scritto:
> > According to the Mediatek MT8365 datasheet, the display PWM block has
> > a power domain.
> >
> > Signed-off-by: Alexandre Mergnat <[email protected]>
>
> It's the same for at least MT8195, MT8183 and I think MT8192 as well... so
> not having that from the beginning is actually a mistake.
>
> Please add a Fixes tag and resend, after which:
>
> Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
You mean similar to:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=fb7c3d8ba039df877886fd457538d8b24ca9c84b
? It seems someone you know well was quicker :-)
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | https://www.pengutronix.de/ |
Il 17/04/24 15:25, Uwe Kleine-König ha scritto:
> Hello,
>
> On Wed, Apr 17, 2024 at 12:19:19PM +0200, AngeloGioacchino Del Regno wrote:
>> Il 16/04/24 17:53, Alexandre Mergnat ha scritto:
>>> According to the Mediatek MT8365 datasheet, the display PWM block has
>>> a power domain.
>>>
>>> Signed-off-by: Alexandre Mergnat <[email protected]>
>>
>> It's the same for at least MT8195, MT8183 and I think MT8192 as well... so
>> not having that from the beginning is actually a mistake.
>>
>> Please add a Fixes tag and resend, after which:
>>
>> Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
>
> You mean similar to:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=fb7c3d8ba039df877886fd457538d8b24ca9c84b
>
> ? It seems someone you know well was quicker :-)
>
> Best regards
> Uwe
>
LOL! I totally forgot that I fixed that already :-D
I need more coffee!
Cheers,
Angelo
On Tue, 16 Apr 2024 17:53:02 +0200, Alexandre Mergnat wrote:
> Document the display Adaptive Ambient Light on MT8365, which is compatible
> with that of the MT8183.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring (Arm) <[email protected]>
On Tue, 16 Apr 2024 17:53:03 +0200, Alexandre Mergnat wrote:
> Document the display Color Correction on MT8365, which is compatible
> with that of the MT8183.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
Acked-by: Rob Herring (Arm) <[email protected]>
On Tue, 16 Apr 2024 17:53:04 +0200, Alexandre Mergnat wrote:
> Document the display Color on MT8365, which is compatible
> with that of the MT8173.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring (Arm) <[email protected]>
On Tue, 16 Apr 2024 17:53:05 +0200, Alexandre Mergnat wrote:
> Document the display Dither on MT8365, which is compatible
> with that of the MT8183.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring (Arm) <[email protected]>
On Tue, 16 Apr 2024 17:53:07 +0200, [email protected] wrote:
> From: Fabien Parent <[email protected]>
>
> DPI is part of the display / multimedia block in MediaTek SoCs, and
> always have a power-domain (at least in the upstream device-trees).
> Add the power-domains property to the binding documentation.
>
> Signed-off-by: Fabien Parent <[email protected]>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
Acked-by: Rob Herring (Arm) <[email protected]>
On Tue, 16 Apr 2024 17:53:06 +0200, Alexandre Mergnat wrote:
> Document the Display Serial Interface on MT8365, which is compatible
> with that of the MT8183.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring (Arm) <[email protected]>
On Tue, 16 Apr 2024 17:53:10 +0200, Alexandre Mergnat wrote:
> Document the display Overlay on MT8365, which is compatible
> with that of the MT8192.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring (Arm) <[email protected]>
On Tue, 16 Apr 2024 17:53:09 +0200, Alexandre Mergnat wrote:
> Document the display Gamma on MT8365, which is compatible
> with that of the MT8183.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring (Arm) <[email protected]>
On Tue, 16 Apr 2024 17:53:11 +0200, Alexandre Mergnat wrote:
> Document the display Data Path Read DMA on MT8365, which is compatible
> with that of the MT8183.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring (Arm) <[email protected]>
On Tue, 16 Apr 2024 17:53:13 +0200, Alexandre Mergnat wrote:
> Add a compatible string for MediaTek Genio 350 MT8365's display PWM
> block: this is the same as MT8183.
>
> Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
> Acked-by: Uwe Kleine-K?nig <[email protected]>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring (Arm) <[email protected]>
Hi Uwe
On 17/04/2024 10:06, Uwe Kleine-König wrote:
> Hello,
>
> On Tue, Apr 16, 2024 at 05:53:13PM +0200, Alexandre Mergnat wrote:
>> Add a compatible string for MediaTek Genio 350 MT8365's display PWM
>> block: this is the same as MT8183.
>>
>> Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
>> Acked-by: Uwe Kleine-König <[email protected]>
>> Signed-off-by: Alexandre Mergnat <[email protected]>
>
> I already asked in reply to v1 what the merge plan is here. There are
> changes in my pwm tree to the mediatek,pwm-disp binding already. I don't
> think they conflict with this patch, but maybe it's still easier to take
> this via pwm?!
Sorry, I though the merge strategy wasn't addressed to me because I'm not a maintainer.
It's fine for me to merge it in the PWM tree.
IMO, this change [1] shouldn't conflict with this patch.
Can you add the "Acked-by: Rob Herring (Arm) <[email protected]>" please if you merge this version ?
Thanks for the review and help.
[1]:
https://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux.git/commit/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml?h=pwm/for-next&id=fb7c3d8ba039df877886fd457538d8b24ca9c84b
--
Regards,
Alexandre
On 17/04/2024 12:27, AngeloGioacchino Del Regno wrote:
>
>> + irq_ite_pins {
>
> Did you run dtbs_check?!? :-)
Yes without error, here my command:
dt-validate -s Documentation/devicetree/bindings arch/arm64/boot/dts/mediatek/mt8365-evk.dtb
Also I've done a "make dtbs_check" just to be sure, nothing wrong on mt8365-evk.dtb.
For you, what is the issue please ?
--
Regards,
Alexandre
Hello Alexandre,
On Thu, Apr 18, 2024 at 11:46:11AM +0200, Alexandre Mergnat wrote:
> On 17/04/2024 10:06, Uwe Kleine-K?nig wrote:
> > On Tue, Apr 16, 2024 at 05:53:13PM +0200, Alexandre Mergnat wrote:
> > > Add a compatible string for MediaTek Genio 350 MT8365's display PWM
> > > block: this is the same as MT8183.
> > >
> > > Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
> > > Acked-by: Uwe Kleine-K?nig <[email protected]>
> > > Signed-off-by: Alexandre Mergnat <[email protected]>
> >
> > I already asked in reply to v1 what the merge plan is here. There are
> > changes in my pwm tree to the mediatek,pwm-disp binding already. I don't
> > think they conflict with this patch, but maybe it's still easier to take
> > this via pwm?!
>
> Sorry, I though the merge strategy wasn't addressed to me because I'm not a maintainer.
Well, you're the canonical person who has an interest to get this series
in, so you can at least have and express an idea. In my experience it's
good to be proactive and suggest a merge plan. Maintainers are triggered
more to reply by a presented plan they don't agree with than with
suggesting a plan themselves. And this way at least there is less
surprise for you as submitter.
> It's fine for me to merge it in the PWM tree.
> IMO, this change [1] shouldn't conflict with this patch.
FTR: [1] is in Linus's tree already now.
> Can you add the "Acked-by: Rob Herring (Arm) <[email protected]>" please if you merge this version ?
I picked the one from your v3 series now where you included Rob's Ack. I
was a bit grumpy because I only spotted your reply here afterwards.
(Everything fine now on my side now.)
Best regards
Uwe
> [1]: https://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux.git/commit/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml?h=pwm/for-next&id=fb7c3d8ba039df877886fd457538d8b24ca9c84b
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | https://www.pengutronix.de/ |