Add the Zba address bit manipulation extension and Zbs single bit
instructions extension into those the kernel is aware of and maintains
in its riscv_isa bitmap.
Signed-off-by: Evan Green <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Palmer Dabbelt <[email protected]>
---
Changes in v2:
- Add Zbs as well
arch/riscv/include/asm/hwcap.h | 2 ++
arch/riscv/kernel/cpu.c | 2 ++
arch/riscv/kernel/cpufeature.c | 2 ++
3 files changed, 6 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index e0c40a4c63d5..6b2e8ff4638c 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -46,6 +46,8 @@
#define RISCV_ISA_EXT_ZICBOZ 34
#define RISCV_ISA_EXT_SMAIA 35
#define RISCV_ISA_EXT_SSAIA 36
+#define RISCV_ISA_EXT_ZBA 37
+#define RISCV_ISA_EXT_ZBS 38
#define RISCV_ISA_EXT_MAX 64
#define RISCV_ISA_EXT_NAME_LEN_MAX 32
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index c96aa56cf1c7..bd294364390d 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -184,7 +184,9 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
+ __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
+ __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index b1d6b7e4b829..a1954c83638f 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -236,7 +236,9 @@ void __init riscv_fill_hwcap(void)
SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
+ SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA);
SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
+ SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS);
SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);
SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
--
2.25.1
On Tue, May 09, 2023 at 11:25:01AM -0700, Evan Green wrote:
> Add the Zba address bit manipulation extension and Zbs single bit
> instructions extension into those the kernel is aware of and maintains
> in its riscv_isa bitmap.
>
> Signed-off-by: Evan Green <[email protected]>
> Reviewed-by: Andrew Jones <[email protected]>
> Reviewed-by: Palmer Dabbelt <[email protected]>
Given you added the lads, rather than ignoring them due to the Zbs
change, I think you forgot my R-b from v1?
Reviewed-by: Conor Dooley <[email protected]>
Cheers,
Conor.
>
> ---
>
> Changes in v2:
> - Add Zbs as well
>
> arch/riscv/include/asm/hwcap.h | 2 ++
> arch/riscv/kernel/cpu.c | 2 ++
> arch/riscv/kernel/cpufeature.c | 2 ++
> 3 files changed, 6 insertions(+)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index e0c40a4c63d5..6b2e8ff4638c 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -46,6 +46,8 @@
> #define RISCV_ISA_EXT_ZICBOZ 34
> #define RISCV_ISA_EXT_SMAIA 35
> #define RISCV_ISA_EXT_SSAIA 36
> +#define RISCV_ISA_EXT_ZBA 37
> +#define RISCV_ISA_EXT_ZBS 38
>
> #define RISCV_ISA_EXT_MAX 64
Heh, gonna start getting tight on bits here soonish :)
> #define RISCV_ISA_EXT_NAME_LEN_MAX 32
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index c96aa56cf1c7..bd294364390d 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -184,7 +184,9 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
> __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
> __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
> __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
> + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
> __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
> + __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
> __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
> __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index b1d6b7e4b829..a1954c83638f 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -236,7 +236,9 @@ void __init riscv_fill_hwcap(void)
> SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
> SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
> SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
> + SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA);
> SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
> + SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS);
> SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
> SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);
> SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
> --
> 2.25.1
>
On Tue, May 9, 2023 at 11:29 AM Conor Dooley <[email protected]> wrote:
>
> On Tue, May 09, 2023 at 11:25:01AM -0700, Evan Green wrote:
> > Add the Zba address bit manipulation extension and Zbs single bit
> > instructions extension into those the kernel is aware of and maintains
> > in its riscv_isa bitmap.
> >
> > Signed-off-by: Evan Green <[email protected]>
> > Reviewed-by: Andrew Jones <[email protected]>
> > Reviewed-by: Palmer Dabbelt <[email protected]>
>
> Given you added the lads, rather than ignoring them due to the Zbs
> change, I think you forgot my R-b from v1?
> Reviewed-by: Conor Dooley <[email protected]>
Whoops, yes I did. Sorry about that, and thanks for the review!
>
> Cheers,
> Conor.
>
> >
> > ---
> >
> > Changes in v2:
> > - Add Zbs as well
> >
> > arch/riscv/include/asm/hwcap.h | 2 ++
> > arch/riscv/kernel/cpu.c | 2 ++
> > arch/riscv/kernel/cpufeature.c | 2 ++
> > 3 files changed, 6 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index e0c40a4c63d5..6b2e8ff4638c 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -46,6 +46,8 @@
> > #define RISCV_ISA_EXT_ZICBOZ 34
> > #define RISCV_ISA_EXT_SMAIA 35
> > #define RISCV_ISA_EXT_SSAIA 36
> > +#define RISCV_ISA_EXT_ZBA 37
> > +#define RISCV_ISA_EXT_ZBS 38
> >
> > #define RISCV_ISA_EXT_MAX 64
>
> Heh, gonna start getting tight on bits here soonish :)
Yeah they're flying in, I had to update mine since SMAIA swooshed in.
-Evan
Am Dienstag, 9. Mai 2023, 20:25:01 CEST schrieb Evan Green:
> Add the Zba address bit manipulation extension and Zbs single bit
> instructions extension into those the kernel is aware of and maintains
> in its riscv_isa bitmap.
>
> Signed-off-by: Evan Green <[email protected]>
> Reviewed-by: Andrew Jones <[email protected]>
> Reviewed-by: Palmer Dabbelt <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
On Wed, 10 May 2023 07:45:50 PDT (-0700), [email protected] wrote:
> Am Dienstag, 9. Mai 2023, 20:25:01 CEST schrieb Evan Green:
>> Add the Zba address bit manipulation extension and Zbs single bit
>> instructions extension into those the kernel is aware of and maintains
>> in its riscv_isa bitmap.
>>
>> Signed-off-by: Evan Green <[email protected]>
>> Reviewed-by: Andrew Jones <[email protected]>
>> Reviewed-by: Palmer Dabbelt <[email protected]>
>
> Reviewed-by: Heiko Stuebner <[email protected]>
Just FYI: b4 is giving me this
NOTE: some trailers ignored due to from/email mismatches:
! Trailer: Reviewed-by: Heiko Stuebner <[email protected]>
Msg From: Heiko Stübner <[email protected]>
NOTE: Rerun with -S to apply them anyway
I added it. No big deal on my end, I also send email from random addresses
that are different from my trailers. It's just the first time I remember b4
saying something.