The node names should have generic name, so use "timings" for LPDDR3
timings. This will also be required by dtschema.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 24c428b84192..2f65dcf6ba73 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -358,7 +358,7 @@ samsung_K3QF2F20DB: lpddr3 {
tCKESR-min-tck = <2>;
tMRD-min-tck = <5>;
- timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
+ timings_samsung_K3QF2F20DB_800mhz: timings@800000000 {
compatible = "jedec,lpddr3-timings";
/* workaround: 'reg' shows max-freq */
reg = <800000000>;
--
2.32.0
The memory manufacturer should be described in vendor part of
compatible, so there is no need to duplicate it in separate property.
Similarly is done in LPDDR2 bindings.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/memory-controllers/ddr/jedec,lpddr3.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
index 0c8353c11767..138c57d8a375 100644
--- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
@@ -40,7 +40,9 @@ properties:
manufacturer-id:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
- Manufacturer ID value read from Mode Register 5.
+ Manufacturer ID value read from Mode Register 5. The property is
+ deprecated, manufacturer should be derived from the compatible.
+ deprecated: true
revision-id:
$ref: /schemas/types.yaml#/definitions/uint32-array
--
2.32.0
According to JEDEC Standard No. 209-3 (table 3.4.1 "Mode Register
Assignment and Definition in LPDDR3 SDRAM"), the LPDDR3 supports only
16- and 32-bit IO width. Drop the unsupported others.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/memory-controllers/ddr/jedec,lpddr3.yaml | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
index c8577186324a..0c8353c11767 100644
--- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
@@ -34,10 +34,8 @@ properties:
description: |
IO bus width in bits of SDRAM chip.
enum:
- - 64
- 32
- 16
- - 8
manufacturer-id:
$ref: /schemas/types.yaml#/definitions/uint32
--
2.32.0
Convert the LPDDR2 memory timings bindings to DT schema format.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../ddr/jedec,lpddr2-timings.yaml | 135 ++++++++++++++++++
.../memory-controllers/ddr/jedec,lpddr2.yaml | 6 +-
.../memory-controllers/ddr/lpddr2-timings.txt | 52 -------
3 files changed, 137 insertions(+), 56 deletions(-)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml
delete mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt
diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml
new file mode 100644
index 000000000000..7cc3021decfe
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
+
+maintainers:
+ - Krzysztof Kozlowski <[email protected]>
+
+properties:
+ compatible:
+ const: jedec,lpddr2-timings
+
+ max-freq:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Maximum DDR clock frequency for the speed-bin, in Hz.
+
+ min-freq:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Minimum DDR clock frequency for the speed-bin, in Hz.
+
+ tCKESR:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ CKE minimum pulse width during SELF REFRESH (low pulse width during
+ SELF REFRESH) in pico seconds.
+
+ tDQSCK-max:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ DQS output data access time from CK_t/CK_c in pico seconds.
+
+ tDQSCK-max-derated:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ DQS output data access time from CK_t/CK_c, temperature de-rated, in pico
+ seconds.
+
+ tFAW:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Four-bank activate window in pico seconds.
+
+ tRAS-max-ns:
+ description: |
+ Row active time in nano seconds.
+
+ tRAS-min:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Row active time in pico seconds.
+
+ tRCD:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ RAS-to-CAS delay in pico seconds.
+
+ tRPab:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Row precharge time (all banks) in pico seconds.
+
+ tRRD:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Active bank A to active bank B in pico seconds.
+
+ tRTP:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Internal READ to PRECHARGE command delay in pico seconds.
+
+ tWR:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ WRITE recovery time in pico seconds.
+
+ tWTR:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Internal WRITE-to-READ command delay in pico seconds.
+
+ tXP:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Exit power-down to next valid command delay in pico seconds.
+
+ tZQCL:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ SELF REFRESH exit to next valid command delay in pico seconds.
+
+ tZQCS:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ SELF REFRESH exit to next valid command delay in pico seconds.
+
+ tZQinit:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ SELF REFRESH exit to next valid command delay in pico seconds.
+
+required:
+ - compatible
+ - min-freq
+ - max-freq
+
+additionalProperties: false
+
+examples:
+ - |
+ timings {
+ compatible = "jedec,lpddr2-timings";
+ min-freq = <10000000>;
+ max-freq = <400000000>;
+ tCKESR = <15000>;
+ tDQSCK-max = <5500>;
+ tFAW = <50000>;
+ tRAS-max-ns = <70000>;
+ tRAS-min = <42000>;
+ tRPab = <21000>;
+ tRCD = <18000>;
+ tRRD = <10000>;
+ tRTP = <7500>;
+ tWR = <15000>;
+ tWTR = <7500>;
+ tXP = <7500>;
+ tZQCL = <360000>;
+ tZQCS = <90000>;
+ tZQinit = <1000000>;
+ };
diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml
index 25ed0266f6dd..2d8a701e2a05 100644
--- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml
@@ -142,14 +142,12 @@ properties:
patternProperties:
"^lpddr2-timings":
- type: object
+ $ref: jedec,lpddr2-timings.yaml
description: |
The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
"lpddr2-timings" provides AC timing parameters of the device for
a given speed-bin. The user may provide the timings for as many
- speed-bins as is required. Please see Documentation/devicetree/
- bindings/memory-controllers/ddr/lpddr2-timings.txt for more information
- on "lpddr2-timings".
+ speed-bins as is required.
required:
- compatible
diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt
deleted file mode 100644
index 9ceb19e0c7fd..000000000000
--- a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
-
-Required properties:
-- compatible : Should be "jedec,lpddr2-timings"
-- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
-- max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
-
-Optional properties:
-
-The following properties represent AC timing parameters from the memory
-data-sheet of the device for a given speed-bin. All these properties are
-of type <u32> and the default unit is ps (pico seconds). Parameters with
-a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
-- tRCD
-- tWR
-- tRAS-min
-- tRRD
-- tWTR
-- tXP
-- tRTP
-- tDQSCK-max
-- tFAW
-- tZQCS
-- tZQinit
-- tRPab
-- tZQCL
-- tCKESR
-- tRAS-max-ns
-- tDQSCK-max-derated
-
-Example:
-
-timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
- compatible = "jedec,lpddr2-timings";
- min-freq = <10000000>;
- max-freq = <400000000>;
- tRPab = <21000>;
- tRCD = <18000>;
- tWR = <15000>;
- tRAS-min = <42000>;
- tRRD = <10000>;
- tWTR = <7500>;
- tXP = <7500>;
- tRTP = <7500>;
- tCKESR = <15000>;
- tDQSCK-max = <5500>;
- tFAW = <50000>;
- tZQCS = <90000>;
- tZQCL = <360000>;
- tZQinit = <1000000>;
- tRAS-max-ns = <70000>;
-};
--
2.32.0
Convert the LPDDR3 memory timings bindings to DT schema format.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../ddr/jedec,lpddr3-timings.yaml | 153 ++++++++++++++++++
.../memory-controllers/ddr/jedec,lpddr3.yaml | 5 +-
.../memory-controllers/ddr/lpddr3-timings.txt | 58 -------
3 files changed, 155 insertions(+), 61 deletions(-)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml
delete mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt
diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml
new file mode 100644
index 000000000000..98bc219e8a25
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml
@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
+
+maintainers:
+ - Krzysztof Kozlowski <[email protected]>
+
+properties:
+ compatible:
+ const: jedec,lpddr3-timings
+
+ reg:
+ maxItems: 1
+ description: |
+ Maximum DDR clock frequency for the speed-bin, in Hz.
+
+ min-freq:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Minimum DDR clock frequency for the speed-bin, in Hz.
+
+ tCKE:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ CKE minimum pulse width (HIGH and LOW pulse width) in pico seconds.
+
+ tCKESR:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ CKE minimum pulse width during SELF REFRESH (low pulse width during
+ SELF REFRESH) in pico seconds.
+
+ tFAW:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Four-bank activate window in pico seconds.
+
+ tMRD:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Mode register set command delay in pico seconds.
+
+ tR2R-C2C:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Additional READ-to-READ delay in chip-to-chip cases in pico seconds.
+
+ tRAS:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Row active time in pico seconds.
+
+ tRC:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ ACTIVATE-to-ACTIVATE command period in pico seconds.
+
+ tRCD:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ RAS-to-CAS delay in pico seconds.
+
+ tRFC:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Refresh Cycle time in pico seconds.
+
+ tRPab:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Row precharge time (all banks) in pico seconds.
+
+ tRPpb:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Row precharge time (single banks) in pico seconds.
+
+ tRRD:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Active bank A to active bank B in pico seconds.
+
+ tRTP:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Internal READ to PRECHARGE command delay in pico seconds.
+
+ tW2W-C2C:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Additional WRITE-to-WRITE delay in chip-to-chip cases in pico seconds.
+
+ tWR:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ WRITE recovery time in pico seconds.
+
+ tWTR:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Internal WRITE-to-READ command delay in pico seconds.
+
+ tXP:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Exit power-down to next valid command delay in pico seconds.
+
+ tXSR:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ SELF REFRESH exit to next valid command delay in pico seconds.
+
+required:
+ - compatible
+ - min-freq
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ lpddr3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ timings@800000000 {
+ compatible = "jedec,lpddr3-timings";
+ reg = <800000000>;
+ min-freq = <100000000>;
+ tCKE = <3750>;
+ tCKESR = <3750>;
+ tFAW = <25000>;
+ tMRD = <7000>;
+ tR2R-C2C = <0>;
+ tRAS = <23000>;
+ tRC = <33750>;
+ tRCD = <10000>;
+ tRFC = <65000>;
+ tRPab = <12000>;
+ tRPpb = <12000>;
+ tRRD = <6000>;
+ tRTP = <3750>;
+ tW2W-C2C = <0>;
+ tWR = <7500>;
+ tWTR = <3750>;
+ tXP = <3750>;
+ tXSR = <70000>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
index 138c57d8a375..3bcba15098ea 100644
--- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
@@ -192,13 +192,12 @@ properties:
patternProperties:
"^timings@[0-9a-f]+$":
- type: object
+ $ref: jedec,lpddr3-timings.yaml
description: |
The lpddr3 node may have one or more child nodes with timings.
Each timing node provides AC timing parameters of the device for a given
speed-bin. The user may provide the timings for as many speed-bins as is
- required. For more information please see::
- Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt
+ required.
required:
- compatible
diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt
deleted file mode 100644
index 84705e50a3fd..000000000000
--- a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-* AC timing parameters of LPDDR3 memories for a given speed-bin.
-
-The structures are based on LPDDR2 and extended where needed.
-
-Required properties:
-- compatible : Should be "jedec,lpddr3-timings"
-- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
-- reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
-
-Optional properties:
-
-The following properties represent AC timing parameters from the memory
-data-sheet of the device for a given speed-bin. All these properties are
-of type <u32> and the default unit is ps (pico seconds).
-- tRFC
-- tRRD
-- tRPab
-- tRPpb
-- tRCD
-- tRC
-- tRAS
-- tWTR
-- tWR
-- tRTP
-- tW2W-C2C
-- tR2R-C2C
-- tFAW
-- tXSR
-- tXP
-- tCKE
-- tCKESR
-- tMRD
-
-Example:
-
-timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
- compatible = "jedec,lpddr3-timings";
- reg = <800000000>; /* workaround: it shows max-freq */
- min-freq = <100000000>;
- tRFC = <65000>;
- tRRD = <6000>;
- tRPab = <12000>;
- tRPpb = <12000>;
- tRCD = <10000>;
- tRC = <33750>;
- tRAS = <23000>;
- tWTR = <3750>;
- tWR = <7500>;
- tRTP = <3750>;
- tW2W-C2C = <0>;
- tR2R-C2C = <0>;
- tFAW = <25000>;
- tXSR = <70000>;
- tXP = <3750>;
- tCKE = <3750>;
- tCKESR = <3750>;
- tMRD = <7000>;
-};
--
2.32.0
Convert the LPDDR3 memory bindings to DT schema format.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../memory-controllers/ddr/jedec,lpddr3.yaml | 266 ++++++++++++++++++
.../memory-controllers/ddr/lpddr3.txt | 107 -------
2 files changed, 266 insertions(+), 107 deletions(-)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
delete mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt
diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
new file mode 100644
index 000000000000..c8577186324a
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
@@ -0,0 +1,266 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
+
+maintainers:
+ - Krzysztof Kozlowski <[email protected]>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - samsung,K3QF2F20DB
+ - const: jedec,lpddr3
+
+ '#address-cells':
+ const: 1
+
+ density:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Density in megabits of SDRAM chip.
+ enum:
+ - 4096
+ - 8192
+ - 16384
+ - 32768
+
+ io-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ IO bus width in bits of SDRAM chip.
+ enum:
+ - 64
+ - 32
+ - 16
+ - 8
+
+ manufacturer-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Manufacturer ID value read from Mode Register 5.
+
+ revision-id:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 2
+ maxItems: 2
+ items:
+ maximum: 255
+ description: |
+ Revision value of SDRAM chip read from Mode Registers 6 and 7.
+
+ '#size-cells':
+ const: 0
+
+ tCKE-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 15
+ description: |
+ CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
+ of clock cycles.
+
+ tCKESR-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 15
+ description: |
+ CKE minimum pulse width during SELF REFRESH (low pulse width during
+ SELF REFRESH) in terms of number of clock cycles.
+
+ tDQSCK-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 15
+ description: |
+ DQS output data access time from CK_t/CK_c in terms of number of clock
+ cycles.
+
+ tFAW-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 63
+ description: |
+ Four-bank activate window in terms of number of clock cycles.
+
+ tMRD-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 15
+ description: |
+ Mode register set command delay in terms of number of clock cycles.
+
+ tR2R-C2C-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ description: |
+ Additional READ-to-READ delay in chip-to-chip cases in terms of number
+ of clock cycles.
+
+ tRAS-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 63
+ description: |
+ Row active time in terms of number of clock cycles.
+
+ tRC-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 63
+ description: |
+ ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
+
+ tRCD-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 15
+ description: |
+ RAS-to-CAS delay in terms of number of clock cycles.
+
+ tRFC-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+ description: |
+ Refresh Cycle time in terms of number of clock cycles.
+
+ tRL-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 15
+ description: |
+ READ data latency in terms of number of clock cycles.
+
+ tRPab-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 15
+ description: |
+ Row precharge time (all banks) in terms of number of clock cycles.
+
+ tRPpb-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 15
+ description: |
+ Row precharge time (single banks) in terms of number of clock cycles.
+
+ tRRD-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 15
+ description: |
+ Active bank A to active bank B in terms of number of clock cycles.
+
+ tRTP-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 15
+ description: |
+ Internal READ to PRECHARGE command delay in terms of number of clock
+ cycles.
+
+ tW2W-C2C-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ description: |
+ Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number
+ of clock cycles.
+
+ tWL-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 15
+ description: |
+ WRITE data latency in terms of number of clock cycles.
+
+ tWR-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 15
+ description: |
+ WRITE recovery time in terms of number of clock cycles.
+
+ tWTR-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 15
+ description: |
+ Internal WRITE-to-READ command delay in terms of number of clock cycles.
+
+ tXP-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+ description: |
+ Exit power-down to next valid command delay in terms of number of clock
+ cycles.
+
+ tXSR-min-tck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 1023
+ description: |
+ SELF REFRESH exit to next valid command delay in terms of number of clock
+ cycles.
+
+patternProperties:
+ "^timings@[0-9a-f]+$":
+ type: object
+ description: |
+ The lpddr3 node may have one or more child nodes with timings.
+ Each timing node provides AC timing parameters of the device for a given
+ speed-bin. The user may provide the timings for as many speed-bins as is
+ required. For more information please see::
+ Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt
+
+required:
+ - compatible
+ - '#address-cells'
+ - density
+ - io-width
+ - '#size-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ lpddr3 {
+ compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
+ density = <16384>;
+ io-width = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tCKE-min-tck = <2>;
+ tCKESR-min-tck = <2>;
+ tDQSCK-min-tck = <5>;
+ tFAW-min-tck = <5>;
+ tMRD-min-tck = <5>;
+ tR2R-C2C-min-tck = <0>;
+ tRAS-min-tck = <5>;
+ tRC-min-tck = <6>;
+ tRCD-min-tck = <3>;
+ tRFC-min-tck = <17>;
+ tRL-min-tck = <14>;
+ tRPab-min-tck = <2>;
+ tRPpb-min-tck = <2>;
+ tRRD-min-tck = <2>;
+ tRTP-min-tck = <2>;
+ tW2W-C2C-min-tck = <0>;
+ tWL-min-tck = <8>;
+ tWR-min-tck = <7>;
+ tWTR-min-tck = <2>;
+ tXP-min-tck = <2>;
+ tXSR-min-tck = <12>;
+
+ timings@800000000 {
+ compatible = "jedec,lpddr3-timings";
+ reg = <800000000>;
+ min-freq = <100000000>;
+ tCKE = <3750>;
+ tCKESR = <3750>;
+ tFAW = <25000>;
+ tMRD = <7000>;
+ tR2R-C2C = <0>;
+ tRAS = <23000>;
+ tRC = <33750>;
+ tRCD = <10000>;
+ tRFC = <65000>;
+ tRPab = <12000>;
+ tRPpb = <12000>;
+ tRRD = <6000>;
+ tRTP = <3750>;
+ tW2W-C2C = <0>;
+ tWR = <7500>;
+ tWTR = <3750>;
+ tXP = <3750>;
+ tXSR = <70000>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt
deleted file mode 100644
index 031af5fb0379..000000000000
--- a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt
+++ /dev/null
@@ -1,107 +0,0 @@
-* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C
-
-Required properties:
-- compatible : Should be "<vendor>,<type>", and generic value "jedec,lpddr3".
- Example "<vendor>,<type>" values:
- "samsung,K3QF2F20DB"
-
-- density : <u32> representing density in Mb (Mega bits)
-- io-width : <u32> representing bus width. Possible values are 8, 16, 32, 64
-- #address-cells: Must be set to 1
-- #size-cells: Must be set to 0
-
-Optional properties:
-
-- manufacturer-id : <u32> Manufacturer ID value read from Mode Register 5
-- revision-id : <u32 u32> Revision IDs read from Mode Registers 6 and 7
-
-The following optional properties represent the minimum value of some AC
-timing parameters of the DDR device in terms of number of clock cycles.
-These values shall be obtained from the device data-sheet.
-- tRFC-min-tck
-- tRRD-min-tck
-- tRPab-min-tck
-- tRPpb-min-tck
-- tRCD-min-tck
-- tRC-min-tck
-- tRAS-min-tck
-- tWTR-min-tck
-- tWR-min-tck
-- tRTP-min-tck
-- tW2W-C2C-min-tck
-- tR2R-C2C-min-tck
-- tWL-min-tck
-- tDQSCK-min-tck
-- tRL-min-tck
-- tFAW-min-tck
-- tXSR-min-tck
-- tXP-min-tck
-- tCKE-min-tck
-- tCKESR-min-tck
-- tMRD-min-tck
-
-Child nodes:
-- The lpddr3 node may have one or more child nodes of type "lpddr3-timings".
- "lpddr3-timings" provides AC timing parameters of the device for
- a given speed-bin. Please see
- Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt
- for more information on "lpddr3-timings"
-
-Example:
-
-samsung_K3QF2F20DB: lpddr3 {
- compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
- density = <16384>;
- io-width = <32>;
- manufacturer-id = <1>;
- revision-id = <123 234>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- tRFC-min-tck = <17>;
- tRRD-min-tck = <2>;
- tRPab-min-tck = <2>;
- tRPpb-min-tck = <2>;
- tRCD-min-tck = <3>;
- tRC-min-tck = <6>;
- tRAS-min-tck = <5>;
- tWTR-min-tck = <2>;
- tWR-min-tck = <7>;
- tRTP-min-tck = <2>;
- tW2W-C2C-min-tck = <0>;
- tR2R-C2C-min-tck = <0>;
- tWL-min-tck = <8>;
- tDQSCK-min-tck = <5>;
- tRL-min-tck = <14>;
- tFAW-min-tck = <5>;
- tXSR-min-tck = <12>;
- tXP-min-tck = <2>;
- tCKE-min-tck = <2>;
- tCKESR-min-tck = <2>;
- tMRD-min-tck = <5>;
-
- timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
- compatible = "jedec,lpddr3-timings";
- /* workaround: 'reg' shows max-freq */
- reg = <800000000>;
- min-freq = <100000000>;
- tRFC = <65000>;
- tRRD = <6000>;
- tRPab = <12000>;
- tRPpb = <12000>;
- tRCD = <10000>;
- tRC = <33750>;
- tRAS = <23000>;
- tWTR = <3750>;
- tWR = <7500>;
- tRTP = <3750>;
- tW2W-C2C = <0>;
- tR2R-C2C = <0>;
- tFAW = <25000>;
- tXSR = <70000>;
- tXP = <3750>;
- tCKE = <3750>;
- tCKESR = <3750>;
- tMRD = <7000>;
- };
-}
--
2.32.0
On Tue, 1 Feb 2022 12:47:44 +0100, Krzysztof Kozlowski wrote:
> The node names should have generic name, so use "timings" for LPDDR3
> timings. This will also be required by dtschema.
>
>
Applied, thanks!
[1/6] arm64: dts: exynos: use generic node name for LPDDR3 timings
commit: 931dac3d3442bb1ea01be9cbdc53310272b68f77
Best regards,
--
Krzysztof Kozlowski <[email protected]>
On 04/02/2022 20:48, Dmitry Osipenko wrote:
> 01.02.2022 14:47, Krzysztof Kozlowski пишет:
>> + tZQCL:
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + description: |
>> + SELF REFRESH exit to next valid command delay in pico seconds.
>> +
>> + tZQCS:
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + description: |
>> + SELF REFRESH exit to next valid command delay in pico seconds.
>> +
>> + tZQinit:
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + description: |
>> + SELF REFRESH exit to next valid command delay in pico seconds.
>
> Hm.. these look incorrect.
>
> tZQCL is Long Calibration Time
>
> tZQCS is Short Calibration Time
>
> tZQinit is Initialization Calibration Time
>
> No?
Yes, thanks for spotting these. Copy-paste error.
Best regards,
Krzysztof
01.02.2022 14:47, Krzysztof Kozlowski пишет:
> + tZQCL:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + SELF REFRESH exit to next valid command delay in pico seconds.
> +
> + tZQCS:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + SELF REFRESH exit to next valid command delay in pico seconds.
> +
> + tZQinit:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + SELF REFRESH exit to next valid command delay in pico seconds.
Hm.. these look incorrect.
tZQCL is Long Calibration Time
tZQCS is Short Calibration Time
tZQinit is Initialization Calibration Time
No?