This series adds support for:
- DisplayPort for J784S4-EVM
- Displayport and HDMI for AM69-SK platform
Changelog v7->v8:
- rebase on tag next-20230731
- add AM69 display support
- fix commit heading for patch [2/5]
Changelog v6->v7:
- change compatible for scm_conf to 'simple-bus'
- drop main_cpsw node due to driver dependency on [2]
Changelog v5->v6:
- Change header file according to [1].
- Add idle-state property in serdes_ln_ctrl node.
- Fix dtbs_check warning due to clock-frequency property in serdes_refclk
node by disabling the node in main.dtsi and enabling it in board file
when the clock-frequency node is actually added.
Changelog v4->v5:
- rebased the patches on linux-next tip.
Changelog v3->v4:
- add reg property to serdes_ln_ctrl and fix the node name again to
get rid of dtbs_check error.
- reorder reg, reg-names and ranges property for main_cpsw1.
- correct the order for clocks in serdes_wiz nodes to fix dtbs_check
warnings.
- fix indentation in reg, reg-names and clock property for dss node.
- add comments for the reg type in dss registers.
Changelog v3->v2:
- fix dtc warnings for 'scm_conf' and 'serdes_ln_ctrl' nodes
(Checked all the changes of the series with W=12 option during build)
- added clock-frequency for serdes_refclk along with other EVM changes
This refclk is being used by all the instances of serdes_wiz which
are disabled by default. So configuring refclk when the serdes nodes
are used for the first time is okay.
Changelog v1->v2:
- Moved J784S4 EVM changes together to the last patch
(Suggested by Andrew)
v7 patch link:
<https://lore.kernel.org/all/[email protected]/>
[1]: <https://lore.kernel.org/all/[email protected]/>
[2]: <https://lore.kernel.org/all/[email protected]/>
Dasnavis Sabiya (1):
arm64: dts: ti: k3-am69-sk: Add DP and HDMI support
Rahul T R (2):
arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node
arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0
Siddharth Vadapalli (2):
arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane
mux
arm64: dts: ti: k3-j784s4-main: Add WIZ and SERDES PHY nodes
arch/arm64/boot/dts/ti/k3-am69-sk.dts | 237 +++++++++++++++++
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 117 +++++++++
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 285 +++++++++++++++++++++
3 files changed, 639 insertions(+)
--
2.25.1
From: Rahul T R <[email protected]>
Enable display for J784S4 EVM.
Add assigned clocks for DSS, DT node for DisplayPort PHY and pinmux for
DP HPD. Add the clock frequency for serdes_refclk.
Add the endpoint nodes to describe connection from:
DSS => MHDP => DisplayPort connector.
Also add the GPIO expander-4 node and pinmux for main_i2c4 which is
required for controlling DP power. Set status for all required nodes
for DP-0 as "okay".
Signed-off-by: Rahul T R <[email protected]>
[[email protected]: move all the changes together to enable DP-0 in EVM]
Signed-off-by: Jayesh Choudhary <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 117 +++++++++++++++++++++++
1 file changed, 117 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 7ad152a1b90f..1145a7f046e2 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -249,6 +249,28 @@ vdd_sd_dv: regulator-TLV71033 {
states = <1800000 0x0>,
<3300000 0x1>;
};
+
+ dp0_pwr_3v3: regulator-dp0-prw {
+ compatible = "regulator-fixed";
+ regulator-name = "dp0-pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&exp4 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ dp0: dp0-connector {
+ compatible = "dp-connector";
+ label = "DP0";
+ type = "full-size";
+ dp-pwr-supply = <&dp0_pwr_3v3>;
+
+ port {
+ dp0_connector_in: endpoint {
+ remote-endpoint = <&dp0_out>;
+ };
+ };
+ };
};
&main_pmx0 {
@@ -286,6 +308,19 @@ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
>;
};
+
+ dp0_pins_default: dp0-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */
+ >;
+ };
+
+ main_i2c4_pins_default: main-i2c4-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */
+ J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */
+ >;
+ };
};
&wkup_pmx2 {
@@ -827,3 +862,85 @@ adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
+
+&serdes_refclk {
+ status = "okay";
+ clock-frequency = <100000000>;
+};
+
+&dss {
+ status = "okay";
+ assigned-clocks = <&k3_clks 218 2>,
+ <&k3_clks 218 5>,
+ <&k3_clks 218 14>,
+ <&k3_clks 218 18>;
+ assigned-clock-parents = <&k3_clks 218 3>,
+ <&k3_clks 218 7>,
+ <&k3_clks 218 16>,
+ <&k3_clks 218 22>;
+};
+
+&serdes_wiz4 {
+ status = "okay";
+};
+
+&serdes4 {
+ status = "okay";
+ serdes4_dp_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <4>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_DP>;
+ resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
+ <&serdes_wiz4 3>, <&serdes_wiz4 4>;
+ };
+};
+
+&mhdp {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_pins_default>;
+ phys = <&serdes4_dp_link>;
+ phy-names = "dpphy";
+};
+
+&dss_ports {
+ port {
+ dpi0_out: endpoint {
+ remote-endpoint = <&dp0_in>;
+ };
+ };
+};
+
+&main_i2c4 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c4_pins_default>;
+ clock-frequency = <400000>;
+
+ exp4: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&dp0_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ dp0_out: endpoint {
+ remote-endpoint = <&dp0_connector_in>;
+ };
+ };
+};
--
2.25.1
From: Siddharth Vadapalli <[email protected]>
J784S4 SoC has 4 Serdes instances along with their respective WIZ
instances. Add device-tree nodes for them and disable them by default.
Signed-off-by: Siddharth Vadapalli <[email protected]>
[[email protected]: fix serdes_wiz clock order & disable serdes refclk]
Signed-off-by: Jayesh Choudhary <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 172 +++++++++++++++++++++
1 file changed, 172 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 8a816563706b..fbf5ab94d785 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -6,9 +6,19 @@
*/
#include <dt-bindings/mux/mux.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-ti.h>
#include "k3-serdes.h"
+/ {
+ serdes_refclk: serdes-refclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ status = "disabled";
+ };
+};
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -709,6 +719,168 @@ main_sdhci1: mmc@4fb0000 {
status = "disabled";
};
+ serdes_wiz0: wiz@5060000 {
+ compatible = "ti,j784s4-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+ assigned-clocks = <&k3_clks 404 6>;
+ assigned-clock-parents = <&k3_clks 404 10>;
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x5060000 0x00 0x5060000 0x10000>;
+
+ status = "disabled";
+
+ serdes0: serdes@5060000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05060000 0x010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 404 6>,
+ <&k3_clks 404 6>,
+ <&k3_clks 404 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
+ serdes_wiz1: wiz@5070000 {
+ compatible = "ti,j784s4-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+ assigned-clocks = <&k3_clks 405 6>;
+ assigned-clock-parents = <&k3_clks 405 10>;
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x05070000 0x00 0x05070000 0x10000>;
+
+ status = "disabled";
+
+ serdes1: serdes@5070000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05070000 0x010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz1 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 405 6>,
+ <&k3_clks 405 6>,
+ <&k3_clks 405 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
+ serdes_wiz2: wiz@5020000 {
+ compatible = "ti,j784s4-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+ assigned-clocks = <&k3_clks 406 6>;
+ assigned-clock-parents = <&k3_clks 406 10>;
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x05020000 0x00 0x05020000 0x10000>;
+
+ status = "disabled";
+
+ serdes2: serdes@5020000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05020000 0x010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz2 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz2 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 406 6>,
+ <&k3_clks 406 6>,
+ <&k3_clks 406 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
+ serdes_wiz4: wiz@5050000 {
+ compatible = "ti,j784s4-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+ assigned-clocks = <&k3_clks 407 6>;
+ assigned-clock-parents = <&k3_clks 407 10>;
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x05050000 0x00 0x05050000 0x10000>,
+ <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */
+
+ status = "disabled";
+
+ serdes4: serdes@5050000 {
+ /*
+ * Note: we also map DPTX PHY registers as the Torrent
+ * needs to manage those.
+ */
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05050000 0x010000>,
+ <0x0a030a00 0x40>; /* DPTX PHY */
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz4 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 407 6>,
+ <&k3_clks 407 6>,
+ <&k3_clks 407 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
main_navss: bus@30000000 {
compatible = "simple-bus";
#address-cells = <2>;
--
2.25.1
From: Siddharth Vadapalli <[email protected]>
The system controller node manages the CTRL_MMR0 region.
Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.
Signed-off-by: Siddharth Vadapalli <[email protected]>
[[email protected]: Fix serdes_ln_ctrl node]
Signed-off-by: Jayesh Choudhary <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 40 ++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 11f163e5cadf..8a816563706b 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -5,6 +5,10 @@
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/mux/mux.h>
+
+#include "k3-serdes.h"
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -26,6 +30,42 @@ l3cache-sram@200000 {
};
};
+ scm_conf: bus@100000 {
+ compatible = "simple-bus";
+ reg = <0x00 0x00100000 0x00 0x1c000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x00100000 0x1c000>;
+
+ serdes_ln_ctrl: mux-controller@4080 {
+ compatible = "mmio-mux";
+ reg = <0x00004080 0x30>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+ <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */
+ <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
+ <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */
+ <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
+ <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */
+ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,
+ <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+ <J784S4_SERDES0_LANE2_IP3_UNUSED>,
+ <J784S4_SERDES0_LANE3_USB>,
+ <J784S4_SERDES1_LANE0_PCIE0_LANE0>,
+ <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
+ <J784S4_SERDES1_LANE2_PCIE0_LANE2>,
+ <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
+ <J784S4_SERDES2_LANE0_IP2_UNUSED>,
+ <J784S4_SERDES2_LANE1_IP2_UNUSED>,
+ <J784S4_SERDES2_LANE2_QSGMII_LANE1>,
+ <J784S4_SERDES2_LANE3_QSGMII_LANE2>,
+ <J784S4_SERDES4_LANE0_EDP_LANE0>,
+ <J784S4_SERDES4_LANE1_EDP_LANE1>,
+ <J784S4_SERDES4_LANE2_EDP_LANE2>,
+ <J784S4_SERDES4_LANE3_EDP_LANE3>;
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
--
2.25.1
On 8/1/23 2:00 AM, Jayesh Choudhary wrote:
> From: Siddharth Vadapalli <[email protected]>
>
> The system controller node manages the CTRL_MMR0 region.
> Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.
>
> Signed-off-by: Siddharth Vadapalli <[email protected]>
> [[email protected]: Fix serdes_ln_ctrl node]
> Signed-off-by: Jayesh Choudhary <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 40 ++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> index 11f163e5cadf..8a816563706b 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -5,6 +5,10 @@
> * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> +#include <dt-bindings/mux/mux.h>
> +
> +#include "k3-serdes.h"
> +
> &cbass_main {
> msmc_ram: sram@70000000 {
> compatible = "mmio-sram";
> @@ -26,6 +30,42 @@ l3cache-sram@200000 {
> };
> };
>
> + scm_conf: bus@100000 {
> + compatible = "simple-bus";
> + reg = <0x00 0x00100000 0x00 0x1c000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x00 0x00 0x00100000 0x1c000>;
> +
> + serdes_ln_ctrl: mux-controller@4080 {
> + compatible = "mmio-mux";
The parent is not a syscon node, this should be "reg-mux".
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/mux/reg-mux.yaml#n19
Andrew
> + reg = <0x00004080 0x30>;
> + #mux-control-cells = <1>;
> + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
> + <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */
> + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
> + <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */
> + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
> + <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */
> + idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,
> + <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
> + <J784S4_SERDES0_LANE2_IP3_UNUSED>,
> + <J784S4_SERDES0_LANE3_USB>,
> + <J784S4_SERDES1_LANE0_PCIE0_LANE0>,
> + <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
> + <J784S4_SERDES1_LANE2_PCIE0_LANE2>,
> + <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
> + <J784S4_SERDES2_LANE0_IP2_UNUSED>,
> + <J784S4_SERDES2_LANE1_IP2_UNUSED>,
> + <J784S4_SERDES2_LANE2_QSGMII_LANE1>,
> + <J784S4_SERDES2_LANE3_QSGMII_LANE2>,
> + <J784S4_SERDES4_LANE0_EDP_LANE0>,
> + <J784S4_SERDES4_LANE1_EDP_LANE1>,
> + <J784S4_SERDES4_LANE2_EDP_LANE2>,
> + <J784S4_SERDES4_LANE3_EDP_LANE3>;
> + };
> + };
> +
> gic500: interrupt-controller@1800000 {
> compatible = "arm,gic-v3";
> #address-cells = <2>;
On 01/08/2023 10:00, Jayesh Choudhary wrote:
> From: Rahul T R <[email protected]>
>
> Enable display for J784S4 EVM.
>
> Add assigned clocks for DSS, DT node for DisplayPort PHY and pinmux for
> DP HPD. Add the clock frequency for serdes_refclk.
>
> Add the endpoint nodes to describe connection from:
> DSS => MHDP => DisplayPort connector.
>
> Also add the GPIO expander-4 node and pinmux for main_i2c4 which is
> required for controlling DP power. Set status for all required nodes
> for DP-0 as "okay".
>
> Signed-off-by: Rahul T R <[email protected]>
> [[email protected]: move all the changes together to enable DP-0 in EVM]
> Signed-off-by: Jayesh Choudhary <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 117 +++++++++++++++++++++++
> 1 file changed, 117 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> index 7ad152a1b90f..1145a7f046e2 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> @@ -249,6 +249,28 @@ vdd_sd_dv: regulator-TLV71033 {
> states = <1800000 0x0>,
> <3300000 0x1>;
> };
> +
> + dp0_pwr_3v3: regulator-dp0-prw {
> + compatible = "regulator-fixed";
> + regulator-name = "dp0-pwr";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&exp4 0 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + dp0: dp0-connector {
dp0-connector is not a standard name.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
how about connector-dp0?
> + compatible = "dp-connector";
> + label = "DP0";
> + type = "full-size";
> + dp-pwr-supply = <&dp0_pwr_3v3>;
> +
> + port {
> + dp0_connector_in: endpoint {
> + remote-endpoint = <&dp0_out>;
> + };
> + };
> + };
> };
>
> &main_pmx0 {
> @@ -286,6 +308,19 @@ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
> J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
> >;
> };
> +
> + dp0_pins_default: dp0-pins-default {
> + pinctrl-single,pins = <
> + J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */
> + >;
> + };
> +
> + main_i2c4_pins_default: main-i2c4-pins-default {
> + pinctrl-single,pins = <
> + J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */
> + J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */
> + >;
> + };
> };
>
> &wkup_pmx2 {
> @@ -827,3 +862,85 @@ adc {
> ti,adc-channels = <0 1 2 3 4 5 6 7>;
> };
> };
> +
> +&serdes_refclk {
> + status = "okay";
> + clock-frequency = <100000000>;
> +};
> +
> +&dss {
> + status = "okay";
> + assigned-clocks = <&k3_clks 218 2>,
> + <&k3_clks 218 5>,
> + <&k3_clks 218 14>,
> + <&k3_clks 218 18>;
> + assigned-clock-parents = <&k3_clks 218 3>,
> + <&k3_clks 218 7>,
> + <&k3_clks 218 16>,
> + <&k3_clks 218 22>;
> +};
> +
> +&serdes_wiz4 {
> + status = "okay";
> +};
> +
> +&serdes4 {
> + status = "okay";
> + serdes4_dp_link: phy@0 {
> + reg = <0>;
> + cdns,num-lanes = <4>;
> + #phy-cells = <0>;
> + cdns,phy-type = <PHY_TYPE_DP>;
> + resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
> + <&serdes_wiz4 3>, <&serdes_wiz4 4>;
> + };
> +};
> +
> +&mhdp {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&dp0_pins_default>;
> + phys = <&serdes4_dp_link>;
> + phy-names = "dpphy";
> +};
> +
> +&dss_ports {
> + port {
> + dpi0_out: endpoint {
> + remote-endpoint = <&dp0_in>;
> + };
> + };
> +};
> +
> +&main_i2c4 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_i2c4_pins_default>;
> + clock-frequency = <400000>;
> +
> + exp4: gpio@20 {
> + compatible = "ti,tca6408";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +};
> +
> +&dp0_ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dp0_in: endpoint {
> + remote-endpoint = <&dpi0_out>;
> + };
> + };
> +
> + port@4 {
> + reg = <4>;
> + dp0_out: endpoint {
> + remote-endpoint = <&dp0_connector_in>;
> + };
> + };
> +};
--
cheers,
-roger
On 01/08/2023 10:00, Jayesh Choudhary wrote:
> From: Siddharth Vadapalli <[email protected]>
>
> J784S4 SoC has 4 Serdes instances along with their respective WIZ
> instances. Add device-tree nodes for them and disable them by default.
>
> Signed-off-by: Siddharth Vadapalli <[email protected]>
> [[email protected]: fix serdes_wiz clock order & disable serdes refclk]
> Signed-off-by: Jayesh Choudhary <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 172 +++++++++++++++++++++
> 1 file changed, 172 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> index 8a816563706b..fbf5ab94d785 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -6,9 +6,19 @@
> */
>
> #include <dt-bindings/mux/mux.h>
> +#include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/phy/phy-ti.h>
>
> #include "k3-serdes.h"
>
> +/ {
> + serdes_refclk: serdes-refclk {
standard name should begin with clock
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + status = "disabled";
> + };
> +};
> +
> &cbass_main {
> msmc_ram: sram@70000000 {
> compatible = "mmio-sram";
> @@ -709,6 +719,168 @@ main_sdhci1: mmc@4fb0000 {
> status = "disabled";
> };
>
> + serdes_wiz0: wiz@5060000 {
> + compatible = "ti,j784s4-wiz-10g";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
> + assigned-clocks = <&k3_clks 404 6>;
> + assigned-clock-parents = <&k3_clks 404 10>;
> + num-lanes = <4>;
> + #reset-cells = <1>;
> + #clock-cells = <1>;
> + ranges = <0x5060000 0x00 0x5060000 0x10000>;
> +> + status = "disabled";
> +
drop blank lines here and rest of this file where you set status to "disabled".
> + serdes0: serdes@5060000 {
phy@5060000
> + compatible = "ti,j721e-serdes-10g";
> + reg = <0x05060000 0x010000>;
> + reg-names = "torrent_phy";
> + resets = <&serdes_wiz0 0>;
> + reset-names = "torrent_reset";
> + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
> + clock-names = "refclk", "phy_en_refclk";
> + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
> + assigned-clock-parents = <&k3_clks 404 6>,
> + <&k3_clks 404 6>,
> + <&k3_clks 404 6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #clock-cells = <1>;
> +
> + status = "disabled";
> + };
> + };
> +
> + serdes_wiz1: wiz@5070000 {
> + compatible = "ti,j784s4-wiz-10g";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
> + assigned-clocks = <&k3_clks 405 6>;
> + assigned-clock-parents = <&k3_clks 405 10>;
> + num-lanes = <4>;
> + #reset-cells = <1>;
> + #clock-cells = <1>;
> + ranges = <0x05070000 0x00 0x05070000 0x10000>;
> +
> + status = "disabled";
> +
> + serdes1: serdes@5070000 {
phy@5070000
> + compatible = "ti,j721e-serdes-10g";
> + reg = <0x05070000 0x010000>;
> + reg-names = "torrent_phy";
> + resets = <&serdes_wiz1 0>;
> + reset-names = "torrent_reset";
> + clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
> + clock-names = "refclk", "phy_en_refclk";
> + assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
> + <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
> + assigned-clock-parents = <&k3_clks 405 6>,
> + <&k3_clks 405 6>,
> + <&k3_clks 405 6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #clock-cells = <1>;
> +
> + status = "disabled";
> + };
> + };
> +
> + serdes_wiz2: wiz@5020000 {
> + compatible = "ti,j784s4-wiz-10g";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
> + assigned-clocks = <&k3_clks 406 6>;
> + assigned-clock-parents = <&k3_clks 406 10>;
> + num-lanes = <4>;
> + #reset-cells = <1>;
> + #clock-cells = <1>;
> + ranges = <0x05020000 0x00 0x05020000 0x10000>;
> +
> + status = "disabled";
> +
> + serdes2: serdes@5020000 {
phy@5020000
> + compatible = "ti,j721e-serdes-10g";
> + reg = <0x05020000 0x010000>;
> + reg-names = "torrent_phy";
> + resets = <&serdes_wiz2 0>;
> + reset-names = "torrent_reset";
> + clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>;
> + clock-names = "refclk", "phy_en_refclk";
> + assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
> + <&serdes_wiz2 TI_WIZ_REFCLK_DIG>;
> + assigned-clock-parents = <&k3_clks 406 6>,
> + <&k3_clks 406 6>,
> + <&k3_clks 406 6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #clock-cells = <1>;
> +
> + status = "disabled";
> + };
> + };
> +
> + serdes_wiz4: wiz@5050000 {
> + compatible = "ti,j784s4-wiz-10g";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
> + assigned-clocks = <&k3_clks 407 6>;
> + assigned-clock-parents = <&k3_clks 407 10>;
> + num-lanes = <4>;
> + #reset-cells = <1>;
> + #clock-cells = <1>;
> + ranges = <0x05050000 0x00 0x05050000 0x10000>,
> + <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */
> +
> + status = "disabled";
> +
> + serdes4: serdes@5050000 {
phy@5050000
> + /*
> + * Note: we also map DPTX PHY registers as the Torrent
> + * needs to manage those.
> + */
> + compatible = "ti,j721e-serdes-10g";
> + reg = <0x05050000 0x010000>,
> + <0x0a030a00 0x40>; /* DPTX PHY */
> + reg-names = "torrent_phy";
> + resets = <&serdes_wiz4 0>;
> + reset-names = "torrent_reset";
> + clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>;
> + clock-names = "refclk", "phy_en_refclk";
> + assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
> + <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
> + assigned-clock-parents = <&k3_clks 407 6>,
> + <&k3_clks 407 6>,
> + <&k3_clks 407 6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #clock-cells = <1>;
> +
> + status = "disabled";
> + };
> + };
> +
> main_navss: bus@30000000 {
> compatible = "simple-bus";
> #address-cells = <2>;
--
cheers,
-roger
Hello Roger,
On 01/08/23 22:26, Roger Quadros wrote:
>
>
> On 01/08/2023 10:00, Jayesh Choudhary wrote:
>> From: Siddharth Vadapalli <[email protected]>
>>
>> J784S4 SoC has 4 Serdes instances along with their respective WIZ
>> instances. Add device-tree nodes for them and disable them by default.
>>
>> Signed-off-by: Siddharth Vadapalli <[email protected]>
>> [[email protected]: fix serdes_wiz clock order & disable serdes refclk]
>> Signed-off-by: Jayesh Choudhary <[email protected]>
>> ---
>> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 172 +++++++++++++++++++++
>> 1 file changed, 172 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> index 8a816563706b..fbf5ab94d785 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> @@ -6,9 +6,19 @@
>> */
>>
>> #include <dt-bindings/mux/mux.h>
>> +#include <dt-bindings/phy/phy.h>
>> +#include <dt-bindings/phy/phy-ti.h>
>>
>> #include "k3-serdes.h"
>>
>> +/ {
>> + serdes_refclk: serdes-refclk {
>
> standard name should begin with clock
>
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + status = "disabled";
>> + };
>> +};
>> +
>> &cbass_main {
>> msmc_ram: sram@70000000 {
>> compatible = "mmio-sram";
>> @@ -709,6 +719,168 @@ main_sdhci1: mmc@4fb0000 {
>> status = "disabled";
>> };
>>
>> + serdes_wiz0: wiz@5060000 {
>> + compatible = "ti,j784s4-wiz-10g";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>;
>> + clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
>> + assigned-clocks = <&k3_clks 404 6>;
>> + assigned-clock-parents = <&k3_clks 404 10>;
>> + num-lanes = <4>;
>> + #reset-cells = <1>;
>> + #clock-cells = <1>;
>> + ranges = <0x5060000 0x00 0x5060000 0x10000>;
>> +> + status = "disabled";
>> +
> drop blank lines here and rest of this file where you set status to "disabled".
>
>> + serdes0: serdes@5060000 {
>
> phy@5060000
According to the bindings, serdes is valid.
(./Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml)
It would throw dtbs_check errors with phy@.
If its a binding change that you are suggesting, then it can be picked
up later on for all platform at once.
So keeping it as serdes@50*0000 on all the suggested places.
>
>> + compatible = "ti,j721e-serdes-10g";
>> + reg = <0x05060000 0x010000>;
[...]
>> +
>> + serdes1: serdes@5070000 {
>
> phy@5070000
>> + compatible = "ti,j721e-serdes-10g";
>> + reg = <0x05070000 0x010000>;
>> + reg-names = "torrent_phy";
[...]
>> +
>> + status = "disabled";
>> +
>> + serdes2: serdes@5020000 {
>
> phy@5020000
>
>> + compatible = "ti,j721e-serdes-10g";
>> + reg = <0x05020000 0x010000>;
[...]
>> + status = "disabled";
>> +
>> + serdes4: serdes@5050000 {
>
> phy@5050000
>
>> + /*
[...]