This patch series adds the relevant phy and controller
configurations for enabling USB on IPQ9754
Portions of the patchset have been merged. Please see
https://lore.kernel.org/lkml/ZGN9gchu7dRb6QwC@matsya/
[v15]:
- Introduce fixed regulator definitions in the last patch
instead of earlier patch
[v14]:
- Missed Konrad's comment. Switch order of regulator-boot-on &
regulator-always-on in mp5496_l2 node
[v13]:
- Move fixed regulator definitions from SoC dtsi to board dts
- Remove 'dr_mode' from SoC dtsi
- Move 'status' property to the end
[v12]:
- In dtsi usb@8a00000 -> usb@8af8800
[v11]:
- Rename dwc_0 -> usb_0_dwc3
- Minor change in qcom,sc8280xp-qmp-usb3-uni-phy.yaml to factor in
latest updates to the file
[v10]:
- Fix regulator definitions
- Address couple of other comments
[v9]:
- Update bindings to make power-domains as optional since
IPQ9574 doesn't have GDSCs
[v8]:
- Update bindings for the clock name change
[v7]:
- com_aux -> cfg_ahb in patch 7
[v6]:
- Incorporated review comments
- Resolve make dtbs_check messages
- Fixed pcs_usb offset
- Board dts file name changed
[v5]:
- Incorporated review comments
- 'make dtbs_check' giving the following messages since
ipq9574 doesn't have power domains. Hope this is ok
/local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property
From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
/local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property
From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
- Move qmp phy DT node to newer specification
[v4]:
- Incorporated review comments
- Address all 'make dtbs_check' errors
[v3]:
- Incorporated review comments regarding coding style
[v2]:
- Incorporated review comments regarding coding style,
maintaining sorted order of entries and unused phy register
offsets
- Removed NOC clock entries from DT node (will be implemented
later with interconnect support)
- Fixed 'make dtbs_check' errors/warnings
[v1]:
https://lore.kernel.org/linux-arm-msm/[email protected]/T/
Varadarajan Narayanan (5):
dt-bindings: usb: dwc3: Add IPQ9574 compatible
clk: qcom: gcc-ipq9574: Add USB related clocks
arm64: dts: qcom: ipq9574: Add USB related nodes
arm64: dts: qcom: ipq9574: Add LDO regulator node
arm64: dts: qcom: ipq9574: Enable USB
.../devicetree/bindings/usb/qcom,dwc3.yaml | 3 +-
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 48 ++++++++++++
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 85 ++++++++++++++++++++++
drivers/clk/qcom/gcc-ipq9574.c | 37 ++++++++++
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 +
5 files changed, 174 insertions(+), 1 deletion(-)
--
2.7.4
Add the clocks needed for enabling USB in IPQ9574
Reviewed-by: Dmitry Baryshkov <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Changes in v12:
- Rebase qcom,ipq9574-gcc.h
Changes in v10:
- Add 'const' for .hw.init = &(struct clk_init_data)
Changes in v2:
- Fixed coding style issues
---
drivers/clk/qcom/gcc-ipq9574.c | 37 ++++++++++++++++++++++++++++
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 ++
2 files changed, 39 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 7b0505f..8e1a3ff 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -1969,6 +1969,41 @@ static struct clk_regmap_mux usb0_pipe_clk_src = {
},
};
+static struct clk_branch gcc_usb0_pipe_clk = {
+ .halt_reg = 0x2c054,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2c054,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb0_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &usb0_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_sleep_clk = {
+ .halt_reg = 0x2c058,
+ .clkr = {
+ .enable_reg = 0x2c058,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb0_sleep_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_sleep_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
F(144000, P_XO, 16, 12, 125),
F(400000, P_XO, 12, 1, 5),
@@ -3932,6 +3967,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
+ [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
+ [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
index 5a2961b..c7c914c 100644
--- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
@@ -210,4 +210,6 @@
#define GCC_SNOC_PCIE1_1LANE_S_CLK 201
#define GCC_SNOC_PCIE2_2LANE_S_CLK 202
#define GCC_SNOC_PCIE3_2LANE_S_CLK 203
+#define GCC_USB0_PIPE_CLK 204
+#define GCC_USB0_SLEEP_CLK 205
#endif
--
2.7.4
Add USB phy and controller related nodes
SS PHY need two supplies and HS PHY needs three supplies. 0.925V
and 3.3V are from fixed regulators and 1.8V is generated from
PMIC's LDO
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Changes in v15:
- Introduce fixed regulators in the last patch instead of this one
Changes in v13:
- Move fixed regulator definitions from SoC dtsi to board dts
- Remove 'dr_mode' from SoC dtsi
- Move 'status' property to the end
Changes in v12:
- Rebase
Changes in v11:
- Rename dwc_0 -> usb_0_dwc3
Changes in v10:
- Fix regulator definitions
Changes in v8:
- Change clocks order to match the bindings
Changes in v7:
- Change com_aux -> cfg_ahb
Changes in v6:
- Introduce fixed regulators for the phy
- Resolved all 'make dtbs_check' messages
Changes in v5:
- Fix additional comments
- Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml
- 'make dtbs_check' giving the following messages since
ipq9574 doesn't have power domains. Hope this is ok
/local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property
From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
/local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property
From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
Changes in v4:
- Use newer bindings without subnodes
- Fix coding style issues
Changes in v3:
- Insert the nodes at proper location
Changes in v2:
- Fixed issues flagged by Krzysztof
- Fix issues reported by make dtbs_check
- Remove NOC related clocks (to be added with proper
interconnect support)
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 85 +++++++++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 0baeb10..feabc19 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -465,6 +465,91 @@
status = "disabled";
};
+ usb_0_qusbphy: phy@7b000 {
+ compatible = "qcom,ipq9574-qusb2-phy";
+ reg = <0x0007b000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&xo_board_clk>;
+ clock-names = "cfg_ahb",
+ "ref";
+
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+ status = "disabled";
+ };
+
+ usb_0_qmpphy: phy@7d000 {
+ compatible = "qcom,ipq9574-qmp-usb3-phy";
+ reg = <0x0007d000 0xa00>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_AUX_CLK>,
+ <&xo_board_clk>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+
+ resets = <&gcc GCC_USB0_PHY_BCR>,
+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
+ reset-names = "phy",
+ "phy_phy";
+
+ #clock-cells = <0>;
+ clock-output-names = "usb0_pipe_clk";
+
+ status = "disabled";
+ };
+
+ usb3: usb@8af8800 {
+ compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
+ reg = <0x08af8800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_SNOC_USB_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_ANOC_USB_AXI_CLK>,
+ <&gcc GCC_USB0_SLEEP_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <200000000>,
+ <24000000>;
+
+ interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event";
+
+ resets = <&gcc GCC_USB_BCR>;
+ status = "disabled";
+
+ usb_0_dwc3: usb@8a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x8a00000 0xcd00>;
+ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "ref";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
--
2.7.4
* Document the IPQ9574 dwc3 compatible.
* Make power-domains as optional since IPQ9574 doesn't have GDSCs
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Changes in v9:
- Place ipq9574 alongwith similar SoCs instead of new entry
- Make power-domains as optional since IPQ9574 doesn't have GDSCs
Changes in v6:
- Made power-domains as optional
- Resolved all 'make dtbs_check' messages
Changes in v5:
- Restore removed constraints
Changes in v4:
- Update other relevant sections
- Remove constraints not applicable to IPQ9574
---
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
index 4a36e2b..ae24dac 100644
--- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
@@ -17,6 +17,7 @@ properties:
- qcom,ipq6018-dwc3
- qcom,ipq8064-dwc3
- qcom,ipq8074-dwc3
+ - qcom,ipq9574-dwc3
- qcom,msm8953-dwc3
- qcom,msm8994-dwc3
- qcom,msm8996-dwc3
@@ -134,7 +135,6 @@ required:
- "#address-cells"
- "#size-cells"
- ranges
- - power-domains
- clocks
- clock-names
- interrupts
@@ -178,6 +178,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,ipq9574-dwc3
- qcom,msm8953-dwc3
- qcom,msm8996-dwc3
- qcom,msm8998-dwc3
--
2.7.4
On Fri, 09 Jun 2023 11:26:29 +0530, Varadarajan Narayanan wrote:
> This patch series adds the relevant phy and controller
> configurations for enabling USB on IPQ9754
>
> Portions of the patchset have been merged. Please see
> https://lore.kernel.org/lkml/ZGN9gchu7dRb6QwC@matsya/
>
> [v15]:
> - Introduce fixed regulator definitions in the last patch
> instead of earlier patch
>
> [...]
Applied, thanks!
[3/5] arm64: dts: qcom: ipq9574: Add USB related nodes
commit: a98bfb31f6766db26e0d4f39c909b7e8926cb0d8
[4/5] arm64: dts: qcom: ipq9574: Add LDO regulator node
commit: d5506524d9d9f2be01cbff510b0b8eec0cc9d691
[5/5] arm64: dts: qcom: ipq9574: Enable USB
commit: ec4f047679d59294c98095ae2470d34c2f2335a2
Best regards,
--
Bjorn Andersson <[email protected]>