This patch series applies to the Cadence SD0801 PHY driver.
Cadence SD0801 PHY is also known as Torrent PHY. Torrent PHY
is a multiprotocol PHY supporting PHY configurations including
Display Port, USB and PCIe.
This patch series converts SD0801 PHY driver for DisplayPort into a
generic Torrent PHY driver, updates DisplayPort functionality with
reconfiguration support and finally adds platform dependent initialization
for TI J7 SoCs.
The patch series has following patches which applies the changes
in the below sequence
1. 001-dt-bindings-phy-Remove-Cadence-MHDP-PHY-dt-binding
This patch removes the MHDP PHY binding.
2. 002-dt-bindings-phy-Add-Cadence-MHDP-PHY-bindings-in-YAML-format.
This patch converts the MHDP PHY device tree bindings to yaml schemas
3. 003-phy-cadence-dp-Rename-to-phy-Cadence-Torrent
Rename Cadence DP PHY driver from phy-cadence-dp to phy-cadence-torrent
4. 004-phy-cadence-torrent-Adopt-Torrent-nomenclature
Update private data structures, module descriptions and functions prefix to Torrent
5. 005-phy-cadence-torrent-Add-wrapper-for-PHY-register-access
Add a wrapper function to write Torrent PHY registers to improve code readability.
6. 006-phy-cadence-torrent-Add-wrapper-for-DPTX-register-access
Add wrapper functions to read, write DisplayPort specific PHY registers to improve code
readability.
7. 007-phy-cadence-torrent-Refactor-code-for-reusability
Add separate function to set different power state values.
Use of uniform polling timeout value. Check return values of functions for error handling.
8. 008-phy-cadence-torrent-Add-19.2-MHz-reference-clock-support
Add configuration functions for 19.2 MHz reference clock support. Add register configurations
for SSC support.
9. 009-phy-cadence-torrent-Implement-phy-configure-APIs
Add PHY configuration APIs for link rate, number of lanes, voltage swing and pre-emphasis values.
10. 010-phy-cadence-torrent-Use-regmap-to-read-and-write-Torrent-PHY-registers
Use regmap for accessing Torrent PHY registers. Update register offsets. Abstract address
calculation using regmap APIs.
11. 011-phy: cadence-torrent-Use-regmap-to-read-and-write-DPTX-PHY-registers
Use regmap to read and write DPTX specific PHY registers.
12. 012-phy-cadence-torrent-Add-platform-dependent-initialization-structure
Add platform dependent initialization data for Torrent PHY used in TI's J721E SoC.
13. 013-phy: cadence-torrent-Add-support-for-subnode-bindings
Implement single link subnode support to the phy driver.
Version History:
v4:
- Add separate patch to remove old binding.
- Add new patch to add new binding in YAML format.
- Squashed "dt-bindings: phy: phy-cadence-torrent: Add platform dependent
compatible string" with "dt-bindings: phy: Add Cadence MHDP PHY bindings
in YAML format".
- Added SPDX dual license tag to YAML bindings.
- Updated resets property description and removed reset-names
property.
- Added enum to cdns,phy-type property adding all the currently
known phy-type values.
- Updated the child node resets property to support one reset
per lane.
- Added default values for cdns,num-lanes and cdns,max-bit-rate properties.
v3:
- Removed "Add clock binding" patch from the series and merged it with
"Convert-Cadence-MHDP-PHY-bindings-to-YAML" patch.
- Added reset and reset-names properties to YAML file.
- Updated dptx_phy reg entry as optional in YAML.
- Renamed reg-names from sd0801_phy to torrent_phy.
- Added subnode property for each group of PHY lanes based on PHY
type to the YAML. Renamed num_lanes and max_bit_rate to cdns,num-lanes
and cdns,max-bit-rate and moved it to subnode properties.
- Added cdns,phy-type property in subnode. Currently cdns,phy-type supports only
PHY_TYPE_DP.
- Added subnode instance structure to the driver in reference to the dts change.
- Updated functions to read properties from child node instead of parent node.
- Added num_lanes as argument to the cdns_torrent_dp_run function.
v2:
- Remove patch [1] from this series and send for a separate review.
- Use enum in compatible property of YAML file.
- Remove quotes in clock-names property "refclk" -> refclk in YAML file.
- Add reg-names property to YAML file
- Add additionalProperties:false to YAML file.
- No change in the driver code.
This patch series is dependent on PHY DisplayPort configuration patch [1].
[1]
https://lkml.org/lkml/2020/1/6/279
Swapnil Jakhade (10):
phy: cadence-torrent: Adopt Torrent nomenclature
phy: cadence-torrent: Add wrapper for PHY register access
phy: cadence-torrent: Add wrapper for DPTX register access
phy: cadence-torrent: Refactor code for reusability
phy: cadence-torrent: Add 19.2 MHz reference clock support
phy: cadence-torrent: Implement PHY configure APIs
phy: cadence-torrent: Use regmap to read and write Torrent PHY
registers
phy: cadence-torrent: Use regmap to read and write DPTX PHY registers
phy: cadence-torrent: Add platform dependent initialization structure
phy: cadence-torrent: Add support for subnode bindings
Yuti Amonkar (3):
dt-bindings: phy: Remove Cadence MHDP PHY dt binding
dt-bindings: phy: Add Cadence MHDP PHY bindings in YAML format.
phy: cadence-dp: Rename to phy-cadence-torrent
.../bindings/phy/phy-cadence-dp.txt | 30 -
.../bindings/phy/phy-cadence-torrent.yaml | 143 ++
drivers/phy/cadence/Kconfig | 6 +-
drivers/phy/cadence/Makefile | 2 +-
drivers/phy/cadence/phy-cadence-dp.c | 541 -----
drivers/phy/cadence/phy-cadence-torrent.c | 1944 +++++++++++++++++
6 files changed, 2091 insertions(+), 575 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
delete mode 100644 drivers/phy/cadence/phy-cadence-dp.c
create mode 100644 drivers/phy/cadence/phy-cadence-torrent.c
--
2.20.1
- Add Cadence MHDP PHY bindings in YAML format.
- Add Torrent PHY reference clock bindings.
- Add sub-node bindings for each group of PHY lanes based on PHY type.
Each sub-node includes properties such as master lane number, link reset,
phy type, number of lanes etc.
- Add reset support including PHY reset and individual lane reset.
- Add a new compatible string used for TI SoCs using Torrent PHY.
This will not affect ABI as the driver has never been functional,
and therefore do not exist in any active use case.
Signed-off-by: Yuti Amonkar <[email protected]>
---
.../bindings/phy/phy-cadence-torrent.yaml | 143 ++++++++++++++++++
1 file changed, 143 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
new file mode 100644
index 000000000000..9f94be1dce6e
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Cadence Torrent SD0801 PHY binding for DisplayPort
+
+description:
+ This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
+ hardware included with the Cadence MHDP DisplayPort controller.
+
+maintainers:
+ - Swapnil Jakhade <[email protected]>
+ - Yuti Amonkar <[email protected]>
+
+properties:
+ compatible:
+ enum:
+ - cdns,torrent-phy
+ - ti,j721e-serdes-10g
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ clocks:
+ maxItems: 1
+ description:
+ PHY reference clock. Must contain an entry in clock-names.
+
+ clock-names:
+ const: refclk
+
+ reg:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: Offset of the Torrent PHY configuration registers.
+ - description: Offset of the DPTX PHY configuration registers.
+
+ reg-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: torrent_phy
+ - const: dptx_phy
+
+ resets:
+ maxItems: 1
+ description:
+ Torrent PHY reset.
+ See Documentation/devicetree/bindings/reset/reset.txt
+
+patternProperties:
+ '^phy@[0-7]+$':
+ type: object
+ description:
+ Each group of PHY lanes with a single master lane should be represented as a sub-node.
+ properties:
+ reg:
+ description:
+ The master lane number. This is the lowest numbered lane in the lane group.
+
+ resets:
+ minItems: 1
+ maxItems: 4
+ description:
+ Contains list of resets, one per lane, to get all the link lanes out of reset.
+
+ "#phy-cells":
+ const: 0
+
+ cdns,phy-type:
+ description:
+ Specifies the type of PHY for which the group of PHY lanes is used.
+ Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [1, 2, 3, 4, 5, 6]
+
+ cdns,num-lanes:
+ description:
+ Number of DisplayPort lanes.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [1, 2, 4]
+ default: 4
+
+ cdns,max-bit-rate:
+ description:
+ Maximum DisplayPort link bit rate to use, in Mbps
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
+ default: 8100
+
+ required:
+ - reg
+ - resets
+ - "#phy-cells"
+ - cdns,phy-type
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+ - clocks
+ - clock-names
+ - reg
+ - reg-names
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+ torrent_phy: phy@f0fb500000 {
+ compatible = "cdns,torrent-phy";
+ reg = <0xf0 0xfb500000 0x0 0x00100000>,
+ <0xf0 0xfb030a00 0x0 0x00000040>;
+ reg-names = "torrent_phy", "dptx_phy";
+ resets = <&phyrst 0>;
+ clocks = <&ref_clk>;
+ clock-names = "refclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ torrent_phy_dp: phy@0 {
+ reg = <0>;
+ resets = <&phyrst 1>, <&phyrst 2>,
+ <&phyrst 3>, <&phyrst 4>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_DP>;
+ cdns,num-lanes = <4>;
+ cdns,max-bit-rate = <8100>;
+ };
+ };
+...
--
2.20.1
From: Swapnil Jakhade <[email protected]>
Add wrapper functions to read, write DisplayPort specific PHY registers to
improve code readability.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Yuti Amonkar <[email protected]>
---
drivers/phy/cadence/phy-cadence-torrent.c | 71 ++++++++++++++++-------
1 file changed, 50 insertions(+), 21 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 59c85d8b9e16..5c7c185ddbfe 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -140,13 +140,31 @@ static void cdns_torrent_phy_write(struct cdns_torrent_phy *cdns_phy,
writel(val, cdns_phy->sd_base + offset);
}
+/* DPTX mmr access functions */
+
+static void cdns_torrent_dp_write(struct cdns_torrent_phy *cdns_phy,
+ u32 offset, u32 val)
+{
+ writel(val, cdns_phy->base + offset);
+}
+
+static u32 cdns_torrent_dp_read(struct cdns_torrent_phy *cdns_phy, u32 offset)
+{
+ return readl(cdns_phy->base + offset);
+}
+
+#define cdns_torrent_dp_read_poll_timeout(cdns_phy, offset, val, cond, \
+ delay_us, timeout_us) \
+ readl_poll_timeout((cdns_phy)->base + (offset), \
+ val, cond, delay_us, timeout_us)
+
static int cdns_torrent_dp_init(struct phy *phy)
{
unsigned char lane_bits;
struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy);
- writel(0x0003, cdns_phy->base + PHY_AUX_CTRL); /* enable AUX */
+ cdns_torrent_dp_write(cdns_phy, PHY_AUX_CTRL, 0x0003); /* enable AUX */
/* PHY PMA registers configuration function */
cdns_torrent_dp_pma_cfg(cdns_phy);
@@ -195,11 +213,11 @@ static int cdns_torrent_dp_init(struct phy *phy)
* used lanes
*/
lane_bits = (1 << cdns_phy->num_lanes) - 1;
- writel(((0xF & ~lane_bits) << 4) | (0xF & lane_bits),
- cdns_phy->base + PHY_RESET);
+ cdns_torrent_dp_write(cdns_phy, PHY_RESET,
+ ((0xF & ~lane_bits) << 4) | (0xF & lane_bits));
/* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
- writel(0x0001, cdns_phy->base + PHY_PMA_XCVR_PLLCLK_EN);
+ cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
/* PHY PMA registers configuration functions */
cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy);
@@ -219,8 +237,8 @@ void cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
unsigned int reg;
int ret;
- ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_CMN_READY, reg,
- reg & 1, 0, 500);
+ ret = cdns_torrent_dp_read_poll_timeout(cdns_phy, PHY_PMA_CMN_READY,
+ reg, reg & 1, 0, 500);
if (ret == -ETIMEDOUT)
dev_err(cdns_phy->dev,
"timeout waiting for PMA common ready\n");
@@ -391,8 +409,10 @@ static void cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy)
* waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
* master lane
*/
- ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_PLLCLK_EN_ACK,
- read_val, read_val & 1, 0, POLL_TIMEOUT_US);
+ ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
+ PHY_PMA_XCVR_PLLCLK_EN_ACK,
+ read_val, read_val & 1, 0,
+ POLL_TIMEOUT_US);
if (ret == -ETIMEDOUT)
dev_err(cdns_phy->dev,
"timeout waiting for link PLL clock enable ack\n");
@@ -417,28 +437,35 @@ static void cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy)
break;
}
- writel(write_val1, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
+ cdns_torrent_dp_write(cdns_phy,
+ PHY_PMA_XCVR_POWER_STATE_REQ, write_val1);
+
+ ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
+ PHY_PMA_XCVR_POWER_STATE_ACK,
+ read_val,
+ (read_val & mask) == write_val1,
+ 0, POLL_TIMEOUT_US);
- ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_ACK,
- read_val, (read_val & mask) == write_val1, 0,
- POLL_TIMEOUT_US);
if (ret == -ETIMEDOUT)
dev_err(cdns_phy->dev,
"timeout waiting for link power state ack\n");
- writel(0, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
+ cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ, 0);
ndelay(100);
- writel(write_val2, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
+ cdns_torrent_dp_write(cdns_phy,
+ PHY_PMA_XCVR_POWER_STATE_REQ, write_val2);
- ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_ACK,
- read_val, (read_val & mask) == write_val2, 0,
- POLL_TIMEOUT_US);
+ ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
+ PHY_PMA_XCVR_POWER_STATE_ACK,
+ read_val,
+ (read_val & mask) == write_val2,
+ 0, POLL_TIMEOUT_US);
if (ret == -ETIMEDOUT)
dev_err(cdns_phy->dev,
"timeout waiting for link power state ack\n");
- writel(0, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
+ cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ, 0);
ndelay(100);
}
@@ -450,9 +477,11 @@ static void cdns_dp_phy_write_field(struct cdns_torrent_phy *cdns_phy,
{
unsigned int read_val;
- read_val = readl(cdns_phy->base + offset);
- writel(((val << start_bit) | (read_val & ~(((1 << num_bits) - 1) <<
- start_bit))), cdns_phy->base + offset);
+ read_val = cdns_torrent_dp_read(cdns_phy, offset);
+ cdns_torrent_dp_write(cdns_phy, offset,
+ ((val << start_bit) |
+ (read_val & ~(((1 << num_bits) - 1) <<
+ start_bit))));
}
static int cdns_torrent_phy_probe(struct platform_device *pdev)
--
2.20.1
On Thu, 6 Feb 2020 07:10:50 +0100, Yuti Amonkar wrote:
> - Add Cadence MHDP PHY bindings in YAML format.
> - Add Torrent PHY reference clock bindings.
> - Add sub-node bindings for each group of PHY lanes based on PHY type.
> Each sub-node includes properties such as master lane number, link reset,
> phy type, number of lanes etc.
> - Add reset support including PHY reset and individual lane reset.
> - Add a new compatible string used for TI SoCs using Torrent PHY.
> This will not affect ABI as the driver has never been functional,
> and therefore do not exist in any active use case.
>
> Signed-off-by: Yuti Amonkar <[email protected]>
> ---
> .../bindings/phy/phy-cadence-torrent.yaml | 143 ++++++++++++++++++
> 1 file changed, 143 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be at root node
Error: Documentation/devicetree/bindings/phy/phy-cadence-torrent.example.dts:33.42-43 syntax error
FATAL ERROR: Unable to parse input tree
scripts/Makefile.lib:300: recipe for target 'Documentation/devicetree/bindings/phy/phy-cadence-torrent.example.dt.yaml' failed
make[1]: *** [Documentation/devicetree/bindings/phy/phy-cadence-torrent.example.dt.yaml] Error 1
Makefile:1263: recipe for target 'dt_binding_check' failed
make: *** [dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1234141
Please check and re-submit.
Hi Rob,
Thanks for the review.
> -----Original Message-----
> From: Rob Herring <[email protected]>
> Sent: Friday, February 7, 2020 2:25
> To: Yuti Suresh Amonkar <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; Milind Parab <[email protected]>; Swapnil Kashinath
> Jakhade <[email protected]>; Yuti Suresh Amonkar
> <[email protected]>
> Subject: Re: [PATCH v4 02/13] dt-bindings: phy: Add Cadence MHDP PHY
> bindings in YAML format.
>
> EXTERNAL MAIL
>
>
> On Thu, 6 Feb 2020 07:10:50 +0100, Yuti Amonkar wrote:
> > - Add Cadence MHDP PHY bindings in YAML format.
> > - Add Torrent PHY reference clock bindings.
> > - Add sub-node bindings for each group of PHY lanes based on PHY type.
> > Each sub-node includes properties such as master lane number, link reset,
> > phy type, number of lanes etc.
> > - Add reset support including PHY reset and individual lane reset.
> > - Add a new compatible string used for TI SoCs using Torrent PHY.
> > This will not affect ABI as the driver has never been functional, and
> > therefore do not exist in any active use case.
> >
> > Signed-off-by: Yuti Amonkar <[email protected]>
> > ---
> > .../bindings/phy/phy-cadence-torrent.yaml | 143 ++++++++++++++++++
> > 1 file changed, 143 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> >
>
> My bot found errors running 'make dt_binding_check' on your patch:
>
> Documentation/devicetree/bindings/display/simple-
> framebuffer.example.dts:21.16-37.11: Warning (chosen_node_is_root):
> /example-0/chosen: chosen node must be at root node
> Error: Documentation/devicetree/bindings/phy/phy-cadence-
> torrent.example.dts:33.42-43 syntax error FATAL ERROR: Unable to parse
> input tree
> scripts/Makefile.lib:300: recipe for target
> 'Documentation/devicetree/bindings/phy/phy-cadence-
> torrent.example.dt.yaml' failed
> make[1]: *** [Documentation/devicetree/bindings/phy/phy-cadence-
> torrent.example.dt.yaml] Error 1
> Makefile:1263: recipe for target 'dt_binding_check' failed
> make: *** [dt_binding_check] Error 2
>
I think this error is due to missing PHY_TYPE_DP macro in the include/dt-bindings/phy/phy.h file. This macro is defined in the patch [1] which is available in phy-next. I forgot to mention dependency of this patch series on [1]. Should I send the series again by mentioning the dependency in the cover letter?
[1]
https://lkml.org/lkml/2019/12/9/586
> See https://urldefense.proofpoint.com/v2/url?u=https-
> 3A__patchwork.ozlabs.org_patch_1234141&d=DwIBAg&c=aUq983L2pue2Fq
> KFoP6PGHMJQyoJ7kl3s3GZ-
> _haXqY&r=xythEVTj32hrXbonw_U5uD9n5Dh9J7TTTznvmGAGKo4&m=4HxnP
> HG3MyXrwx28RZFwK7SF4T0LlYYpDjAaJcJ0lXI&s=zp6pUcrsuA4OAIRcws8y1rxY
> xC4OrNk7GCrLcWqE0z8&e=
> Please check and re-submit.
Thanks & Regards,
Yuti Amonkar
On 06/02/2020 22:55, Rob Herring wrote:
> On Thu, 6 Feb 2020 07:10:50 +0100, Yuti Amonkar wrote:
>> - Add Cadence MHDP PHY bindings in YAML format.
>> - Add Torrent PHY reference clock bindings.
>> - Add sub-node bindings for each group of PHY lanes based on PHY type.
>> Each sub-node includes properties such as master lane number, link reset,
>> phy type, number of lanes etc.
>> - Add reset support including PHY reset and individual lane reset.
>> - Add a new compatible string used for TI SoCs using Torrent PHY.
>> This will not affect ABI as the driver has never been functional,
>> and therefore do not exist in any active use case.
>>
>> Signed-off-by: Yuti Amonkar <[email protected]>
>> ---
>> .../bindings/phy/phy-cadence-torrent.yaml | 143 ++++++++++++++++++
>> 1 file changed, 143 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>>
>
> My bot found errors running 'make dt_binding_check' on your patch:
>
> Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be at root node
> Error: Documentation/devicetree/bindings/phy/phy-cadence-torrent.example.dts:33.42-43 syntax error
> FATAL ERROR: Unable to parse input tree
> scripts/Makefile.lib:300: recipe for target 'Documentation/devicetree/bindings/phy/phy-cadence-torrent.example.dt.yaml' failed
> make[1]: *** [Documentation/devicetree/bindings/phy/phy-cadence-torrent.example.dt.yaml] Error 1
> Makefile:1263: recipe for target 'dt_binding_check' failed
> make: *** [dt_binding_check] Error 2
>
> See https://patchwork.ozlabs.org/patch/1234141
> Please check and re-submit.
>
This should work now, that 8a79db5e83a5d52c74e6f3c40d6f312cf899213e is
in, if applied again on top of recently tagged v5.6-rc1 .
Best regards,
Jyri
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
On 06/02/20 11:40 am, Yuti Amonkar wrote:
> This patch series applies to the Cadence SD0801 PHY driver.
> Cadence SD0801 PHY is also known as Torrent PHY. Torrent PHY
> is a multiprotocol PHY supporting PHY configurations including
> Display Port, USB and PCIe.
>
> This patch series converts SD0801 PHY driver for DisplayPort into a
> generic Torrent PHY driver, updates DisplayPort functionality with
> reconfiguration support and finally adds platform dependent initialization
> for TI J7 SoCs.
merged now, Thanks!
-Kishon
>
> The patch series has following patches which applies the changes
> in the below sequence
> 1. 001-dt-bindings-phy-Remove-Cadence-MHDP-PHY-dt-binding
> This patch removes the MHDP PHY binding.
> 2. 002-dt-bindings-phy-Add-Cadence-MHDP-PHY-bindings-in-YAML-format.
> This patch converts the MHDP PHY device tree bindings to yaml schemas
> 3. 003-phy-cadence-dp-Rename-to-phy-Cadence-Torrent
> Rename Cadence DP PHY driver from phy-cadence-dp to phy-cadence-torrent
> 4. 004-phy-cadence-torrent-Adopt-Torrent-nomenclature
> Update private data structures, module descriptions and functions prefix to Torrent
> 5. 005-phy-cadence-torrent-Add-wrapper-for-PHY-register-access
> Add a wrapper function to write Torrent PHY registers to improve code readability.
> 6. 006-phy-cadence-torrent-Add-wrapper-for-DPTX-register-access
> Add wrapper functions to read, write DisplayPort specific PHY registers to improve code
> readability.
> 7. 007-phy-cadence-torrent-Refactor-code-for-reusability
> Add separate function to set different power state values.
> Use of uniform polling timeout value. Check return values of functions for error handling.
> 8. 008-phy-cadence-torrent-Add-19.2-MHz-reference-clock-support
> Add configuration functions for 19.2 MHz reference clock support. Add register configurations
> for SSC support.
> 9. 009-phy-cadence-torrent-Implement-phy-configure-APIs
> Add PHY configuration APIs for link rate, number of lanes, voltage swing and pre-emphasis values.
> 10. 010-phy-cadence-torrent-Use-regmap-to-read-and-write-Torrent-PHY-registers
> Use regmap for accessing Torrent PHY registers. Update register offsets. Abstract address
> calculation using regmap APIs.
> 11. 011-phy: cadence-torrent-Use-regmap-to-read-and-write-DPTX-PHY-registers
> Use regmap to read and write DPTX specific PHY registers.
> 12. 012-phy-cadence-torrent-Add-platform-dependent-initialization-structure
> Add platform dependent initialization data for Torrent PHY used in TI's J721E SoC.
> 13. 013-phy: cadence-torrent-Add-support-for-subnode-bindings
> Implement single link subnode support to the phy driver.
>
> Version History:
>
> v4:
> - Add separate patch to remove old binding.
> - Add new patch to add new binding in YAML format.
> - Squashed "dt-bindings: phy: phy-cadence-torrent: Add platform dependent
> compatible string" with "dt-bindings: phy: Add Cadence MHDP PHY bindings
> in YAML format".
> - Added SPDX dual license tag to YAML bindings.
> - Updated resets property description and removed reset-names
> property.
> - Added enum to cdns,phy-type property adding all the currently
> known phy-type values.
> - Updated the child node resets property to support one reset
> per lane.
> - Added default values for cdns,num-lanes and cdns,max-bit-rate properties.
>
>
> v3:
> - Removed "Add clock binding" patch from the series and merged it with
> "Convert-Cadence-MHDP-PHY-bindings-to-YAML" patch.
> - Added reset and reset-names properties to YAML file.
> - Updated dptx_phy reg entry as optional in YAML.
> - Renamed reg-names from sd0801_phy to torrent_phy.
> - Added subnode property for each group of PHY lanes based on PHY
> type to the YAML. Renamed num_lanes and max_bit_rate to cdns,num-lanes
> and cdns,max-bit-rate and moved it to subnode properties.
> - Added cdns,phy-type property in subnode. Currently cdns,phy-type supports only
> PHY_TYPE_DP.
> - Added subnode instance structure to the driver in reference to the dts change.
> - Updated functions to read properties from child node instead of parent node.
> - Added num_lanes as argument to the cdns_torrent_dp_run function.
>
> v2:
> - Remove patch [1] from this series and send for a separate review.
> - Use enum in compatible property of YAML file.
> - Remove quotes in clock-names property "refclk" -> refclk in YAML file.
> - Add reg-names property to YAML file
> - Add additionalProperties:false to YAML file.
> - No change in the driver code.
>
> This patch series is dependent on PHY DisplayPort configuration patch [1].
>
> [1]
>
> https://lkml.org/lkml/2020/1/6/279
>
> Swapnil Jakhade (10):
> phy: cadence-torrent: Adopt Torrent nomenclature
> phy: cadence-torrent: Add wrapper for PHY register access
> phy: cadence-torrent: Add wrapper for DPTX register access
> phy: cadence-torrent: Refactor code for reusability
> phy: cadence-torrent: Add 19.2 MHz reference clock support
> phy: cadence-torrent: Implement PHY configure APIs
> phy: cadence-torrent: Use regmap to read and write Torrent PHY
> registers
> phy: cadence-torrent: Use regmap to read and write DPTX PHY registers
> phy: cadence-torrent: Add platform dependent initialization structure
> phy: cadence-torrent: Add support for subnode bindings
>
> Yuti Amonkar (3):
> dt-bindings: phy: Remove Cadence MHDP PHY dt binding
> dt-bindings: phy: Add Cadence MHDP PHY bindings in YAML format.
> phy: cadence-dp: Rename to phy-cadence-torrent
>
> .../bindings/phy/phy-cadence-dp.txt | 30 -
> .../bindings/phy/phy-cadence-torrent.yaml | 143 ++
> drivers/phy/cadence/Kconfig | 6 +-
> drivers/phy/cadence/Makefile | 2 +-
> drivers/phy/cadence/phy-cadence-dp.c | 541 -----
> drivers/phy/cadence/phy-cadence-torrent.c | 1944 +++++++++++++++++
> 6 files changed, 2091 insertions(+), 575 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
> create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> delete mode 100644 drivers/phy/cadence/phy-cadence-dp.c
> create mode 100644 drivers/phy/cadence/phy-cadence-torrent.c
>
On Thu, Feb 6, 2020 at 12:11 AM Yuti Amonkar <[email protected]> wrote:
>
> - Add Cadence MHDP PHY bindings in YAML format.
> - Add Torrent PHY reference clock bindings.
> - Add sub-node bindings for each group of PHY lanes based on PHY type.
> Each sub-node includes properties such as master lane number, link reset,
> phy type, number of lanes etc.
> - Add reset support including PHY reset and individual lane reset.
> - Add a new compatible string used for TI SoCs using Torrent PHY.
> This will not affect ABI as the driver has never been functional,
> and therefore do not exist in any active use case.
>
> Signed-off-by: Yuti Amonkar <[email protected]>
> ---
> .../bindings/phy/phy-cadence-torrent.yaml | 143 ++++++++++++++++++
> 1 file changed, 143 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> new file mode 100644
> index 000000000000..9f94be1dce6e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> @@ -0,0 +1,143 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Cadence Torrent SD0801 PHY binding for DisplayPort
> +
> +description:
> + This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
> + hardware included with the Cadence MHDP DisplayPort controller.
> +
> +maintainers:
> + - Swapnil Jakhade <[email protected]>
> + - Yuti Amonkar <[email protected]>
> +
> +properties:
> + compatible:
> + enum:
> + - cdns,torrent-phy
> + - ti,j721e-serdes-10g
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
> +
> + clocks:
> + maxItems: 1
> + description:
> + PHY reference clock. Must contain an entry in clock-names.
> +
> + clock-names:
> + const: refclk
> +
> + reg:
> + minItems: 1
> + maxItems: 2
> + items:
> + - description: Offset of the Torrent PHY configuration registers.
> + - description: Offset of the DPTX PHY configuration registers.
> +
> + reg-names:
> + minItems: 1
> + maxItems: 2
> + items:
> + - const: torrent_phy
> + - const: dptx_phy
> +
> + resets:
> + maxItems: 1
> + description:
> + Torrent PHY reset.
> + See Documentation/devicetree/bindings/reset/reset.txt
> +
> +patternProperties:
> + '^phy@[0-7]+$':
> + type: object
> + description:
> + Each group of PHY lanes with a single master lane should be represented as a sub-node.
> + properties:
> + reg:
> + description:
> + The master lane number. This is the lowest numbered lane in the lane group.
> +
> + resets:
> + minItems: 1
> + maxItems: 4
> + description:
> + Contains list of resets, one per lane, to get all the link lanes out of reset.
> +
> + "#phy-cells":
> + const: 0
> +
> + cdns,phy-type:
> + description:
> + Specifies the type of PHY for which the group of PHY lanes is used.
> + Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [1, 2, 3, 4, 5, 6]
> +
> + cdns,num-lanes:
> + description:
> + Number of DisplayPort lanes.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [1, 2, 4]
> + default: 4
> +
> + cdns,max-bit-rate:
> + description:
> + Maximum DisplayPort link bit rate to use, in Mbps
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
> + default: 8100
> +
> + required:
> + - reg
> + - resets
> + - "#phy-cells"
> + - cdns,phy-type
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - "#address-cells"
> + - "#size-cells"
> + - clocks
> + - clock-names
> + - reg
> + - reg-names
> + - resets
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/phy/phy.h>
> + torrent_phy: phy@f0fb500000 {
The example still fails, now in linux-next:
Documentation/devicetree/bindings/phy/phy-cadence-torrent.example.dt.yaml:
phy@f0fb500000: '#phy-cells' is a required property
This is because of the node name 'phy' and this node is not a phy
provider (the child nodes are). Just use 'torrent-phy@...' here.
> + compatible = "cdns,torrent-phy";
> + reg = <0xf0 0xfb500000 0x0 0x00100000>,
> + <0xf0 0xfb030a00 0x0 0x00000040>;
> + reg-names = "torrent_phy", "dptx_phy";
> + resets = <&phyrst 0>;
> + clocks = <&ref_clk>;
> + clock-names = "refclk";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + torrent_phy_dp: phy@0 {
> + reg = <0>;
> + resets = <&phyrst 1>, <&phyrst 2>,
> + <&phyrst 3>, <&phyrst 4>;
> + #phy-cells = <0>;
> + cdns,phy-type = <PHY_TYPE_DP>;
> + cdns,num-lanes = <4>;
> + cdns,max-bit-rate = <8100>;
> + };
> + };
> +...
> --
> 2.20.1
>