2023-12-08 16:07:44

by Conor Dooley

Subject: [PATCH v1] dt-bindings: riscv: permit numbers in "riscv,isa"

From: Conor Dooley <[email protected]>

There are some extensions that contain numbers, such as Zve32f, which
are enabled by the "max" cpu type in QEMU.

Signed-off-by: Conor Dooley <[email protected]>
---
CC: Conor Dooley <[email protected]>
CC: Rob Herring <[email protected]>
CC: Krzysztof Kozlowski <[email protected]>
CC: Paul Walmsley <[email protected]>
CC: Palmer Dabbelt <[email protected]>
CC: Albert Ou <[email protected]>
CC: [email protected]
CC: [email protected]
CC: [email protected]
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index c91ab0e46648..92c31245d3fc 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -48,7 +48,7 @@ properties:
insensitive, letters in the riscv,isa string must be all
lowercase.
$ref: /schemas/types.yaml#/definitions/string
- pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
+ pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$
deprecated: true

riscv,isa-base:
--
2.39.2

2023-12-08 18:01:36

by Krzysztof Kozlowski

Subject: Re: [PATCH v1] dt-bindings: riscv: permit numbers in "riscv,isa"

On 08/12/2023 17:06, Conor Dooley wrote:
> From: Conor Dooley <[email protected]>
>
> There are some extensions that contain numbers, such as Zve32f, which
> are enabled by the "max" cpu type in QEMU.
>
> Signed-off-by: Conor Dooley <[email protected]>

That regex exceeded my capabilities long time ago, so just formality, FWIW:

Acked-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2024-01-11 14:52:58

by patchwork-bot+linux-riscv

Subject: Re: [PATCH v1] dt-bindings: riscv: permit numbers in "riscv,isa"

Hello:

This patch was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <[email protected]>:

On Fri, 8 Dec 2023 16:06:51 +0000 you wrote:
> From: Conor Dooley <[email protected]>
>
> There are some extensions that contain numbers, such as Zve32f, which
> are enabled by the "max" cpu type in QEMU.
>
> Signed-off-by: Conor Dooley <[email protected]>
>
> [...]

Here is the summary with links:
- [v1] dt-bindings: riscv: permit numbers in "riscv,isa"
https://git.kernel.org/riscv/c/baa04909d100

You are awesome, thank you!
--
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