In function create_timings_aligned, all the max is to use
dmc->min_tck->xxx, aligned with val dmc->timings->xxx.
But the dmc->timings->tFAW use dmc->min_tck->tXP?
Maybe this point is wrong parameter useing.
Signed-off-by: Bernard Zhao <[email protected]>
---
drivers/memory/samsung/exynos5422-dmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c
index 81a1b1d01683..22a43d662833 100644
--- a/drivers/memory/samsung/exynos5422-dmc.c
+++ b/drivers/memory/samsung/exynos5422-dmc.c
@@ -1091,7 +1091,7 @@ static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row,
/* power related timings */
val = dmc->timings->tFAW / clk_period_ps;
val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;
- val = max(val, dmc->min_tck->tXP);
+ val = max(val, dmc->min_tck->tFAW);
reg = &timing_power[0];
*reg_timing_power |= TIMING_VAL2REG(reg, val);
--
2.26.2
Hi Bernard,
On 5/7/20 12:45 PM, Bernard Zhao wrote:
> In function create_timings_aligned, all the max is to use
> dmc->min_tck->xxx, aligned with val dmc->timings->xxx.
> But the dmc->timings->tFAW use dmc->min_tck->tXP?
> Maybe this point is wrong parameter useing.
>
> Signed-off-by: Bernard Zhao <[email protected]>
> ---
> drivers/memory/samsung/exynos5422-dmc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c
> index 81a1b1d01683..22a43d662833 100644
> --- a/drivers/memory/samsung/exynos5422-dmc.c
> +++ b/drivers/memory/samsung/exynos5422-dmc.c
> @@ -1091,7 +1091,7 @@ static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row,
> /* power related timings */
> val = dmc->timings->tFAW / clk_period_ps;
> val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;
> - val = max(val, dmc->min_tck->tXP);
> + val = max(val, dmc->min_tck->tFAW);
> reg = &timing_power[0];
> *reg_timing_power |= TIMING_VAL2REG(reg, val);
>
>
Good catch! Indeed this should be a dmc->min_tck->tFAW used for
clamping.
It didn't show up in testing because the frequency values based on
which the 'clk_period_ps' are calculated are sane.
Check the dump below:
[ 5.458227] DMC: mem tFAW=25000, clk_period_ps=6060
[ 5.461743] DMC: tFAW=5, tXP=2 val=5
[ 5.465273] DMC: mem tFAW=25000, clk_period_ps=4854
[ 5.470101] DMC: tFAW=5, tXP=2 val=6
[ 5.473668] DMC: mem tFAW=25000, clk_period_ps=3636
[ 5.478507] DMC: tFAW=5, tXP=2 val=7
[ 5.482072] DMC: mem tFAW=25000, clk_period_ps=2421
[ 5.486951] DMC: tFAW=5, tXP=2 val=11
[ 5.490531] DMC: mem tFAW=25000, clk_period_ps=1841
[ 5.495439] DMC: tFAW=5, tXP=2 val=14
[ 5.499113] DMC: mem tFAW=25000, clk_period_ps=1579
[ 5.503877] DMC: tFAW=5, tXP=2 val=16
[ 5.507476] DMC: mem tFAW=25000, clk_period_ps=1373
[ 5.512368] DMC: tFAW=5, tXP=2 val=19
[ 5.515968] DMC: mem tFAW=25000, clk_period_ps=1212
[ 5.520826] DMC: tFAW=5, tXP=2 val=21
That's why in the existing configuration it does not harm
(the calculated 'val' is always >= 5) the board.
But I think this patch should be applied (after small changes in the
commit message).
@Krzysztof could you have a look on the commit message or take the
patch with small adjustment in the description, please?
I conditionally give (because of this description):
Reviewed-by: Lukasz Luba <[email protected]>
Thank you Bernard for reporting and fixing this.
Regards,
Lukasz
On Thu, May 07, 2020 at 04:42:46PM +0100, Lukasz Luba wrote:
> Hi Bernard,
>
>
> On 5/7/20 12:45 PM, Bernard Zhao wrote:
> > In function create_timings_aligned, all the max is to use
> > dmc->min_tck->xxx, aligned with val dmc->timings->xxx.
> > But the dmc->timings->tFAW use dmc->min_tck->tXP?
> > Maybe this point is wrong parameter useing.
> >
> > Signed-off-by: Bernard Zhao <[email protected]>
> > ---
> > drivers/memory/samsung/exynos5422-dmc.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c
> > index 81a1b1d01683..22a43d662833 100644
> > --- a/drivers/memory/samsung/exynos5422-dmc.c
> > +++ b/drivers/memory/samsung/exynos5422-dmc.c
> > @@ -1091,7 +1091,7 @@ static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row,
> > /* power related timings */
> > val = dmc->timings->tFAW / clk_period_ps;
> > val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;
> > - val = max(val, dmc->min_tck->tXP);
> > + val = max(val, dmc->min_tck->tFAW);
> > reg = &timing_power[0];
> > *reg_timing_power |= TIMING_VAL2REG(reg, val);
> >
>
> Good catch! Indeed this should be a dmc->min_tck->tFAW used for
> clamping.
>
> It didn't show up in testing because the frequency values based on
> which the 'clk_period_ps' are calculated are sane.
> Check the dump below:
>
> [ 5.458227] DMC: mem tFAW=25000, clk_period_ps=6060
> [ 5.461743] DMC: tFAW=5, tXP=2 val=5
> [ 5.465273] DMC: mem tFAW=25000, clk_period_ps=4854
> [ 5.470101] DMC: tFAW=5, tXP=2 val=6
> [ 5.473668] DMC: mem tFAW=25000, clk_period_ps=3636
> [ 5.478507] DMC: tFAW=5, tXP=2 val=7
> [ 5.482072] DMC: mem tFAW=25000, clk_period_ps=2421
> [ 5.486951] DMC: tFAW=5, tXP=2 val=11
> [ 5.490531] DMC: mem tFAW=25000, clk_period_ps=1841
> [ 5.495439] DMC: tFAW=5, tXP=2 val=14
> [ 5.499113] DMC: mem tFAW=25000, clk_period_ps=1579
> [ 5.503877] DMC: tFAW=5, tXP=2 val=16
> [ 5.507476] DMC: mem tFAW=25000, clk_period_ps=1373
> [ 5.512368] DMC: tFAW=5, tXP=2 val=19
> [ 5.515968] DMC: mem tFAW=25000, clk_period_ps=1212
> [ 5.520826] DMC: tFAW=5, tXP=2 val=21
>
> That's why in the existing configuration it does not harm
> (the calculated 'val' is always >= 5) the board.
>
> But I think this patch should be applied (after small changes in the
> commit message).
>
> @Krzysztof could you have a look on the commit message or take the
> patch with small adjustment in the description, please?
>
> I conditionally give (because of this description):
>
> Reviewed-by: Lukasz Luba <[email protected]>
Thanks for review.
I applied patch with CC-stable and adjusred commit msg.
Best regards,
Krzysztof