Bring up the SM6125 DPU now that all preliminary series (such as INTF
TE) have been merged (for me to test the hardware properly), and most
other conflicting work (barring ongoing catalog *improvements*) has made
its way in as well or is still being discussed.
The second part of the series complements that by immediately utilizing
this hardware in DT, and even enabling the MDSS/DSI nodes complete with
a 6.0" 1080x2520 panel for Sony's Seine PDX201 (Xperia 10 II).
The last patch ("sm6125-seine: Configure MDSS, DSI and panel") depends
on (an impending v2 of) my Sony panel collection series [1].
[1]: https://lore.kernel.org/linux-arm-msm/[email protected]/
---
Changes in v3:
- Drop status="disabled" from MDSS dt-bindings example;
- Use "nom" instead of "svs" OPP for dsi-phy PD, matching downstream;
- Add "retention" OPP to dispcc PD;
- Reword dsi-phy required-opps documentation;
- Rebased on latest -next and fixed conflicts in DT and DPU catalog;
- Link to v2: https://lore.kernel.org/r/[email protected]
Changes in v2:
- Moved dispcc DT clock reordering to the right patch (--fixup on the
wrong hash) (Dmitry, Konrad multiple times);
- Drop removal of GCC_DISP_AHB_CLK in dispcc bindings. While it is
unused in the current driver, it is likely used to ensure a guaranteed
probe order between GCC and DISPCC downstream, as well as currently
relying on the fact that GCC_DISP_AHB_CLK is CLK_IS_CRITICAL and never
turned off (Bjorn);
- Add GCC_DISP_GPLL0_DIV_CLK_SRC at the end of the dispcc clock list to
maintain some form of ABI stability (Krzysztof);
- Use SoC-prefix format for 14nm DSI PHY qcom,sm6125-dsi-phy-14nm
compatible (Dmitry, Krzysztof);
- Add patch to drop unused regulators from QCM2290 14nm DSI PHY (Konrad,
Dmitry);
- Reuse QCM2290 14nm DSI PHY config struct for SM6125 compatible
(Konrad);
- s/sde/mdss in pdx201.dts pinctrl node names and labels (Konrad);
- Use MX power domain in DSI PHY with SVS OPP (Dmitry);
- Use CX power domain with (already-existing) OPP table in DSI CTRL
(Konrad, Dmitry);
- Rebased on top of DPU catalog rework [1] by inlining macro
invocations, and validated by diffing stripped dpu_hw_catalog.o that
there are no unexpected changes;
- Unset min_llcc_ib because this platform has no LLCC (Konrad);
- Fix UBWC comment to mention "encoding" version (Dmitry);
- Reordered DT nodes to follow Konrad's requested sorting;
- Add power-domains and required-opps properties to dsi-phy-14nm.yaml;
- Link to v1: https://lore.kernel.org/r/[email protected]
The discussions and this list ran quite long, apologies if I missed or
mis-resolved anything in advance!
[1]: https://lore.kernel.org/linux-arm-msm/[email protected]/
---
Marijn Suijten (15):
drm/msm/dsi: Drop unused regulators from QCM2290 14nm DSI PHY config
arm64: dts: qcom: sm6125: Sort spmi_bus node numerically by reg
dt-bindings: clock: qcom,dispcc-sm6125: Require GCC PLL0 DIV clock
dt-bindings: clock: qcom,dispcc-sm6125: Allow power-domains property
dt-bindings: display/msm: dsi-controller-main: Document SM6125
dt-bindings: display/msm: sc7180-dpu: Describe SM6125
dt-bindings: display/msm: Add SM6125 MDSS
drm/msm/dpu: Add SM6125 support
drm/msm/mdss: Add SM6125 support
dt-bindings: msm: dsi-phy-14nm: Document SM6125 variant
drm/msm/dsi: Reuse QCM2290 14nm DSI PHY configuration for SM6125
arm64: dts: qcom: sm6125: Switch fixed xo_board clock to RPM XO clock
arm64: dts: qcom: sm6125: Add dispcc node
arm64: dts: qcom: sm6125: Add display hardware nodes
arm64: dts: qcom: sm6125-seine: Configure MDSS, DSI and panel
.../bindings/clock/qcom,dispcc-sm6125.yaml | 24 +-
.../bindings/display/msm/dsi-controller-main.yaml | 2 +
.../bindings/display/msm/dsi-phy-14nm.yaml | 11 +
.../bindings/display/msm/qcom,sc7180-dpu.yaml | 14 ++
.../bindings/display/msm/qcom,sm6125-mdss.yaml | 211 +++++++++++++++++
.../dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 59 +++++
arch/arm64/boot/dts/qcom/sm6125.dtsi | 255 +++++++++++++++++++--
.../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 236 +++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 7 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 2 -
drivers/gpu/drm/msm/msm_mdss.c | 8 +
14 files changed, 810 insertions(+), 23 deletions(-)
---
base-commit: 535ce75f2d80a47ce5407681014cd5a976646e38
change-id: 20230624-sm6125-dpu-aedc9637ee7b
Best regards,
--
Marijn Suijten <[email protected]>
This node has always resided in the wrong spot, making it somewhat
harder to contribute new node entries while maintaining proper sorting
around it. Move the node up to sit after hsusb_phy1 where it maintains
proper numerical sorting on the (first of its many) reg address
property.
Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125")
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Marijn Suijten <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 38 ++++++++++++++++++------------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 6937c7ebdb81..cfd0901d4555 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -684,6 +684,24 @@ hsusb_phy1: phy@1613000 {
status = "disabled";
};
+ spmi_bus: spmi@1c40000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x01c40000 0x1100>,
+ <0x01e00000 0x2000000>,
+ <0x03e00000 0x100000>,
+ <0x03f00000 0xa0000>,
+ <0x01c0a000 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
rpm_msg_ram: sram@45f0000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x045f0000 0x7000>;
@@ -1189,27 +1207,9 @@ sram@4690000 {
reg = <0x04690000 0x10000>;
};
- spmi_bus: spmi@1c40000 {
- compatible = "qcom,spmi-pmic-arb";
- reg = <0x01c40000 0x1100>,
- <0x01e00000 0x2000000>,
- <0x03e00000 0x100000>,
- <0x03f00000 0xa0000>,
- <0x01c0a000 0x26000>;
- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
- interrupt-names = "periph_irq";
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
- qcom,ee = <0>;
- qcom,channel = <0>;
- #address-cells = <2>;
- #size-cells = <0>;
- interrupt-controller;
- #interrupt-cells = <4>;
- };
-
apps_smmu: iommu@c600000 {
compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
- reg = <0xc600000 0x80000>;
+ reg = <0x0c600000 0x80000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
--
2.41.0
Enable MDSS and DSI, and configure the Samsung SOFEF01-M ams597ut01
6.0" 1080x2520 panel.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Marijn Suijten <[email protected]>
---
.../dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 59 ++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
index 82b0da5bb794..62c3e6d8147c 100644
--- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
+++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
@@ -179,6 +179,43 @@ &i2c3 {
/* Cirrus Logic CS35L41 boosted audio amplifier @ 40 */
};
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&pm6125_l18>;
+ status = "okay";
+
+ panel@0 {
+ compatible = "samsung,sofef01-m-ams597ut01";
+ reg = <0>;
+
+ reset-gpios = <&tlmm 90 GPIO_ACTIVE_LOW>;
+
+ vddio-supply = <&pm6125_l12>;
+
+ pinctrl-0 = <&mdss_dsi_active &mdss_te_active_sleep>;
+ pinctrl-1 = <&mdss_dsi_sleep &mdss_te_active_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&panel_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ status = "okay";
+};
+
&pm6125_adc {
pinctrl-names = "default";
pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm &rf_pa1_therm>;
@@ -469,6 +506,28 @@ vol_down_n: vol-down-n-state {
drive-strength = <2>;
bias-disable;
};
+
+ mdss_te_active_sleep: mdss-te-active-sleep-state {
+ pins = "gpio89";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ mdss_dsi_active: mdss-dsi-active-state {
+ pins = "gpio90";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ mdss_dsi_sleep: mdss-dsi-sleep-state {
+ pins = "gpio90";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
};
&usb3 {
--
2.41.0
Document availability of the 14nm DSI PHY on SM6125. Note that this
compatible uses the SoC-suffix variant, intead of postfixing an
arbitrary number without the sm/sdm portion. The PHY is not powered by
a vcca regulator like on most SoCs, but by the MX power domain that is
provided via the power-domains property and a single corresponding
required-opps.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Marijn Suijten <[email protected]>
---
.../devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
index a43e11d3b00d..2361da5f6736 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
@@ -19,6 +19,7 @@ properties:
- qcom,dsi-phy-14nm-2290
- qcom,dsi-phy-14nm-660
- qcom,dsi-phy-14nm-8953
+ - qcom,sm6125-dsi-phy-14nm
reg:
items:
@@ -35,6 +36,16 @@ properties:
vcca-supply:
description: Phandle to vcca regulator device node.
+ power-domains:
+ description:
+ A phandle and PM domain specifier for an optional power domain.
+ maxItems: 1
+
+ required-opps:
+ description:
+ A phandle to an OPP node describing the power domain's performance point.
+ maxItems: 1
+
required:
- compatible
- reg
--
2.41.0
Add definitions for the display hardware used on the Qualcomm SM6125
platform.
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Marijn Suijten <[email protected]>
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 236 +++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 7 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
4 files changed, 245 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
new file mode 100644
index 000000000000..5fddfcce6288
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
@@ -0,0 +1,236 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023 Marijn Suijten <[email protected]>. All rights reserved.
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_5_4_SM6125_H
+#define _DPU_5_4_SM6125_H
+
+static const struct dpu_caps sm6125_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x6,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = 2160,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
+static const struct dpu_ubwc_cfg sm6125_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_10,
+ .highest_bank_bit = 0x1,
+ .ubwc_swizzle = 0x1,
+};
+
+static const struct dpu_mdp_cfg sm6125_mdp = {
+ .name = "top_0",
+ .base = 0x0, .len = 0x45c,
+ .features = 0,
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ },
+};
+
+static const struct dpu_ctl_cfg sm6125_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x1800, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a00, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
+static const struct dpu_sspp_cfg sm6125_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x1f0,
+ .features = VIG_SM6125_MASK,
+ .sblk = &sm6125_vig_sblk_0,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x1f0,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_0,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x1f0,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_1,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA1,
+ },
+};
+
+static const struct dpu_lm_cfg sm6125_lm[] = {
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_QCM2290_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ .lm_pair = LM_1,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .features = MIXER_QCM2290_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .pingpong = PINGPONG_1,
+ .dspp = 0,
+ .lm_pair = LM_0,
+ },
+};
+
+static const struct dpu_dspp_cfg sm6125_dspp[] = {
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sdm845_dspp_sblk,
+ },
+};
+
+static const struct dpu_pingpong_cfg sm6125_pp[] = {
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x70000, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .merge_3d = 0,
+ .sblk = &sdm845_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x70800, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .merge_3d = 0,
+ .sblk = &sdm845_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ .intr_rdptr = -1,
+ },
+};
+
+static const struct dpu_intf_cfg sm6125_intf[] = {
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x6a000, .len = 0x280,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x6a800, .len = 0x2c0,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DSI,
+ .controller_id = 0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
+ },
+};
+
+static const struct dpu_perf_cfg sm6125_perf_data = {
+ .max_bw_low = 4100000,
+ .max_bw_high = 4100000,
+ .min_core_ib = 2400000,
+ .min_llcc_ib = 0, /* No LLCC on this SoC */
+ .min_dram_ib = 800000,
+ .min_prefill_lines = 24,
+ .danger_lut_tbl = {0xf, 0xffff, 0x0},
+ .safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sm8150_qos_linear),
+ .entries = sm8150_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+ .entries = sc7180_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ /* TODO: macrotile-qseed is different from macrotile */
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+static const struct dpu_mdss_version sm6125_mdss_ver = {
+ .core_major_ver = 5,
+ .core_minor_ver = 4,
+};
+
+const struct dpu_mdss_cfg dpu_sm6125_cfg = {
+ .mdss_ver = &sm6125_mdss_ver,
+ .caps = &sm6125_dpu_caps,
+ .ubwc = &sm6125_ubwc_cfg,
+ .mdp = &sm6125_mdp,
+ .ctl_count = ARRAY_SIZE(sm6125_ctl),
+ .ctl = sm6125_ctl,
+ .sspp_count = ARRAY_SIZE(sm6125_sspp),
+ .sspp = sm6125_sspp,
+ .mixer_count = ARRAY_SIZE(sm6125_lm),
+ .mixer = sm6125_lm,
+ .dspp_count = ARRAY_SIZE(sm6125_dspp),
+ .dspp = sm6125_dspp,
+ .pingpong_count = ARRAY_SIZE(sm6125_pp),
+ .pingpong = sm6125_pp,
+ .intf_count = ARRAY_SIZE(sm6125_intf),
+ .intf = sm6125_intf,
+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
+ .vbif = sdm845_vbif,
+ .perf = &sm6125_perf_data,
+ .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF0_INTR) | \
+ BIT(MDP_INTF1_INTR) | \
+ BIT(MDP_INTF1_TEAR_INTR),
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 4fdef908bde4..f2aa4d7afae4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -38,6 +38,9 @@
#define VIG_SC7180_MASK \
(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
+#define VIG_SM6125_MASK \
+ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
+
#define VIG_SC7180_MASK_SDMA \
(VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
@@ -380,6 +383,9 @@ static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
_VIG_SBLK(2, DPU_SSPP_SCALER_QSEED4);
+static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 =
+ _VIG_SBLK(3, DPU_SSPP_SCALER_QSEED3LITE);
+
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
_VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4);
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
@@ -718,6 +724,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
#include "catalog/dpu_5_0_sm8150.h"
#include "catalog/dpu_5_1_sc8180x.h"
+#include "catalog/dpu_5_4_sm6125.h"
#include "catalog/dpu_6_0_sm8250.h"
#include "catalog/dpu_6_2_sc7180.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 8d18e535472b..ca2d6d3ed4ac 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -873,6 +873,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
+extern const struct dpu_mdss_cfg dpu_sm6125_cfg;
extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 34a6f67932d3..7ba9428e943e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1282,6 +1282,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
+ { .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },
{ .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
{ .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
--
2.41.0
On 19/07/2023 00:24, Marijn Suijten wrote:
> This node has always resided in the wrong spot, making it somewhat
> harder to contribute new node entries while maintaining proper sorting
> around it. Move the node up to sit after hsusb_phy1 where it maintains
> proper numerical sorting on the (first of its many) reg address
> property.
>
> Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125")
> Reviewed-by: Konrad Dybcio <[email protected]>
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm6125.dtsi | 38 ++++++++++++++++++------------------
> 1 file changed, 19 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> index 6937c7ebdb81..cfd0901d4555 100644
> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> @@ -684,6 +684,24 @@ hsusb_phy1: phy@1613000 {
> status = "disabled";
> };
>
> + spmi_bus: spmi@1c40000 {
> + compatible = "qcom,spmi-pmic-arb";
> + reg = <0x01c40000 0x1100>,
> + <0x01e00000 0x2000000>,
> + <0x03e00000 0x100000>,
> + <0x03f00000 0xa0000>,
> + <0x01c0a000 0x26000>;
> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> + interrupt-names = "periph_irq";
> + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,ee = <0>;
> + qcom,channel = <0>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + interrupt-controller;
> + #interrupt-cells = <4>;
> + };
> +
> rpm_msg_ram: sram@45f0000 {
> compatible = "qcom,rpm-msg-ram";
> reg = <0x045f0000 0x7000>;
> @@ -1189,27 +1207,9 @@ sram@4690000 {
> reg = <0x04690000 0x10000>;
> };
>
> - spmi_bus: spmi@1c40000 {
> - compatible = "qcom,spmi-pmic-arb";
> - reg = <0x01c40000 0x1100>,
> - <0x01e00000 0x2000000>,
> - <0x03e00000 0x100000>,
> - <0x03f00000 0xa0000>,
> - <0x01c0a000 0x26000>;
> - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> - interrupt-names = "periph_irq";
> - interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
> - qcom,ee = <0>;
> - qcom,channel = <0>;
> - #address-cells = <2>;
> - #size-cells = <0>;
> - interrupt-controller;
> - #interrupt-cells = <4>;
> - };
> -
> apps_smmu: iommu@c600000 {
> compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
> - reg = <0xc600000 0x80000>;
> + reg = <0x0c600000 0x80000>;
Irrelevant, please split.
> interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
>
--
With best wishes
Dmitry
On 2023-07-19 01:02:56, Dmitry Baryshkov wrote:
> On 19/07/2023 00:24, Marijn Suijten wrote:
> > This node has always resided in the wrong spot, making it somewhat
> > harder to contribute new node entries while maintaining proper sorting
> > around it. Move the node up to sit after hsusb_phy1 where it maintains
> > proper numerical sorting on the (first of its many) reg address
> > property.
> >
> > Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125")
> > Reviewed-by: Konrad Dybcio <[email protected]>
> > Signed-off-by: Marijn Suijten <[email protected]>
> > ---
> > arch/arm64/boot/dts/qcom/sm6125.dtsi | 38 ++++++++++++++++++------------------
> > 1 file changed, 19 insertions(+), 19 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > index 6937c7ebdb81..cfd0901d4555 100644
> > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > @@ -684,6 +684,24 @@ hsusb_phy1: phy@1613000 {
> > status = "disabled";
> > };
> >
> > + spmi_bus: spmi@1c40000 {
> > + compatible = "qcom,spmi-pmic-arb";
> > + reg = <0x01c40000 0x1100>,
> > + <0x01e00000 0x2000000>,
> > + <0x03e00000 0x100000>,
> > + <0x03f00000 0xa0000>,
> > + <0x01c0a000 0x26000>;
> > + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> > + interrupt-names = "periph_irq";
> > + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
> > + qcom,ee = <0>;
> > + qcom,channel = <0>;
> > + #address-cells = <2>;
> > + #size-cells = <0>;
> > + interrupt-controller;
> > + #interrupt-cells = <4>;
> > + };
> > +
> > rpm_msg_ram: sram@45f0000 {
> > compatible = "qcom,rpm-msg-ram";
> > reg = <0x045f0000 0x7000>;
> > @@ -1189,27 +1207,9 @@ sram@4690000 {
> > reg = <0x04690000 0x10000>;
> > };
> >
> > - spmi_bus: spmi@1c40000 {
> > - compatible = "qcom,spmi-pmic-arb";
> > - reg = <0x01c40000 0x1100>,
> > - <0x01e00000 0x2000000>,
> > - <0x03e00000 0x100000>,
> > - <0x03f00000 0xa0000>,
> > - <0x01c0a000 0x26000>;
> > - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> > - interrupt-names = "periph_irq";
> > - interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
> > - qcom,ee = <0>;
> > - qcom,channel = <0>;
> > - #address-cells = <2>;
> > - #size-cells = <0>;
> > - interrupt-controller;
> > - #interrupt-cells = <4>;
> > - };
> > -
> > apps_smmu: iommu@c600000 {
> > compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
> > - reg = <0xc600000 0x80000>;
> > + reg = <0x0c600000 0x80000>;
>
> Irrelevant, please split.
This was already here in v1, and it is what likely contributed to the
sorting mismatch in the first place.
But will split it and send a v4 for just this...
- Marijn
Il 19/07/23 23:54, Marijn Suijten ha scritto:
> On 2023-07-19 01:02:56, Dmitry Baryshkov wrote:
>> On 19/07/2023 00:24, Marijn Suijten wrote:
>>> This node has always resided in the wrong spot, making it somewhat
>>> harder to contribute new node entries while maintaining proper sorting
>>> around it. Move the node up to sit after hsusb_phy1 where it maintains
>>> proper numerical sorting on the (first of its many) reg address
>>> property.
>>>
>>> Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125")
>>> Reviewed-by: Konrad Dybcio <[email protected]>
>>> Signed-off-by: Marijn Suijten <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/qcom/sm6125.dtsi | 38 ++++++++++++++++++------------------
>>> 1 file changed, 19 insertions(+), 19 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
>>> index 6937c7ebdb81..cfd0901d4555 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
>>> @@ -684,6 +684,24 @@ hsusb_phy1: phy@1613000 {
>>> status = "disabled";
>>> };
>>>
>>> + spmi_bus: spmi@1c40000 {
>>> + compatible = "qcom,spmi-pmic-arb";
>>> + reg = <0x01c40000 0x1100>,
>>> + <0x01e00000 0x2000000>,
>>> + <0x03e00000 0x100000>,
>>> + <0x03f00000 0xa0000>,
>>> + <0x01c0a000 0x26000>;
>>> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
>>> + interrupt-names = "periph_irq";
>>> + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
>>> + qcom,ee = <0>;
>>> + qcom,channel = <0>;
>>> + #address-cells = <2>;
>>> + #size-cells = <0>;
>>> + interrupt-controller;
>>> + #interrupt-cells = <4>;
>>> + };
>>> +
>>> rpm_msg_ram: sram@45f0000 {
>>> compatible = "qcom,rpm-msg-ram";
>>> reg = <0x045f0000 0x7000>;
>>> @@ -1189,27 +1207,9 @@ sram@4690000 {
>>> reg = <0x04690000 0x10000>;
>>> };
>>>
>>> - spmi_bus: spmi@1c40000 {
>>> - compatible = "qcom,spmi-pmic-arb";
>>> - reg = <0x01c40000 0x1100>,
>>> - <0x01e00000 0x2000000>,
>>> - <0x03e00000 0x100000>,
>>> - <0x03f00000 0xa0000>,
>>> - <0x01c0a000 0x26000>;
>>> - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
>>> - interrupt-names = "periph_irq";
>>> - interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
>>> - qcom,ee = <0>;
>>> - qcom,channel = <0>;
>>> - #address-cells = <2>;
>>> - #size-cells = <0>;
>>> - interrupt-controller;
>>> - #interrupt-cells = <4>;
>>> - };
>>> -
>>> apps_smmu: iommu@c600000 {
>>> compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
>>> - reg = <0xc600000 0x80000>;
>>> + reg = <0x0c600000 0x80000>;
>>
>> Irrelevant, please split.
>
> This was already here in v1, and it is what likely contributed to the
> sorting mismatch in the first place.
>
> But will split it and send a v4 for just this...
>
I agree in that it is irrelevant, but anyway, for the next time: you should at
least mention "the other change" in your commit message ;-)
Also, remember that this commit has a Fixes tag........ :-)
Cheers,
Angelo