2018-03-09 14:40:57

by Harry Pan

[permalink] [raw]
Subject: [PATCH 1/3] powercap: intel_rapl: Add support for Cannon Lake

Cannon Lake microarchitecture is similar to Kaby Lake in terms of
RAPL, this patch enables CNL RAPL support.

Signed-off-by: Harry Pan <[email protected]>
---
drivers/powercap/intel_rapl.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/powercap/intel_rapl.c b/drivers/powercap/intel_rapl.c
index 35636e1d8a3d..295d8dcba48c 100644
--- a/drivers/powercap/intel_rapl.c
+++ b/drivers/powercap/intel_rapl.c
@@ -1162,6 +1162,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
RAPL_CPU(INTEL_FAM6_SKYLAKE_X, rapl_defaults_hsw_server),
RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE, rapl_defaults_core),
RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP, rapl_defaults_core),
+ RAPL_CPU(INTEL_FAM6_CANNONLAKE_MOBILE, rapl_defaults_core),

RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1, rapl_defaults_byt),
RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT, rapl_defaults_cht),
--
2.13.5



2018-03-09 14:39:41

by Harry Pan

[permalink] [raw]
Subject: [PATCH 3/3] perf/x86/intel: Enable C-state residency events for Cannon Lake

Cannon Lake supports C1/C3/C6/C7, PC2/PC3/PC6/PC7/PC8/PC9/PC10
state residency counters, this patch enables those counters.

The MSR information is based on Intel Software Developers' Manual,
Vol. 4, Order No. 335592.

Signed-off-by: Harry Pan <[email protected]>
---
arch/x86/events/intel/cstate.c | 44 +++++++++++++++++++++++++++++-------------
1 file changed, 31 insertions(+), 13 deletions(-)

diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 72db0664a53d..9aca448bb8e6 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -40,50 +40,51 @@
* Model specific counters:
* MSR_CORE_C1_RES: CORE C1 Residency Counter
* perf code: 0x00
- * Available model: SLM,AMT,GLM
+ * Available model: SLM,AMT,GLM,CNL
* Scope: Core (each processor core has a MSR)
* MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
* perf code: 0x01
- * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM
+ * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
+ CNL
* Scope: Core
* MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
* perf code: 0x02
- * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- * SKL,KNL,GLM
+ * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
+ * SKL,KNL,GLM,CNL
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
- * Available model: SNB,IVB,HSW,BDW,SKL
+ * Available model: SNB,IVB,HSW,BDW,SKL,CNL
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
- * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM
+ * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
- * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL
- * GLM
+ * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
+ * GLM,CNL
* Scope: Package (physical package)
* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- * SKL,KNL,GLM
+ * SKL,KNL,GLM,CNL
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
- * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL
+ * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL
* Scope: Package (physical package)
* MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
* perf code: 0x04
- * Available model: HSW ULT only
+ * Available model: HSW ULT,CNL
* Scope: Package (physical package)
* MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
* perf code: 0x05
- * Available model: HSW ULT only
+ * Available model: HSW ULT,CNL
* Scope: Package (physical package)
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
* perf code: 0x06
- * Available model: HSW ULT, GLM
+ * Available model: HSW ULT,GLM,CNL
* Scope: Package (physical package)
*
*/
@@ -486,6 +487,21 @@ static const struct cstate_model hswult_cstates __initconst = {
BIT(PERF_CSTATE_PKG_C10_RES),
};

+static const struct cstate_model cnl_cstates __initconst = {
+ .core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
+ BIT(PERF_CSTATE_CORE_C3_RES) |
+ BIT(PERF_CSTATE_CORE_C6_RES) |
+ BIT(PERF_CSTATE_CORE_C7_RES),
+
+ .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
+ BIT(PERF_CSTATE_PKG_C3_RES) |
+ BIT(PERF_CSTATE_PKG_C6_RES) |
+ BIT(PERF_CSTATE_PKG_C7_RES) |
+ BIT(PERF_CSTATE_PKG_C8_RES) |
+ BIT(PERF_CSTATE_PKG_C9_RES) |
+ BIT(PERF_CSTATE_PKG_C10_RES),
+};
+
static const struct cstate_model slm_cstates __initconst = {
.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
BIT(PERF_CSTATE_CORE_C6_RES),
@@ -557,6 +573,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE, snb_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates),

+ X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_MOBILE, cnl_cstates),
+
X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),

--
2.13.5


2018-03-09 14:40:04

by Harry Pan

[permalink] [raw]
Subject: [PATCH 2/3] perf/x86/intel: Add Cannon Lake support of RAPL profiling

This patch enables RAPL counters (energy consumption counters)
support for Cannon Lake processors.

ESU and power domains refer to Intel Software Developers' Manual,
Vol. 4, Order No. 335592.

Usage example:

$ perf list
$ perf stat -a -e power/energy-cores/,power/energy-pkg/ sleep 10

Signed-off-by: Harry Pan <[email protected]>
---
arch/x86/events/intel/rapl.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c
index a2efb490f743..32f3e9423e99 100644
--- a/arch/x86/events/intel/rapl.c
+++ b/arch/x86/events/intel/rapl.c
@@ -774,6 +774,8 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = {
X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_MOBILE, skl_rapl_init),
X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_rapl_init),

+ X86_RAPL_MODEL_MATCH(INTEL_FAM6_CANNONLAKE_MOBILE, skl_rapl_init),
+
X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init),
X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_DENVERTON, hsw_rapl_init),

--
2.13.5


2018-03-20 02:01:50

by Benson Leung

[permalink] [raw]
Subject: Re: [PATCH 2/3] perf/x86/intel: Add Cannon Lake support of RAPL profiling

Hi Harry,

On 03/09/2018 04:15 AM, Harry Pan wrote:
> This patch enables RAPL counters (energy consumption counters)
> support for Cannon Lake processors.
>
> ESU and power domains refer to Intel Software Developers' Manual,
> Vol. 4, Order No. 335592.
>
> Usage example:
>
> $ perf list
> $ perf stat -a -e power/energy-cores/,power/energy-pkg/ sleep 10
>
> Signed-off-by: Harry Pan <[email protected]>

Reviewed-by: Benson Leung <[email protected]>

> ---
> arch/x86/events/intel/rapl.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c
> index a2efb490f743..32f3e9423e99 100644
> --- a/arch/x86/events/intel/rapl.c
> +++ b/arch/x86/events/intel/rapl.c
> @@ -774,6 +774,8 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = {
> X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_MOBILE, skl_rapl_init),
> X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_rapl_init),
>
> + X86_RAPL_MODEL_MATCH(INTEL_FAM6_CANNONLAKE_MOBILE, skl_rapl_init),
> +
> X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init),
> X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_DENVERTON, hsw_rapl_init),
>
>

Thanks,
--
Benson Leung
Staff Software Engineer
Chrome OS Kernel
Google Inc.
[email protected]
Chromium OS Project
[email protected]

Attachments:
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2018-03-20 02:02:04

by Benson Leung

[permalink] [raw]
Subject: Re: [PATCH 3/3] perf/x86/intel: Enable C-state residency events for Cannon Lake

Hi Harry,

On 03/09/2018 04:15 AM, Harry Pan wrote:
> Cannon Lake supports C1/C3/C6/C7, PC2/PC3/PC6/PC7/PC8/PC9/PC10
> state residency counters, this patch enables those counters.
>
> The MSR information is based on Intel Software Developers' Manual,
> Vol. 4, Order No. 335592.
>
> Signed-off-by: Harry Pan <[email protected]>

Reviewed-by: Benson Leung <[email protected]>

> ---
> arch/x86/events/intel/cstate.c | 44 +++++++++++++++++++++++++++++-------------
> 1 file changed, 31 insertions(+), 13 deletions(-)
>
> diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
> index 72db0664a53d..9aca448bb8e6 100644
> --- a/arch/x86/events/intel/cstate.c
> +++ b/arch/x86/events/intel/cstate.c
> @@ -40,50 +40,51 @@
> * Model specific counters:
> * MSR_CORE_C1_RES: CORE C1 Residency Counter
> * perf code: 0x00
> - * Available model: SLM,AMT,GLM
> + * Available model: SLM,AMT,GLM,CNL
> * Scope: Core (each processor core has a MSR)
> * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
> * perf code: 0x01
> - * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM
> + * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
> + CNL
> * Scope: Core
> * MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
> * perf code: 0x02
> - * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
> - * SKL,KNL,GLM
> + * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
> + * SKL,KNL,GLM,CNL
> * Scope: Core
> * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
> * perf code: 0x03
> - * Available model: SNB,IVB,HSW,BDW,SKL
> + * Available model: SNB,IVB,HSW,BDW,SKL,CNL
> * Scope: Core
> * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
> * perf code: 0x00
> - * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM
> + * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL
> * Scope: Package (physical package)
> * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
> * perf code: 0x01
> - * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL
> - * GLM
> + * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
> + * GLM,CNL
> * Scope: Package (physical package)
> * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
> * perf code: 0x02
> * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
> - * SKL,KNL,GLM
> + * SKL,KNL,GLM,CNL
> * Scope: Package (physical package)
> * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
> * perf code: 0x03
> - * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL
> + * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL
> * Scope: Package (physical package)
> * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
> * perf code: 0x04
> - * Available model: HSW ULT only
> + * Available model: HSW ULT,CNL
> * Scope: Package (physical package)
> * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
> * perf code: 0x05
> - * Available model: HSW ULT only
> + * Available model: HSW ULT,CNL
> * Scope: Package (physical package)
> * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
> * perf code: 0x06
> - * Available model: HSW ULT, GLM
> + * Available model: HSW ULT,GLM,CNL
> * Scope: Package (physical package)
> *
> */
> @@ -486,6 +487,21 @@ static const struct cstate_model hswult_cstates __initconst = {
> BIT(PERF_CSTATE_PKG_C10_RES),
> };
>
> +static const struct cstate_model cnl_cstates __initconst = {
> + .core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
> + BIT(PERF_CSTATE_CORE_C3_RES) |
> + BIT(PERF_CSTATE_CORE_C6_RES) |
> + BIT(PERF_CSTATE_CORE_C7_RES),
> +
> + .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
> + BIT(PERF_CSTATE_PKG_C3_RES) |
> + BIT(PERF_CSTATE_PKG_C6_RES) |
> + BIT(PERF_CSTATE_PKG_C7_RES) |
> + BIT(PERF_CSTATE_PKG_C8_RES) |
> + BIT(PERF_CSTATE_PKG_C9_RES) |
> + BIT(PERF_CSTATE_PKG_C10_RES),
> +};
> +
> static const struct cstate_model slm_cstates __initconst = {
> .core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
> BIT(PERF_CSTATE_CORE_C6_RES),
> @@ -557,6 +573,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
> X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE, snb_cstates),
> X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates),
>
> + X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_MOBILE, cnl_cstates),
> +
> X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),
> X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),
>
>

Thank you!
--
Benson Leung
Staff Software Engineer
Chrome OS Kernel
Google Inc.
[email protected]
Chromium OS Project
[email protected]

Attachments:
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2018-03-20 02:02:10

by Puthikorn Voravootivat

[permalink] [raw]
Subject: Re: [PATCH 2/3] perf/x86/intel: Add Cannon Lake support of RAPL profiling

On Mon, Mar 19, 2018 at 4:05 PM Benson Leung <[email protected]> wrote:

> Hi Harry,

> On 03/09/2018 04:15 AM, Harry Pan wrote:
> > This patch enables RAPL counters (energy consumption counters)
> > support for Cannon Lake processors.
> >
> > ESU and power domains refer to Intel Software Developers' Manual,
> > Vol. 4, Order No. 335592.
> >
> > Usage example:
> >
> > $ perf list
> > $ perf stat -a -e power/energy-cores/,power/energy-pkg/ sleep 10
> >
> > Signed-off-by: Harry Pan <[email protected]>

> Reviewed-by: Benson Leung <[email protected]>

Tested-by: Puthikorn Voravootivat <[email protected]>


> > ---
> > arch/x86/events/intel/rapl.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c
> > index a2efb490f743..32f3e9423e99 100644
> > --- a/arch/x86/events/intel/rapl.c
> > +++ b/arch/x86/events/intel/rapl.c
> > @@ -774,6 +774,8 @@ static const struct x86_cpu_id rapl_cpu_match[]
__initconst = {
> > X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_MOBILE, skl_rapl_init),
> > X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_rapl_init),
> >
> > + X86_RAPL_MODEL_MATCH(INTEL_FAM6_CANNONLAKE_MOBILE,
skl_rapl_init),
> > +
> > X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init),
> > X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_DENVERTON, hsw_rapl_init),
> >
> >

> Thanks,
> --
> Benson Leung
> Staff Software Engineer
> Chrome OS Kernel
> Google Inc.
> [email protected]
> Chromium OS Project
> [email protected]

2018-03-20 02:02:16

by Benson Leung

[permalink] [raw]
Subject: Re: [PATCH 1/3] powercap: intel_rapl: Add support for Cannon Lake

[email protected]

On 03/09/2018 04:15 AM, Harry Pan wrote:
> Cannon Lake microarchitecture is similar to Kaby Lake in terms of
> RAPL, this patch enables CNL RAPL support.
>
> Signed-off-by: Harry Pan <[email protected]>
> ---
> drivers/powercap/intel_rapl.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/powercap/intel_rapl.c b/drivers/powercap/intel_rapl.c
> index 35636e1d8a3d..295d8dcba48c 100644
> --- a/drivers/powercap/intel_rapl.c
> +++ b/drivers/powercap/intel_rapl.c
> @@ -1162,6 +1162,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
> RAPL_CPU(INTEL_FAM6_SKYLAKE_X, rapl_defaults_hsw_server),
> RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE, rapl_defaults_core),
> RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP, rapl_defaults_core),
> + RAPL_CPU(INTEL_FAM6_CANNONLAKE_MOBILE, rapl_defaults_core),
>
> RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1, rapl_defaults_byt),
> RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT, rapl_defaults_cht),
>

--
Benson Leung
Staff Software Engineer
Chrome OS Kernel
Google Inc.
[email protected]
Chromium OS Project
[email protected]

Attachments:
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2018-03-20 02:02:25

by Puthikorn Voravootivat

[permalink] [raw]
Subject: Re: [PATCH 1/3] powercap: intel_rapl: Add support for Cannon Lake

On Mon, Mar 19, 2018 at 4:14 PM Benson Leung <[email protected]> wrote:

> [email protected]

> On 03/09/2018 04:15 AM, Harry Pan wrote:
> > Cannon Lake microarchitecture is similar to Kaby Lake in terms of
> > RAPL, this patch enables CNL RAPL support.
> >
> > Signed-off-by: Harry Pan <[email protected]>
Tested-by: Puthikorn Voravootivat <[email protected]>
> > ---
> > drivers/powercap/intel_rapl.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/powercap/intel_rapl.c
b/drivers/powercap/intel_rapl.c
> > index 35636e1d8a3d..295d8dcba48c 100644
> > --- a/drivers/powercap/intel_rapl.c
> > +++ b/drivers/powercap/intel_rapl.c
> > @@ -1162,6 +1162,7 @@ static const struct x86_cpu_id rapl_ids[]
__initconst = {
> > RAPL_CPU(INTEL_FAM6_SKYLAKE_X, rapl_defaults_hsw_server),
> > RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE, rapl_defaults_core),
> > RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP, rapl_defaults_core),
> > + RAPL_CPU(INTEL_FAM6_CANNONLAKE_MOBILE, rapl_defaults_core),
> >
> > RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1, rapl_defaults_byt),
> > RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT, rapl_defaults_cht),
> >

> --
> Benson Leung
> Staff Software Engineer
> Chrome OS Kernel
> Google Inc.
> [email protected]
> Chromium OS Project
> [email protected]

2018-03-20 02:03:01

by Benson Leung

[permalink] [raw]
Subject: Re: [PATCH 1/3] powercap: intel_rapl: Add support for Cannon Lake

Hi Harry,

On 03/09/2018 04:15 AM, Harry Pan wrote:
> Cannon Lake microarchitecture is similar to Kaby Lake in terms of
> RAPL, this patch enables CNL RAPL support.
>
> Signed-off-by: Harry Pan <[email protected]>

Reviewed-by: Benson Leung <[email protected]>

> ---
> drivers/powercap/intel_rapl.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/powercap/intel_rapl.c b/drivers/powercap/intel_rapl.c
> index 35636e1d8a3d..295d8dcba48c 100644
> --- a/drivers/powercap/intel_rapl.c
> +++ b/drivers/powercap/intel_rapl.c
> @@ -1162,6 +1162,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
> RAPL_CPU(INTEL_FAM6_SKYLAKE_X, rapl_defaults_hsw_server),
> RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE, rapl_defaults_core),
> RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP, rapl_defaults_core),
> + RAPL_CPU(INTEL_FAM6_CANNONLAKE_MOBILE, rapl_defaults_core),
>
> RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1, rapl_defaults_byt),
> RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT, rapl_defaults_cht),
>

Thanks!
--
Benson Leung
Staff Software Engineer
Chrome OS Kernel
Google Inc.
[email protected]
Chromium OS Project
[email protected]

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2018-03-20 02:03:39

by Puthikorn Voravootivat

[permalink] [raw]
Subject: Re: [PATCH 3/3] perf/x86/intel: Enable C-state residency events for Cannon Lake

On Mon, Mar 19, 2018 at 4:09 PM Benson Leung <[email protected]> wrote:

> Hi Harry,

> On 03/09/2018 04:15 AM, Harry Pan wrote:
> > Cannon Lake supports C1/C3/C6/C7, PC2/PC3/PC6/PC7/PC8/PC9/PC10
> > state residency counters, this patch enables those counters.
> >
> > The MSR information is based on Intel Software Developers' Manual,
> > Vol. 4, Order No. 335592.
> >
> > Signed-off-by: Harry Pan <[email protected]>

> Reviewed-by: Benson Leung <[email protected]>

Tested-by: Puthikorn Voravootivat <[email protected]>

> > ---
> > arch/x86/events/intel/cstate.c | 44
+++++++++++++++++++++++++++++-------------
> > 1 file changed, 31 insertions(+), 13 deletions(-)
> >
> > diff --git a/arch/x86/events/intel/cstate.c
b/arch/x86/events/intel/cstate.c
> > index 72db0664a53d..9aca448bb8e6 100644
> > --- a/arch/x86/events/intel/cstate.c
> > +++ b/arch/x86/events/intel/cstate.c
> > @@ -40,50 +40,51 @@
> > * Model specific counters:
> > * MSR_CORE_C1_RES: CORE C1 Residency Counter
> > * perf code: 0x00
> > - * Available model: SLM,AMT,GLM
> > + * Available model: SLM,AMT,GLM,CNL
> > * Scope: Core (each processor core has a MSR)
> > * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
> > * perf code: 0x01
> > - * Available model:
NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM
> > + * Available model:
NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
> > + CNL
> > * Scope: Core
> > * MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
> > * perf code: 0x02
> > - * Available model:
SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
> > - * SKL,KNL,GLM
> > + * Available model:
SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
> > + * SKL,KNL,GLM,CNL
> > * Scope: Core
> > * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
> > * perf code: 0x03
> > - * Available model: SNB,IVB,HSW,BDW,SKL
> > + * Available model: SNB,IVB,HSW,BDW,SKL,CNL
> > * Scope: Core
> > * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
> > * perf code: 0x00
> > - * Available model:
SNB,IVB,HSW,BDW,SKL,KNL,GLM
> > + * Available model:
SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL
> > * Scope: Package (physical package)
> > * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
> > * perf code: 0x01
> > - * Available model:
NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL
> > - * GLM
> > + * Available model:
NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
> > + * GLM,CNL
> > * Scope: Package (physical package)
> > * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
> > * perf code: 0x02
> > * Available model:
SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
> > - * SKL,KNL,GLM
> > + * SKL,KNL,GLM,CNL
> > * Scope: Package (physical package)
> > * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
> > * perf code: 0x03
> > - * Available model:
NHM,WSM,SNB,IVB,HSW,BDW,SKL
> > + * Available model:
NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL
> > * Scope: Package (physical package)
> > * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
> > * perf code: 0x04
> > - * Available model: HSW ULT only
> > + * Available model: HSW ULT,CNL
> > * Scope: Package (physical package)
> > * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
> > * perf code: 0x05
> > - * Available model: HSW ULT only
> > + * Available model: HSW ULT,CNL
> > * Scope: Package (physical package)
> > * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
> > * perf code: 0x06
> > - * Available model: HSW ULT, GLM
> > + * Available model: HSW ULT,GLM,CNL
> > * Scope: Package (physical package)
> > *
> > */
> > @@ -486,6 +487,21 @@ static const struct cstate_model hswult_cstates
__initconst = {
> > BIT(PERF_CSTATE_PKG_C10_RES),
> > };
> >
> > +static const struct cstate_model cnl_cstates __initconst = {
> > + .core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
> > + BIT(PERF_CSTATE_CORE_C3_RES) |
> > + BIT(PERF_CSTATE_CORE_C6_RES) |
> > + BIT(PERF_CSTATE_CORE_C7_RES),
> > +
> > + .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
> > + BIT(PERF_CSTATE_PKG_C3_RES) |
> > + BIT(PERF_CSTATE_PKG_C6_RES) |
> > + BIT(PERF_CSTATE_PKG_C7_RES) |
> > + BIT(PERF_CSTATE_PKG_C8_RES) |
> > + BIT(PERF_CSTATE_PKG_C9_RES) |
> > + BIT(PERF_CSTATE_PKG_C10_RES),
> > +};
> > +
> > static const struct cstate_model slm_cstates __initconst = {
> > .core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
> > BIT(PERF_CSTATE_CORE_C6_RES),
> > @@ -557,6 +573,8 @@ static const struct x86_cpu_id
intel_cstates_match[] __initconst = {
> > X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE, snb_cstates),
> > X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates),
> >
> > + X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_MOBILE, cnl_cstates),
> > +
> > X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),
> > X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),
> >
> >

> Thank you!
> --
> Benson Leung
> Staff Software Engineer
> Chrome OS Kernel
> Google Inc.
> [email protected]
> Chromium OS Project
> [email protected]

2018-03-20 10:00:04

by Rafael J. Wysocki

[permalink] [raw]
Subject: Re: [PATCH 1/3] powercap: intel_rapl: Add support for Cannon Lake

On Fri, Mar 9, 2018 at 1:15 PM, Harry Pan <[email protected]> wrote:
> Cannon Lake microarchitecture is similar to Kaby Lake in terms of
> RAPL, this patch enables CNL RAPL support.
>
> Signed-off-by: Harry Pan <[email protected]>

I have applied an analogous patch from Joe Konno that was posted earlier.

Thanks!


> ---
> drivers/powercap/intel_rapl.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/powercap/intel_rapl.c b/drivers/powercap/intel_rapl.c
> index 35636e1d8a3d..295d8dcba48c 100644
> --- a/drivers/powercap/intel_rapl.c
> +++ b/drivers/powercap/intel_rapl.c
> @@ -1162,6 +1162,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
> RAPL_CPU(INTEL_FAM6_SKYLAKE_X, rapl_defaults_hsw_server),
> RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE, rapl_defaults_core),
> RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP, rapl_defaults_core),
> + RAPL_CPU(INTEL_FAM6_CANNONLAKE_MOBILE, rapl_defaults_core),
>
> RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1, rapl_defaults_byt),
> RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT, rapl_defaults_cht),
> --
> 2.13.5
>

Subject: [tip:perf/core] perf/x86/intel: Add Cannon Lake support for RAPL profiling

Commit-ID: 490d03e83da2a5e9d7db84b1ec30a9c95415787e
Gitweb: https://git.kernel.org/tip/490d03e83da2a5e9d7db84b1ec30a9c95415787e
Author: Harry Pan <[email protected]>
AuthorDate: Fri, 9 Mar 2018 20:15:47 +0800
Committer: Ingo Molnar <[email protected]>
CommitDate: Sat, 31 Mar 2018 11:28:36 +0200

perf/x86/intel: Add Cannon Lake support for RAPL profiling

This patch enables RAPL counters (energy consumption counters)
support for Cannon Lake processors.

( ESU and power domains refer to Intel Software Developers' Manual,
Vol. 4, Order No. 335592. )

Usage example:

$ perf list
$ perf stat -a -e power/energy-cores/,power/energy-pkg/ sleep 10

Tested-by: Puthikorn Voravootivat <[email protected]>
Signed-off-by: Harry Pan <[email protected]>
Reviewed-by: Benson Leung <[email protected]>
Cc: Alexander Shishkin <[email protected]>
Cc: Arnaldo Carvalho de Melo <[email protected]>
Cc: Jiri Olsa <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Stephane Eranian <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Vince Weaver <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
---
arch/x86/events/intel/rapl.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c
index a2efb490f743..32f3e9423e99 100644
--- a/arch/x86/events/intel/rapl.c
+++ b/arch/x86/events/intel/rapl.c
@@ -774,6 +774,8 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = {
X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_MOBILE, skl_rapl_init),
X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_rapl_init),

+ X86_RAPL_MODEL_MATCH(INTEL_FAM6_CANNONLAKE_MOBILE, skl_rapl_init),
+
X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init),
X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_DENVERTON, hsw_rapl_init),


Subject: [tip:perf/core] perf/x86/intel: Enable C-state residency events for Cannon Lake

Commit-ID: 1159e09476536250c2a0173d4298d15114df7a89
Gitweb: https://git.kernel.org/tip/1159e09476536250c2a0173d4298d15114df7a89
Author: Harry Pan <[email protected]>
AuthorDate: Fri, 9 Mar 2018 20:15:48 +0800
Committer: Ingo Molnar <[email protected]>
CommitDate: Sat, 31 Mar 2018 11:28:36 +0200

perf/x86/intel: Enable C-state residency events for Cannon Lake

Cannon Lake supports C1/C3/C6/C7, PC2/PC3/PC6/PC7/PC8/PC9/PC10
state residency counters, this patch enables those counters.

( The MSR information is based on Intel Software Developers' Manual,
Vol. 4, Order No. 335592. )

Tested-by: Puthikorn Voravootivat <[email protected]>
Signed-off-by: Harry Pan <[email protected]>
Reviewed-by: Benson Leung <[email protected]>
Cc: Alexander Shishkin <[email protected]>
Cc: Arnaldo Carvalho de Melo <[email protected]>
Cc: Jiri Olsa <[email protected]>
Cc: [email protected]
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Stephane Eranian <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Vince Weaver <[email protected]>
Cc: [email protected]
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
---
arch/x86/events/intel/cstate.c | 44 +++++++++++++++++++++++++++++-------------
1 file changed, 31 insertions(+), 13 deletions(-)

diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 72db0664a53d..9aca448bb8e6 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -40,50 +40,51 @@
* Model specific counters:
* MSR_CORE_C1_RES: CORE C1 Residency Counter
* perf code: 0x00
- * Available model: SLM,AMT,GLM
+ * Available model: SLM,AMT,GLM,CNL
* Scope: Core (each processor core has a MSR)
* MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
* perf code: 0x01
- * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM
+ * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
+ CNL
* Scope: Core
* MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
* perf code: 0x02
- * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- * SKL,KNL,GLM
+ * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
+ * SKL,KNL,GLM,CNL
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
- * Available model: SNB,IVB,HSW,BDW,SKL
+ * Available model: SNB,IVB,HSW,BDW,SKL,CNL
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
- * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM
+ * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
- * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL
- * GLM
+ * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
+ * GLM,CNL
* Scope: Package (physical package)
* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- * SKL,KNL,GLM
+ * SKL,KNL,GLM,CNL
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
- * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL
+ * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL
* Scope: Package (physical package)
* MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
* perf code: 0x04
- * Available model: HSW ULT only
+ * Available model: HSW ULT,CNL
* Scope: Package (physical package)
* MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
* perf code: 0x05
- * Available model: HSW ULT only
+ * Available model: HSW ULT,CNL
* Scope: Package (physical package)
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
* perf code: 0x06
- * Available model: HSW ULT, GLM
+ * Available model: HSW ULT,GLM,CNL
* Scope: Package (physical package)
*
*/
@@ -486,6 +487,21 @@ static const struct cstate_model hswult_cstates __initconst = {
BIT(PERF_CSTATE_PKG_C10_RES),
};

+static const struct cstate_model cnl_cstates __initconst = {
+ .core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
+ BIT(PERF_CSTATE_CORE_C3_RES) |
+ BIT(PERF_CSTATE_CORE_C6_RES) |
+ BIT(PERF_CSTATE_CORE_C7_RES),
+
+ .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
+ BIT(PERF_CSTATE_PKG_C3_RES) |
+ BIT(PERF_CSTATE_PKG_C6_RES) |
+ BIT(PERF_CSTATE_PKG_C7_RES) |
+ BIT(PERF_CSTATE_PKG_C8_RES) |
+ BIT(PERF_CSTATE_PKG_C9_RES) |
+ BIT(PERF_CSTATE_PKG_C10_RES),
+};
+
static const struct cstate_model slm_cstates __initconst = {
.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
BIT(PERF_CSTATE_CORE_C6_RES),
@@ -557,6 +573,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE, snb_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates),

+ X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_MOBILE, cnl_cstates),
+
X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),