2005-05-25 18:47:17

by YhLu

Subject: 2.6.12-rc5 is broken in nvidia Ck804 Opteron MB/with dual core du al way

Andi,

following patch solve the problem.

YH

--- smpboot.o.c 2005-05-25 12:36:20.793913936 -0700
+++ smpboot.c 2005-05-25 12:36:31.569275832 -0700
@@ -764,7 +764,7 @@
int i;
if (smp_num_siblings > 1) {
for_each_online_cpu (i) {
- if (cpu_core_id[cpu] == cpu_core_id[i]) {
+ if (cpu_to_node[cpu] == cpu_to_node[i]) {
siblings++;
cpu_set(i, cpu_sibling_map[cpu]);
}

> -----Original Message-----
> From: YhLu
> Sent: Wednesday, May 25, 2005 11:10 AM
> To: 'Andi Kleen'
> Cc: [email protected]
> Subject: RE: RT patch acceptance
>
> Andi,
>
> the 2.6.12-rc5 is broken in nvidia Ck804 Opteron MB.
>
> the Core id seems to be right now.
>
> the core 0 of node 1 can not be started and hang there.
>
> YH
>
> CPU 0(2) -> Node 0 -> Core 0
> enabled ExtINT on CPU#0
> ENABLING IO-APIC IRQs
> Using IO-APIC 4
> ...changing IO-APIC physical APIC ID to 4 ... ok.
> Using IO-APIC 5
> ...changing IO-APIC physical APIC ID to 5 ... ok.
> Using IO-APIC 6
> ...changing IO-APIC physical APIC ID to 6 ... ok.
> Using IO-APIC 7
> ...changing IO-APIC physical APIC ID to 7 ... ok.
> Synchronizing Arb IDs.
> testing the IO APIC.......................
>
>
>
>
> .................................... done.
> Using local APIC timer interrupts.
> Detected 12.564 MHz APIC timer.
> Booting processor 1/1 rip 6000 rsp ffff81007ff07f58
> Initializing CPU#1 masked ExtINT on CPU#1
> CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
> CPU: L2 Cache: 1024K (64 bytes/line)
> CPU 1(2) -> Node 0 -> Core 1
> stepping 00
> CPU 1: Syncing TSC to CPU 0.
> Booting processor 2/2 rip 6000 rsp ffff81013ff11f58
> Initializing CPU#2 masked ExtINT on CPU#2

2005-05-25 18:59:02

by Andi Kleen

Subject: Re: 2.6.12-rc5 is broken in nvidia Ck804 Opteron MB/with dual core du al way

On Wed, May 25, 2005 at 11:45:47AM -0700, YhLu wrote:
> Andi,
>
> following patch solve the problem.
>
> YH
>
> --- smpboot.o.c 2005-05-25 12:36:20.793913936 -0700
> +++ smpboot.c 2005-05-25 12:36:31.569275832 -0700
> @@ -764,7 +764,7 @@
> int i;
> if (smp_num_siblings > 1) {
> for_each_online_cpu (i) {
> - if (cpu_core_id[cpu] == cpu_core_id[i]) {
> + if (cpu_to_node[cpu] == cpu_to_node[i]) {

This is not correct though, it doesnt make any sense on non NUMA systems
like Intel ones.

-Andi

> siblings++;
> cpu_set(i, cpu_sibling_map[cpu]);
> }
>
> > -----Original Message-----
> > From: YhLu
> > Sent: Wednesday, May 25, 2005 11:10 AM
> > To: 'Andi Kleen'
> > Cc: [email protected]
> > Subject: RE: RT patch acceptance
> >
> > Andi,
> >
> > the 2.6.12-rc5 is broken in nvidia Ck804 Opteron MB.
> >
> > the Core id seems to be right now.
> >
> > the core 0 of node 1 can not be started and hang there.
> >
> > YH
> >
> > CPU 0(2) -> Node 0 -> Core 0
> > enabled ExtINT on CPU#0
> > ENABLING IO-APIC IRQs
> > Using IO-APIC 4
> > ...changing IO-APIC physical APIC ID to 4 ... ok.
> > Using IO-APIC 5
> > ...changing IO-APIC physical APIC ID to 5 ... ok.
> > Using IO-APIC 6
> > ...changing IO-APIC physical APIC ID to 6 ... ok.
> > Using IO-APIC 7
> > ...changing IO-APIC physical APIC ID to 7 ... ok.
> > Synchronizing Arb IDs.
> > testing the IO APIC.......................
> >
> >
> >
> >
> > .................................... done.
> > Using local APIC timer interrupts.
> > Detected 12.564 MHz APIC timer.
> > Booting processor 1/1 rip 6000 rsp ffff81007ff07f58
> > Initializing CPU#1 masked ExtINT on CPU#1
> > CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
> > CPU: L2 Cache: 1024K (64 bytes/line)
> > CPU 1(2) -> Node 0 -> Core 1
> > stepping 00
> > CPU 1: Syncing TSC to CPU 0.
> > Booting processor 2/2 rip 6000 rsp ffff81013ff11f58
> > Initializing CPU#2 masked ExtINT on CPU#2