Add the compatible "intel,socfpga-stratix10-hsotg" to the DWC2
implementation, because the Stratix DWC2 implementation does
not support clock gating. This compatible is used with generic
snps,dwc2.
Signed-off-by: Meng Li <[email protected]>
---
Documentation/devicetree/bindings/usb/dwc2.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml
index dc4988c0009c..f90094320914 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
@@ -51,6 +51,7 @@ properties:
- amlogic,meson-g12a-usb
- amlogic,meson-a1-usb
- intel,socfpga-agilex-hsotg
+ - intel,socfpga-stratix10-hsotg
- const: snps,dwc2
- const: amcc,dwc-otg
- const: apm,apm82181-dwc-otg
--
2.34.1
On 19/07/2023 04:55, Meng Li wrote:
> Add the compatible "intel,socfpga-stratix10-hsotg" to the DWC2
> implementation, because the Stratix DWC2 implementation does
> not support clock gating. This compatible is used with generic
> snps,dwc2.
>
> Signed-off-by: Meng Li <[email protected]>
Missing changelog, missing versioning. This is v3 or v4.
> ---
> Documentation/devicetree/bindings/usb/dwc2.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml
> index dc4988c0009c..f90094320914 100644
> --- a/Documentation/devicetree/bindings/usb/dwc2.yaml
> +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
> @@ -51,6 +51,7 @@ properties:
> - amlogic,meson-g12a-usb
> - amlogic,meson-a1-usb
> - intel,socfpga-agilex-hsotg
> + - intel,socfpga-stratix10-hsotg
So you just sent the same patch as before. I pointed you to the proper
solution with compatibility.
Best regards,
Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Wednesday, July 19, 2023 2:39 PM
> To: Li, Meng <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]
> Cc: [email protected]
> Subject: Re: [PATCH 3/3] dt-bindings: usb: dwc2: add compatible "intel,socfpga-
> stratix10-hsotg"
>
> CAUTION: This email comes from a non Wind River email account!
> Do not click links or open attachments unless you recognize the sender and
> know the content is safe.
>
> On 19/07/2023 04:55, Meng Li wrote:
> > Add the compatible "intel,socfpga-stratix10-hsotg" to the DWC2
> > implementation, because the Stratix DWC2 implementation does not
> > support clock gating. This compatible is used with generic snps,dwc2.
> >
> > Signed-off-by: Meng Li <[email protected]>
>
> Missing changelog, missing versioning. This is v3 or v4.
>
> > ---
> > Documentation/devicetree/bindings/usb/dwc2.yaml | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml
> > b/Documentation/devicetree/bindings/usb/dwc2.yaml
> > index dc4988c0009c..f90094320914 100644
> > --- a/Documentation/devicetree/bindings/usb/dwc2.yaml
> > +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
> > @@ -51,6 +51,7 @@ properties:
> > - amlogic,meson-g12a-usb
> > - amlogic,meson-a1-usb
> > - intel,socfpga-agilex-hsotg
> > + - intel,socfpga-stratix10-hsotg
>
> So you just sent the same patch as before. I pointed you to the proper solution
> with compatibility.
>
No. not the same.
I don't understand why SoC specific compatible "intel,socfpga-agilex-hsotg" is able to be added, but the SoC specific compatible "intel,socfpga-stratix10-hsotg" is not allowed.
You said "Where is SoC specific compatible?"
Now, I add the SoC specific compatible "intel,socfpga-stratix10-hsotg", but why it is still not reasonable.
Thanks,
Limeng
>
>
> Best regards,
> Krzysztof
On 19/07/2023 10:45, Li, Meng wrote:
>
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski <[email protected]>
>> Sent: Wednesday, July 19, 2023 2:39 PM
>> To: Li, Meng <[email protected]>; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]
>> Cc: [email protected]
>> Subject: Re: [PATCH 3/3] dt-bindings: usb: dwc2: add compatible "intel,socfpga-
>> stratix10-hsotg"
>>
>> CAUTION: This email comes from a non Wind River email account!
>> Do not click links or open attachments unless you recognize the sender and
>> know the content is safe.
>>
>> On 19/07/2023 04:55, Meng Li wrote:
>>> Add the compatible "intel,socfpga-stratix10-hsotg" to the DWC2
>>> implementation, because the Stratix DWC2 implementation does not
>>> support clock gating. This compatible is used with generic snps,dwc2.
>>>
>>> Signed-off-by: Meng Li <[email protected]>
>>
>> Missing changelog, missing versioning. This is v3 or v4.
>>
>>> ---
>>> Documentation/devicetree/bindings/usb/dwc2.yaml | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml
>>> b/Documentation/devicetree/bindings/usb/dwc2.yaml
>>> index dc4988c0009c..f90094320914 100644
>>> --- a/Documentation/devicetree/bindings/usb/dwc2.yaml
>>> +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
>>> @@ -51,6 +51,7 @@ properties:
>>> - amlogic,meson-g12a-usb
>>> - amlogic,meson-a1-usb
>>> - intel,socfpga-agilex-hsotg
>>> + - intel,socfpga-stratix10-hsotg
>>
>> So you just sent the same patch as before. I pointed you to the proper solution
>> with compatibility.
>>
>
> No. not the same.
> I don't understand why SoC specific compatible "intel,socfpga-agilex-hsotg" is able to be added, but the SoC specific compatible "intel,socfpga-stratix10-hsotg" is not allowed.
>
> You said "Where is SoC specific compatible?"
> Now, I add the SoC specific compatible "intel,socfpga-stratix10-hsotg", but why it is still not reasonable.
The compatible should be added, but I said they are compatible, so
express it. I also gave you example of file which expresses it.
Why that compatible is not allowed alone? Because what we said here
many, many times and because the doc I gave you which explains this.
Best regards,
Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Wednesday, July 19, 2023 4:59 PM
> To: Li, Meng <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]
> Cc: [email protected]
> Subject: Re: [PATCH 3/3] dt-bindings: usb: dwc2: add compatible "intel,socfpga-
> stratix10-hsotg"
>
> CAUTION: This email comes from a non Wind River email account!
> Do not click links or open attachments unless you recognize the sender and
> know the content is safe.
>
> On 19/07/2023 10:45, Li, Meng wrote:
> >
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <[email protected]>
> >> Sent: Wednesday, July 19, 2023 2:39 PM
> >> To: Li, Meng <[email protected]>; [email protected];
> >> [email protected]; [email protected];
> >> [email protected];
> >> [email protected]; [email protected]; [email protected];
> >> [email protected]
> >> Cc: [email protected]
> >> Subject: Re: [PATCH 3/3] dt-bindings: usb: dwc2: add compatible
> >> "intel,socfpga- stratix10-hsotg"
> >>
> >> CAUTION: This email comes from a non Wind River email account!
> >> Do not click links or open attachments unless you recognize the
> >> sender and know the content is safe.
> >>
> >> On 19/07/2023 04:55, Meng Li wrote:
> >>> Add the compatible "intel,socfpga-stratix10-hsotg" to the DWC2
> >>> implementation, because the Stratix DWC2 implementation does not
> >>> support clock gating. This compatible is used with generic snps,dwc2.
> >>>
> >>> Signed-off-by: Meng Li <[email protected]>
> >>
> >> Missing changelog, missing versioning. This is v3 or v4.
> >>
> >>> ---
> >>> Documentation/devicetree/bindings/usb/dwc2.yaml | 1 +
> >>> 1 file changed, 1 insertion(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml
> >>> b/Documentation/devicetree/bindings/usb/dwc2.yaml
> >>> index dc4988c0009c..f90094320914 100644
> >>> --- a/Documentation/devicetree/bindings/usb/dwc2.yaml
> >>> +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
> >>> @@ -51,6 +51,7 @@ properties:
> >>> - amlogic,meson-g12a-usb
> >>> - amlogic,meson-a1-usb
> >>> - intel,socfpga-agilex-hsotg
> >>> + - intel,socfpga-stratix10-hsotg
> >>
> >> So you just sent the same patch as before. I pointed you to the
> >> proper solution with compatibility.
> >>
> >
> > No. not the same.
> > I don't understand why SoC specific compatible "intel,socfpga-agilex-hsotg" is
> able to be added, but the SoC specific compatible "intel,socfpga-stratix10-hsotg"
> is not allowed.
> >
> > You said "Where is SoC specific compatible?"
> > Now, I add the SoC specific compatible "intel,socfpga-stratix10-hsotg", but
> why it is still not reasonable.
>
> The compatible should be added, but I said they are compatible, so express it. I
> also gave you example of file which expresses it.
>
> Why that compatible is not allowed alone? Because what we said here many,
> many times and because the doc I gave you which explains this.
>
I had a look the doc ,and refer to rk3128.dtsi and commit 5032b269203287c17064d33c72be1ebf30c04a95.
So I think it needs to add " intel,socfpga-stratix10-hsotg" Documentation/devicetree/bindings/usb/dwc2.yaml.
But if you think it is not reasonable, could you please show what is your modification for the dwc2.yaml.
Thanks,
Limeng
> Best regards,
> Krzysztof
On 19/07/2023 11:49, Li, Meng wrote:
>
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski <[email protected]>
>> Sent: Wednesday, July 19, 2023 4:59 PM
>> To: Li, Meng <[email protected]>; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]
>> Cc: [email protected]
>> Subject: Re: [PATCH 3/3] dt-bindings: usb: dwc2: add compatible "intel,socfpga-
>> stratix10-hsotg"
>>
>> CAUTION: This email comes from a non Wind River email account!
>> Do not click links or open attachments unless you recognize the sender and
>> know the content is safe.
>>
>> On 19/07/2023 10:45, Li, Meng wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: Krzysztof Kozlowski <[email protected]>
>>>> Sent: Wednesday, July 19, 2023 2:39 PM
>>>> To: Li, Meng <[email protected]>; [email protected];
>>>> [email protected]; [email protected];
>>>> [email protected];
>>>> [email protected]; [email protected]; [email protected];
>>>> [email protected]
>>>> Cc: [email protected]
>>>> Subject: Re: [PATCH 3/3] dt-bindings: usb: dwc2: add compatible
>>>> "intel,socfpga- stratix10-hsotg"
>>>>
>>>> CAUTION: This email comes from a non Wind River email account!
>>>> Do not click links or open attachments unless you recognize the
>>>> sender and know the content is safe.
>>>>
>>>> On 19/07/2023 04:55, Meng Li wrote:
>>>>> Add the compatible "intel,socfpga-stratix10-hsotg" to the DWC2
>>>>> implementation, because the Stratix DWC2 implementation does not
>>>>> support clock gating. This compatible is used with generic snps,dwc2.
>>>>>
>>>>> Signed-off-by: Meng Li <[email protected]>
>>>>
>>>> Missing changelog, missing versioning. This is v3 or v4.
>>>>
>>>>> ---
>>>>> Documentation/devicetree/bindings/usb/dwc2.yaml | 1 +
>>>>> 1 file changed, 1 insertion(+)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml
>>>>> b/Documentation/devicetree/bindings/usb/dwc2.yaml
>>>>> index dc4988c0009c..f90094320914 100644
>>>>> --- a/Documentation/devicetree/bindings/usb/dwc2.yaml
>>>>> +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
>>>>> @@ -51,6 +51,7 @@ properties:
>>>>> - amlogic,meson-g12a-usb
>>>>> - amlogic,meson-a1-usb
>>>>> - intel,socfpga-agilex-hsotg
>>>>> + - intel,socfpga-stratix10-hsotg
>>>>
>>>> So you just sent the same patch as before. I pointed you to the
>>>> proper solution with compatibility.
>>>>
>>>
>>> No. not the same.
>>> I don't understand why SoC specific compatible "intel,socfpga-agilex-hsotg" is
>> able to be added, but the SoC specific compatible "intel,socfpga-stratix10-hsotg"
>> is not allowed.
>>>
>>> You said "Where is SoC specific compatible?"
>>> Now, I add the SoC specific compatible "intel,socfpga-stratix10-hsotg", but
>> why it is still not reasonable.
>>
>> The compatible should be added, but I said they are compatible, so express it. I
>> also gave you example of file which expresses it.
>>
>> Why that compatible is not allowed alone? Because what we said here many,
>> many times and because the doc I gave you which explains this.
>>
>
> I had a look the doc ,and refer to rk3128.dtsi and commit 5032b269203287c17064d33c72be1ebf30c04a95.
> So I think it needs to add " intel,socfpga-stratix10-hsotg" Documentation/devicetree/bindings/usb/dwc2.yaml.
Open the DTSI and look at compatibles. Now open the driver and look at
the compatibles - surprise, there is no rockchip,rk3128-usb! Now open
the binding and look how it is done.
> But if you think it is not reasonable, could you please show what is your modification for the dwc2.yaml.
Open the binding - it is already there.
I bet there is someone in Windriver who does Linux and can help here as
well, none of existing code is working for you as an example?
Best regards,
Krzysztof