On Wed, Nov 15, 2017 at 11:54:20AM +0100, Marc Kleine-Budde wrote:
> On 11/14/2017 01:02 PM, Mark Brown wrote:
> > On Mon, Nov 13, 2017 at 01:17:42PM -0800, Tim Harvey wrote:
> >
> >> When a register is read from the mcp251x driver the
> >> octeon_spi_do_transfer() gets a spi_message with a single spi_xfer of
> >> len=3, a tx_buf, and an rx_buf which I believe is supposed to shift
> >> out 3 bytes out MOSI and shift in 3 bytes from MISO where the last
> >> byte shifted in would be the response.
> >
> > No, that will simultaneously transmit and recieve three bytes.
>
> That's what the driver supposed to do.
>
> > If you want to transmit two bytes and then recieve one byte you need
> > two xfers, one with a len of 2 and a tx_buf, the other with a len of
> > 1 and a rx_buf.
> To read a register (mcp251x_read_reg()) the mcp251x does a 3 byte full
> duplex transfer. The first byte send is the command (read register) the
> second byte the register number the third byte is a dummy. The first 2
> bytes received are ignored the 3rd byte is the register contents.
To support this full duplex transfer the Cavium SPI controller needs
to know the receive lenght before setting up the transaction.
spi_transfer only includes the total length, so I don't see how this
should work.
--Jan
From 1584139669779375728@xxx Wed Nov 15 13:41:56 +0000 2017
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On 11/15/2017 01:07 PM, Jan Glauber wrote:
> On Wed, Nov 15, 2017 at 11:54:20AM +0100, Marc Kleine-Budde wrote:
>> On 11/14/2017 01:02 PM, Mark Brown wrote:
>>> On Mon, Nov 13, 2017 at 01:17:42PM -0800, Tim Harvey wrote:
>>>
>>>> When a register is read from the mcp251x driver the
>>>> octeon_spi_do_transfer() gets a spi_message with a single spi_xfer of
>>>> len=3, a tx_buf, and an rx_buf which I believe is supposed to shift
>>>> out 3 bytes out MOSI and shift in 3 bytes from MISO where the last
>>>> byte shifted in would be the response.
>>>
>>> No, that will simultaneously transmit and recieve three bytes.
>>
>> That's what the driver supposed to do.
>>
>>> If you want to transmit two bytes and then recieve one byte you need
>>> two xfers, one with a len of 2 and a tx_buf, the other with a len of
>>> 1 and a rx_buf.
>> To read a register (mcp251x_read_reg()) the mcp251x does a 3 byte full
>> duplex transfer. The first byte send is the command (read register) the
>> second byte the register number the third byte is a dummy. The first 2
>> bytes received are ignored the 3rd byte is the register contents.
>
> To support this full duplex transfer the Cavium SPI controller needs
> to know the receive lenght before setting up the transaction.
>
> spi_transfer only includes the total length, so I don't see how this
> should work.
It's a standard 3 byte full duplex transfer. Three bytes are send while
three bytes are received.
> static int mcp251x_spi_trans(struct spi_device *spi, int len)
> {
> struct mcp251x_priv *priv = spi_get_drvdata(spi);
> struct spi_transfer t = {
> .tx_buf = priv->spi_tx_buf,
> .rx_buf = priv->spi_rx_buf,
> .len = len,
> .cs_change = 0,
> };
> struct spi_message m;
> int ret;
>
> spi_message_init(&m);
>
> if (mcp251x_enable_dma) {
> t.tx_dma = priv->spi_tx_dma;
> t.rx_dma = priv->spi_rx_dma;
> m.is_dma_mapped = 1;
> }
>
> spi_message_add_tail(&t, &m);
>
> ret = spi_sync(spi, &m);
> if (ret)
> dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
> return ret;
> }
mcp251x_spi_trans() is called with len=3,
priv->spi_tx_buf and priv->spi_rx_buf point to previously allocared memory
priv->spi_tx_buf has been filled before calling mcp251x_spi_trans().
Marc
--
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