Add sdhc instance for supporting eMMC on QDU1000 and
QRU1000 SoCs.
Changes in v3 -
* Removed aliases and dropped "_1" suffix as suggested by Bjorn.
* Changed pinconfig names.
Changes in v2-
* Updated the binding alphabetically.
* Removed extra comments as suggested by Bhupesh.
* Moved non-removable, no-sd, no-sdio and other properties from
soc to board dts file as suggested by Bhupesh and Konrad.
* Removed extra newlines and leading zeroes as suggested by Konrad.
* Modified sdhc1_opp_table.
* Updated the SDHC node entries alphabetically.
* Moved the status entry at the end.
Komal Bajaj (4):
dt-bindings: mmc: sdhci-msm: Document the QDU1000/QRU1000 compatible
arm: dts: qcom: qdu1000: Add SDHCI node
arm64: dts: qcom: qdu1000: Add SDHCI pin configuration to DTSI
arm64: dts: qcom: qdu1000-idp: add SDHCI for emmc
.../devicetree/bindings/mmc/sdhci-msm.yaml | 1 +
arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 23 +++++
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 97 +++++++++++++++++++
3 files changed, 121 insertions(+)
--
2.17.1
Document the compatible for SDHCI on QDU1000 and QRU1000 SoCs.
Acked-by: Conor Dooley <[email protected]>
Reviewed-by: Bhupesh Sharma <[email protected]>
Signed-off-by: Komal Bajaj <[email protected]>
---
Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
index 4f2d9e8127dd..af29d60ff0d6 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
@@ -39,6 +39,7 @@ properties:
- qcom,ipq9574-sdhci
- qcom,qcm2290-sdhci
- qcom,qcs404-sdhci
+ - qcom,qdu1000-sdhci
- qcom,sc7180-sdhci
- qcom,sc7280-sdhci
- qcom,sdm630-sdhci
--
2.17.1
Add sdhc node for eMMC on QDU1000 and QRU1000 SoCs.
Signed-off-by: Komal Bajaj <[email protected]>
---
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 47 +++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index 734438113bba..6df07334f1d3 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -842,6 +842,53 @@
#hwlock-cells = <1>;
};
+ sdhc: mmc@8804000 {
+ compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x08804000 0x0 0x1000>,
+ <0x0 0x08805000 0x0 0x1000>;
+ reg-names = "hc", "cqhci";
+
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC5_AHB_CLK>,
+ <&gcc GCC_SDCC5_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "core",
+ "xo";
+
+ resets = <&gcc GCC_SDCC5_BCR>;
+
+ interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>;
+ interconnect-names = "sdhc-ddr", "cpu-sdhc";
+ power-domains = <&rpmhpd QDU1000_CX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
+
+ iommus = <&apps_smmu 0x80 0x0>;
+ dma-coherent;
+
+ bus-width = <8>;
+
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+
+ status = "disabled";
+
+ sdhc1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <6528000 1652800>;
+ opp-avg-kBps = <400000 0>;
+ };
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,qdu1000-pdc", "qcom,pdc";
reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
--
2.17.1
Add sdhci node for emmc in qdu1000-idp.
Signed-off-by: Komal Bajaj <[email protected]>
---
arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
index 9e9fd4b8023e..6e988e90aa50 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
+++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
@@ -448,6 +448,29 @@
status = "okay";
};
+&sdhc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc_on_state>;
+ pinctrl-1 = <&sdc_off_state>;
+
+ cap-mmc-hw-reset;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+
+ non-removable;
+ no-sd;
+ no-sdio;
+
+ supports-cqe;
+
+ vmmc-supply = <&vreg_l10a_2p95>;
+ vqmmc-supply = <&vreg_l7a_1p8>;
+
+ status = "okay";
+};
+
&uart7 {
status = "okay";
};
--
2.17.1
On Tue, May 23, 2023 at 07:27:31PM +0530, Komal Bajaj wrote:
> Add sdhc node for eMMC on QDU1000 and QRU1000 SoCs.
>
Please fix your $subject prefix, it should say arm64
Regards,
Bjorn
> Signed-off-by: Komal Bajaj <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 47 +++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> index 734438113bba..6df07334f1d3 100644
> --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> @@ -842,6 +842,53 @@
> #hwlock-cells = <1>;
> };
>
> + sdhc: mmc@8804000 {
> + compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0x0 0x08804000 0x0 0x1000>,
> + <0x0 0x08805000 0x0 0x1000>;
> + reg-names = "hc", "cqhci";
> +
> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC5_AHB_CLK>,
> + <&gcc GCC_SDCC5_APPS_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface",
> + "core",
> + "xo";
> +
> + resets = <&gcc GCC_SDCC5_BCR>;
> +
> + interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>;
> + interconnect-names = "sdhc-ddr", "cpu-sdhc";
> + power-domains = <&rpmhpd QDU1000_CX>;
> + operating-points-v2 = <&sdhc1_opp_table>;
> +
> + iommus = <&apps_smmu 0x80 0x0>;
> + dma-coherent;
> +
> + bus-width = <8>;
> +
> + qcom,dll-config = <0x0007642c>;
> + qcom,ddr-config = <0x80040868>;
> +
> + status = "disabled";
> +
> + sdhc1_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-384000000 {
> + opp-hz = /bits/ 64 <384000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + opp-peak-kBps = <6528000 1652800>;
> + opp-avg-kBps = <400000 0>;
> + };
> + };
> + };
> +
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,qdu1000-pdc", "qcom,pdc";
> reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
> --
> 2.17.1
>
On 23.05.2023 15:57, Komal Bajaj wrote:
> Add sdhci node for emmc in qdu1000-idp.
>
> Signed-off-by: Komal Bajaj <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> index 9e9fd4b8023e..6e988e90aa50 100644
> --- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> @@ -448,6 +448,29 @@
> status = "okay";
> };
>
> +&sdhc {
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&sdc_on_state>;
> + pinctrl-1 = <&sdc_off_state>;
Please do
property-n
property-names
we've had a little bit of a mess over the years but we're trying
to unify that.
With that:
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> +
> + cap-mmc-hw-reset;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + mmc-hs400-enhanced-strobe;
> +
> + non-removable;
> + no-sd;
> + no-sdio;
> +
> + supports-cqe;
> +
> + vmmc-supply = <&vreg_l10a_2p95>;
> + vqmmc-supply = <&vreg_l7a_1p8>;
> +
> + status = "okay";
> +};
> +
> &uart7 {
> status = "okay";
> };
> --
> 2.17.1
>
On 5/25/2023 9:57 AM, Bjorn Andersson wrote:
> On Tue, May 23, 2023 at 07:27:31PM +0530, Komal Bajaj wrote:
>> Add sdhc node for eMMC on QDU1000 and QRU1000 SoCs.
>>
> Please fix your $subject prefix, it should say arm64
>
> Regards,
> Bjorn
Noted.
>> Signed-off-by: Komal Bajaj <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 47 +++++++++++++++++++++++++++
>> 1 file changed, 47 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> index 734438113bba..6df07334f1d3 100644
>> --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> @@ -842,6 +842,53 @@
>> #hwlock-cells = <1>;
>> };
>>
>> + sdhc: mmc@8804000 {
>> + compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5";
>> + reg = <0x0 0x08804000 0x0 0x1000>,
>> + <0x0 0x08805000 0x0 0x1000>;
>> + reg-names = "hc", "cqhci";
>> +
>> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "hc_irq", "pwr_irq";
>> +
>> + clocks = <&gcc GCC_SDCC5_AHB_CLK>,
>> + <&gcc GCC_SDCC5_APPS_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK>;
>> + clock-names = "iface",
>> + "core",
>> + "xo";
>> +
>> + resets = <&gcc GCC_SDCC5_BCR>;
>> +
>> + interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>;
>> + interconnect-names = "sdhc-ddr", "cpu-sdhc";
>> + power-domains = <&rpmhpd QDU1000_CX>;
>> + operating-points-v2 = <&sdhc1_opp_table>;
>> +
>> + iommus = <&apps_smmu 0x80 0x0>;
>> + dma-coherent;
>> +
>> + bus-width = <8>;
>> +
>> + qcom,dll-config = <0x0007642c>;
>> + qcom,ddr-config = <0x80040868>;
>> +
>> + status = "disabled";
>> +
>> + sdhc1_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-384000000 {
>> + opp-hz = /bits/ 64 <384000000>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + opp-peak-kBps = <6528000 1652800>;
>> + opp-avg-kBps = <400000 0>;
>> + };
>> + };
>> + };
>> +
>> pdc: interrupt-controller@b220000 {
>> compatible = "qcom,qdu1000-pdc", "qcom,pdc";
>> reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
>> --
>> 2.17.1
>>
On 5/27/2023 4:52 AM, Konrad Dybcio wrote:
>
> On 23.05.2023 15:57, Komal Bajaj wrote:
>> Add sdhci node for emmc in qdu1000-idp.
>>
>> Signed-off-by: Komal Bajaj <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 23 +++++++++++++++++++++++
>> 1 file changed, 23 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
>> index 9e9fd4b8023e..6e988e90aa50 100644
>> --- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
>> +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
>> @@ -448,6 +448,29 @@
>> status = "okay";
>> };
>>
>> +&sdhc {
>> + pinctrl-names = "default", "sleep";
>> + pinctrl-0 = <&sdc_on_state>;
>> + pinctrl-1 = <&sdc_off_state>;
> Please do
>
> property-n
> property-names
>
> we've had a little bit of a mess over the years but we're trying
> to unify that.
Sure, will change in the next patch set.
Thanks
Komal
>
> With that:
>
> Reviewed-by: Konrad Dybcio <[email protected]>
>
> Konrad
>> +
>> + cap-mmc-hw-reset;
>> + mmc-ddr-1_8v;
>> + mmc-hs200-1_8v;
>> + mmc-hs400-1_8v;
>> + mmc-hs400-enhanced-strobe;
>> +
>> + non-removable;
>> + no-sd;
>> + no-sdio;
>> +
>> + supports-cqe;
>> +
>> + vmmc-supply = <&vreg_l10a_2p95>;
>> + vqmmc-supply = <&vreg_l7a_1p8>;
>> +
>> + status = "okay";
>> +};
>> +
>> &uart7 {
>> status = "okay";
>> };
>> --
>> 2.17.1
>>