This patch series adds the relevant phy and controller
configurations for enabling USB on IPQ9754
Depends on:
https://lore.kernel.org/all/[email protected]/
[v4]:
- Incorporated review comments
- Address all 'make dtbs_check' errors
[v3]:
- Incorporated review comments regarding coding style
[v2]:
- Incorporated review comments regarding coding style,
maintaining sorted order of entries and unused phy register
offsets
- Removed NOC clock entries from DT node (will be implemented
later with interconnect support)
- Fixed 'make dtbs_check' errors/warnings
[v1]:
https://lore.kernel.org/linux-arm-msm/[email protected]/T/
Varadarajan Narayanan (8):
dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible
dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY
dt-bindings: usb: dwc3: Add IPQ9574 compatible
clk: qcom: gcc-ipq9574: Add USB related clocks
phy: qcom-qusb2: add QUSB2 support for IPQ9574
phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
arm64: dts: qcom: ipq9574: Add USB related nodes
arm64: dts: qcom: ipq9574: Enable USB
.../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 25 +++-
.../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 6 +-
.../devicetree/bindings/usb/qcom,dwc3.yaml | 22 +++-
arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 12 ++
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 83 +++++++++++++
drivers/clk/qcom/gcc-ipq9574.c | 37 ++++++
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 129 +++++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 +
9 files changed, 310 insertions(+), 9 deletions(-)
--
2.7.4
Document the compatible string used for the qusb2 phy in IPQ9574.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Changes in v4:
- Remove constraints not applicable to IPQ9574
Changes in v3:
- Maintain the proper sorted order
Changes in v2:
- Moved ipq6018 to the proper place and placed ipq9574
next to it as suggested by Dmitry
---
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
index 7f403e7..3cb27da 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
@@ -18,13 +18,14 @@ properties:
oneOf:
- items:
- enum:
+ - qcom,ipq6018-qusb2-phy
- qcom,ipq8074-qusb2-phy
+ - qcom,ipq9574-qusb2-phy
- qcom,msm8953-qusb2-phy
- qcom,msm8996-qusb2-phy
- qcom,msm8998-qusb2-phy
- qcom,qcm2290-qusb2-phy
- qcom,sdm660-qusb2-phy
- - qcom,ipq6018-qusb2-phy
- qcom,sm4250-qusb2-phy
- qcom,sm6115-qusb2-phy
- items:
@@ -157,9 +158,6 @@ required:
- "#phy-cells"
- clocks
- clock-names
- - vdd-supply
- - vdda-pll-supply
- - vdda-phy-dpdm-supply
- resets
allOf:
--
2.7.4
Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Changes in v4:
- Remove constraints not applicable to IPQ9574
Changes in v3:
- Update other mandatory fields to accomodate IPQ9574
Changes in v2:
- Updated sections missed in previous patch
---
.../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 25 ++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
index e81a382..aa5b58c 100644
--- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
@@ -21,6 +21,7 @@ properties:
enum:
- qcom,ipq6018-qmp-usb3-phy
- qcom,ipq8074-qmp-usb3-phy
+ - qcom,ipq9574-qmp-usb3-phy
- qcom,msm8996-qmp-usb3-phy
- qcom,msm8998-qmp-usb3-phy
- qcom,qcm2290-qmp-usb3-phy
@@ -122,8 +123,6 @@ required:
- clock-names
- resets
- reset-names
- - vdda-phy-supply
- - vdda-pll-supply
additionalProperties: false
@@ -204,6 +203,28 @@ allOf:
compatible:
contains:
enum:
+ - qcom,ipq9574-qmp-usb3-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: pipe
+ resets:
+ maxItems: 2
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
- qcom,sm8150-qmp-usb3-phy
- qcom,sm8150-qmp-usb3-uni-phy
- qcom,sm8250-qmp-usb3-uni-phy
--
2.7.4
Document the IPQ9574 dwc3 compatible.
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Changes in v4:
- Update other relevant sections
- Remove constraints not applicable to IPQ9574
---
.../devicetree/bindings/usb/qcom,dwc3.yaml | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
index a2aabda..3fc8c3c 100644
--- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
@@ -17,6 +17,7 @@ properties:
- qcom,ipq6018-dwc3
- qcom,ipq8064-dwc3
- qcom,ipq8074-dwc3
+ - qcom,ipq9574-dwc3
- qcom,msm8953-dwc3
- qcom,msm8994-dwc3
- qcom,msm8996-dwc3
@@ -132,11 +133,8 @@ required:
- "#address-cells"
- "#size-cells"
- ranges
- - power-domains
- clocks
- clock-names
- - interrupts
- - interrupt-names
allOf:
- if:
@@ -242,6 +240,24 @@ allOf:
compatible:
contains:
enum:
+ - qcom,ipq9574-dwc3
+ then:
+ properties:
+ clocks:
+ maxItems: 5
+ clock-names:
+ items:
+ - const: sys_noc_axi
+ - const: anoc_axi
+ - const: master
+ - const: sleep
+ - const: mock_utmi
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
- qcom,msm8994-dwc3
- qcom,qcs404-dwc3
then:
--
2.7.4
Add the clocks needed for enabling USB in IPQ9574
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Changes in v2:
- Fixed coding style issues
---
drivers/clk/qcom/gcc-ipq9574.c | 37 ++++++++++++++++++++++++++++
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 ++
2 files changed, 39 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 1bf33d5..06b724a 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -2041,6 +2041,41 @@ static struct clk_regmap_mux usb0_pipe_clk_src = {
},
};
+static struct clk_branch gcc_usb0_pipe_clk = {
+ .halt_reg = 0x2c054,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2c054,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &usb0_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_sleep_clk = {
+ .halt_reg = 0x2c058,
+ .clkr = {
+ .enable_reg = 0x2c058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_sleep_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_sleep_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
F(144000, P_XO, 16, 12, 125),
F(400000, P_XO, 12, 1, 5),
@@ -4008,6 +4043,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
+ [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
+ [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
index 14543a4..97a7b19 100644
--- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
@@ -214,4 +214,6 @@
#define GCC_SNOC_PCIE1_1LANE_S_CLK 205
#define GCC_SNOC_PCIE2_2LANE_S_CLK 206
#define GCC_SNOC_PCIE3_2LANE_S_CLK 207
+#define GCC_USB0_PIPE_CLK 208
+#define GCC_USB0_SLEEP_CLK 209
#endif
--
2.7.4
Updated USB QMP PHY Init sequence based on HPG for IPQ9574.
Reused clock and reset list from existing targets.
Signed-off-by: Praveenkumar I <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Changes in v4:
- Use qmp_usb_offsets for register space access
Changes in v3:
- Fix hex captitalization
Changes in v2:
- Removed unused phy register offsets
- Moved the clock entries to the correct place
- Maintain sorted order
---
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 129 ++++++++++++++++++++++++++++++++
1 file changed, 129 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index a49711c..ed5f794 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -94,6 +94,7 @@ enum qphy_reg_layout {
QPHY_PCS_STATUS,
QPHY_PCS_AUTONOMOUS_MODE_CTRL,
QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
+ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
QPHY_PCS_POWER_DOWN_CONTROL,
/* Keep last to ensure regs_layout arrays are properly initialized */
QPHY_LAYOUT_SIZE
@@ -139,6 +140,97 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
};
+static const unsigned int usb3phy_regs_layout[] = {
+ [QPHY_SW_RESET] = 0x00,
+ [QPHY_START_CTRL] = 0x08,
+ [QPHY_PCS_STATUS] = 0x17c,
+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
+ /* PLL and Loop filter settings */
+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+ /* SSC settings */
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
+};
+
static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
@@ -1510,6 +1602,10 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
}
/* list of clocks required by phy */
+static const char * const ipq9574_phy_clk_l[] = {
+ "aux", "cfg_ahb",
+};
+
static const char * const msm8996_phy_clk_l[] = {
"aux", "cfg_ahb", "ref",
};
@@ -1558,6 +1654,14 @@ static const char * const qmp_phy_vreg_l[] = {
"vdda-phy", "vdda-pll",
};
+static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
+ .serdes = 0,
+ .pcs = 0x800,
+ .pcs_usb = 0x600,
+ .tx = 0x200,
+ .rx = 0x400,
+};
+
static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
.serdes = 0,
.pcs = 0x0200,
@@ -1586,6 +1690,28 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
.regs = qmp_v3_usb3phy_regs_layout,
};
+static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
+ .lanes = 1,
+
+ .offsets = &qmp_usb_offsets_ipq9574,
+
+ .serdes_tbl = ipq9574_usb3_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
+ .tx_tbl = ipq9574_usb3_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
+ .rx_tbl = ipq9574_usb3_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
+ .pcs_tbl = ipq9574_usb3_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
+ .clk_list = ipq9574_phy_clk_l,
+ .num_clks = ARRAY_SIZE(ipq9574_phy_clk_l),
+ .reset_list = msm8996_usb3phy_reset_l,
+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = usb3phy_regs_layout,
+};
+
static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
.lanes = 1,
@@ -2589,6 +2715,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
.compatible = "qcom,ipq8074-qmp-usb3-phy",
.data = &ipq8074_usb3phy_cfg,
}, {
+ .compatible = "qcom,ipq9574-qmp-usb3-phy",
+ .data = &ipq9574_usb3phy_cfg,
+ }, {
.compatible = "qcom,msm8996-qmp-usb3-phy",
.data = &msm8996_usb3phy_cfg,
}, {
--
2.7.4
Add USB phy and controller related nodes
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Changes in v4:
- Use newer bindings without subnodes
- Fix coding style issues
Changes in v3:
- Insert the nodes at proper location
Changes in v2:
- Fixed issues flagged by Krzysztof
- Fix issues reported by make dtbs_check
- Remove NOC related clocks (to be added with proper
interconnect support)
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 83 +++++++++++++++++++++++++++++++++++
1 file changed, 83 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 2bb4053..5379c25 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -215,6 +215,45 @@
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
+ qusb_phy_0: phy@7b000 {
+ compatible = "qcom,ipq9574-qusb2-phy";
+ reg = <0x0007b000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&xo_board_clk>;
+ clock-names = "cfg_ahb",
+ "ref";
+
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+ status = "disabled";
+ };
+
+ ssphy_0: phy@7d000 {
+ compatible = "qcom,ipq9574-qmp-usb3-phy";
+ reg = <0x0007d000 0xa00>;
+ #clock-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_USB0_AUX_CLK>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "pipe";
+
+ resets = <&gcc GCC_USB0_PHY_BCR>,
+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+ status = "disabled";
+
+ #phy-cells = <0>;
+ clock-output-names = "usb0_pipe_clk";
+ };
+
pcie0_phy: phy@84000 {
compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
reg = <0x00084000 0x1bc>; /* Serdes PLL */
@@ -436,6 +475,50 @@
status = "disabled";
};
+ usb3: usb3@8a00000 {
+ compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
+ reg = <0x08af8800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_SNOC_USB_CLK>,
+ <&gcc GCC_ANOC_USB_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_SLEEP_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+
+ clock-names = "sys_noc_axi",
+ "anoc_axi",
+ "master",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <200000000>,
+ <24000000>;
+
+ resets = <&gcc GCC_USB_BCR>;
+ status = "disabled";
+
+ dwc_0: usb@8a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x8a00000 0xcd00>;
+ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "ref";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&qusb_phy_0>, <&ssphy_0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ dr_mode = "host";
+ };
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
--
2.7.4
Add the phy init sequence for the Super Speed ports found
on IPQ9574.
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Changes in v2:
- Place the entry such that the list continues to be sorted
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index 2ef638b..bec6e40 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -912,6 +912,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
.compatible = "qcom,ipq8074-qusb2-phy",
.data = &msm8996_phy_cfg,
}, {
+ .compatible = "qcom,ipq9574-qusb2-phy",
+ .data = &ipq6018_phy_cfg,
+ }, {
.compatible = "qcom,msm8953-qusb2-phy",
.data = &msm8996_phy_cfg,
}, {
--
2.7.4
Turn on USB related nodes
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Changes in v2:
- Fix node placement and coding style
- "ok" -> "okay"
---
arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
index 8a6caae..d0d18e5 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
+++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
@@ -57,6 +57,10 @@
status = "okay";
};
+&qusb_phy_0 {
+ status = "okay";
+};
+
&rpm_requests {
regulators {
compatible = "qcom,rpm-mp5496-regulators";
@@ -84,6 +88,10 @@
clock-frequency = <32000>;
};
+&ssphy_0 {
+ status = "okay";
+};
+
&tlmm {
sdc_default_state: sdc-default-state {
clk-pins {
@@ -118,6 +126,10 @@
};
};
+&usb3 {
+ status = "okay";
+};
+
&xo_board_clk {
clock-frequency = <24000000>;
};
--
2.7.4
On Mon, 27 Mar 2023 at 12:32, Varadarajan Narayanan
<[email protected]> wrote:
>
> Updated USB QMP PHY Init sequence based on HPG for IPQ9574.
> Reused clock and reset list from existing targets.
>
> Signed-off-by: Praveenkumar I <[email protected]>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> Changes in v4:
> - Use qmp_usb_offsets for register space access
> Changes in v3:
> - Fix hex captitalization
> Changes in v2:
> - Removed unused phy register offsets
> - Moved the clock entries to the correct place
> - Maintain sorted order
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 129 ++++++++++++++++++++++++++++++++
> 1 file changed, 129 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> index a49711c..ed5f794 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> @@ -94,6 +94,7 @@ enum qphy_reg_layout {
> QPHY_PCS_STATUS,
> QPHY_PCS_AUTONOMOUS_MODE_CTRL,
> QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
> + QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
This is unused
> QPHY_PCS_POWER_DOWN_CONTROL,
> /* Keep last to ensure regs_layout arrays are properly initialized */
> QPHY_LAYOUT_SIZE
> @@ -139,6 +140,97 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
> };
>
> +static const unsigned int usb3phy_regs_layout[] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x17c,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
> +};
This does not look correct. you are yousing QPHY_V3_PCS for the table,
while your register layout corresponds to QPHY_V2_PCS registers.
Please doublecheck this. Also, is there any reason to duplicate
existing qmp_v2_usb3phy_regs_layout or qmp_v3_usb3phy_regs_layout?
> +
> +static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + /* PLL and Loop filter settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + /* SSC settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> +};
> +
> static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
> QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> @@ -1510,6 +1602,10 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
> }
>
> /* list of clocks required by phy */
> +static const char * const ipq9574_phy_clk_l[] = {
> + "aux", "cfg_ahb",
No ref clock?
> +};
> +
> static const char * const msm8996_phy_clk_l[] = {
> "aux", "cfg_ahb", "ref",
> };
> @@ -1558,6 +1654,14 @@ static const char * const qmp_phy_vreg_l[] = {
> "vdda-phy", "vdda-pll",
> };
>
> +static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
> + .serdes = 0,
> + .pcs = 0x800,
> + .pcs_usb = 0x600,
Are you confusing pcs_usb vs pcs_misc? There was no separate pcs_usb on v3 PHYs
> + .tx = 0x200,
> + .rx = 0x400,
> +};
> +
> static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
> .serdes = 0,
> .pcs = 0x0200,
> @@ -1586,6 +1690,28 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
> .regs = qmp_v3_usb3phy_regs_layout,
> };
>
> +static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
> + .lanes = 1,
> +
> + .offsets = &qmp_usb_offsets_ipq9574,
> +
> + .serdes_tbl = ipq9574_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
> + .tx_tbl = ipq9574_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
> + .rx_tbl = ipq9574_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
> + .pcs_tbl = ipq9574_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
> + .clk_list = ipq9574_phy_clk_l,
> + .num_clks = ARRAY_SIZE(ipq9574_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = usb3phy_regs_layout,
> +};
> +
> static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
> .lanes = 1,
>
> @@ -2589,6 +2715,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
> .compatible = "qcom,ipq8074-qmp-usb3-phy",
> .data = &ipq8074_usb3phy_cfg,
> }, {
> + .compatible = "qcom,ipq9574-qmp-usb3-phy",
> + .data = &ipq9574_usb3phy_cfg,
> + }, {
> .compatible = "qcom,msm8996-qmp-usb3-phy",
> .data = &msm8996_usb3phy_cfg,
> }, {
> --
> 2.7.4
>
--
With best wishes
Dmitry
On 27/03/2023 12:30, Varadarajan Narayanan wrote:
> Document the compatible string used for the qusb2 phy in IPQ9574.
>
> Acked-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
>
> ---
> Changes in v4:
> - Remove constraints not applicable to IPQ9574
I don't think this is a correct way to go
> Changes in v3:
> - Maintain the proper sorted order
>
> Changes in v2:
> - Moved ipq6018 to the proper place and placed ipq9574
> next to it as suggested by Dmitry
> ---
> Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> index 7f403e7..3cb27da 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> @@ -18,13 +18,14 @@ properties:
> oneOf:
> - items:
> - enum:
> + - qcom,ipq6018-qusb2-phy
> - qcom,ipq8074-qusb2-phy
> + - qcom,ipq9574-qusb2-phy
> - qcom,msm8953-qusb2-phy
> - qcom,msm8996-qusb2-phy
> - qcom,msm8998-qusb2-phy
> - qcom,qcm2290-qusb2-phy
> - qcom,sdm660-qusb2-phy
> - - qcom,ipq6018-qusb2-phy
> - qcom,sm4250-qusb2-phy
> - qcom,sm6115-qusb2-phy
> - items:
> @@ -157,9 +158,6 @@ required:
> - "#phy-cells"
> - clocks
> - clock-names
> - - vdd-supply
> - - vdda-pll-supply
> - - vdda-phy-dpdm-supply
So, how does ipq9574 power on the PHY?
> - resets
>
> allOf:
--
With best wishes
Dmitry
On 27/03/2023 12:30, Varadarajan Narayanan wrote:
> Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> Changes in v4:
> - Remove constraints not applicable to IPQ9574
> Changes in v3:
> - Update other mandatory fields to accomodate IPQ9574
> Changes in v2:
> - Updated sections missed in previous patch
> ---
> .../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 25 ++++++++++++++++++++--
> 1 file changed, 23 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
> index e81a382..aa5b58c 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
> @@ -21,6 +21,7 @@ properties:
> enum:
> - qcom,ipq6018-qmp-usb3-phy
> - qcom,ipq8074-qmp-usb3-phy
> + - qcom,ipq9574-qmp-usb3-phy
> - qcom,msm8996-qmp-usb3-phy
> - qcom,msm8998-qmp-usb3-phy
> - qcom,qcm2290-qmp-usb3-phy
> @@ -122,8 +123,6 @@ required:
> - clock-names
> - resets
> - reset-names
> - - vdda-phy-supply
> - - vdda-pll-supply
Same questions as for the qusb2 PHY. How is the PHY powered?
>
> additionalProperties: false
>
--
With best wishes
Dmitry
On 27/03/2023 12:30, Varadarajan Narayanan wrote:
> Add the clocks needed for enabling USB in IPQ9574
>
> Acked-by: Stephen Boyd <[email protected]>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> Changes in v2:
> - Fixed coding style issues
> ---
> drivers/clk/qcom/gcc-ipq9574.c | 37 ++++++++++++++++++++++++++++
> include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 ++
> 2 files changed, 39 insertions(+)
Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
On 27/03/2023 12:30, Varadarajan Narayanan wrote:
> Add the phy init sequence for the Super Speed ports found
> on IPQ9574.
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> Changes in v2:
> - Place the entry such that the list continues to be sorted
> ---
> drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
On 27/03/2023 11:30, Varadarajan Narayanan wrote:
> Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> Changes in v4:
> - Remove constraints not applicable to IPQ9574
> Changes in v3:
> - Update other mandatory fields to accomodate IPQ9574
> Changes in v2:
> - Updated sections missed in previous patch
> ---
> .../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 25 ++++++++++++++++++++--
> 1 file changed, 23 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
> index e81a382..aa5b58c 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
> @@ -21,6 +21,7 @@ properties:
> enum:
> - qcom,ipq6018-qmp-usb3-phy
> - qcom,ipq8074-qmp-usb3-phy
> + - qcom,ipq9574-qmp-usb3-phy
> - qcom,msm8996-qmp-usb3-phy
> - qcom,msm8998-qmp-usb3-phy
> - qcom,qcm2290-qmp-usb3-phy
> @@ -122,8 +123,6 @@ required:
> - clock-names
> - resets
> - reset-names
> - - vdda-phy-supply
> - - vdda-pll-supply
>
> additionalProperties: false
>
> @@ -204,6 +203,28 @@ allOf:
> compatible:
> contains:
> enum:
> + - qcom,ipq9574-qmp-usb3-phy
> + then:
> + properties:
> + clocks:
> + maxItems: 3
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: pipe
Isn't pipe the clock for child node?
Best regards,
Krzysztof
On 27/03/2023 11:30, Varadarajan Narayanan wrote:
> Add USB phy and controller related nodes
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> Changes in v4:
> - Use newer bindings without subnodes
> - Fix coding style issues
>
> Changes in v3:
> - Insert the nodes at proper location
>
> Changes in v2:
> - Fixed issues flagged by Krzysztof
> - Fix issues reported by make dtbs_check
> - Remove NOC related clocks (to be added with proper
> interconnect support)
> ---
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 83 +++++++++++++++++++++++++++++++++++
> 1 file changed, 83 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 2bb4053..5379c25 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -215,6 +215,45 @@
> #size-cells = <1>;
> ranges = <0 0 0 0xffffffff>;
>
> + qusb_phy_0: phy@7b000 {
> + compatible = "qcom,ipq9574-qusb2-phy";
> + reg = <0x0007b000 0x180>;
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> + <&xo_board_clk>;
> + clock-names = "cfg_ahb",
> + "ref";
> +
> + resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> + status = "disabled";
> + };
> +
> + ssphy_0: phy@7d000 {
> + compatible = "qcom,ipq9574-qmp-usb3-phy";
> + reg = <0x0007d000 0xa00>;
> + #clock-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
Why do you need these three?
> +
> + clocks = <&gcc GCC_USB0_AUX_CLK>,
> + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> + <&gcc GCC_USB0_PIPE_CLK>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "pipe";
> +
> + resets = <&gcc GCC_USB0_PHY_BCR>,
> + <&gcc GCC_USB3PHY_0_PHY_BCR>;
> + reset-names = "phy",
> + "common";
> + status = "disabled";
> +
> + #phy-cells = <0>;
> + clock-output-names = "usb0_pipe_clk";
Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).
> + };
> +
> pcie0_phy: phy@84000 {
> compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> reg = <0x00084000 0x1bc>; /* Serdes PLL */
> @@ -436,6 +475,50 @@
> status = "disabled";
> };
>
> + usb3: usb3@8a00000 {
usb@
> + compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
> + reg = <0x08af8800 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_SNOC_USB_CLK>,
> + <&gcc GCC_ANOC_USB_AXI_CLK>,
> + <&gcc GCC_USB0_MASTER_CLK>,
> + <&gcc GCC_USB0_SLEEP_CLK>,
> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> +
> + clock-names = "sys_noc_axi",
> + "anoc_axi",
> + "master",
> + "sleep",
> + "mock_utmi";
> +
> + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> + assigned-clock-rates = <200000000>,
> + <24000000>;
> +
> + resets = <&gcc GCC_USB_BCR>;
> + status = "disabled";
> +
> + dwc_0: usb@8a00000 {
> + compatible = "snps,dwc3";
> + reg = <0x8a00000 0xcd00>;
> + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> + clock-names = "ref";
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&qusb_phy_0>, <&ssphy_0>;
> + phy-names = "usb2-phy", "usb3-phy";
> + tx-fifo-resize;
> + snps,is-utmi-l1-suspend;
> + snps,hird-threshold = /bits/ 8 <0x0>;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_u3_susphy_quirk;
> + dr_mode = "host";
Are you saying that peripheral mode cannot work on this USB controller?
Never?
Best regards,
Krzysztof
On 27/03/2023 11:30, Varadarajan Narayanan wrote:
> Document the IPQ9574 dwc3 compatible.
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> Changes in v4:
> - Update other relevant sections
> - Remove constraints not applicable to IPQ9574
No, that's not way to go. These are required.
> ---
> .../devicetree/bindings/usb/qcom,dwc3.yaml | 22 +++++++++++++++++++---
> 1 file changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> index a2aabda..3fc8c3c 100644
> --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> @@ -17,6 +17,7 @@ properties:
> - qcom,ipq6018-dwc3
> - qcom,ipq8064-dwc3
> - qcom,ipq8074-dwc3
> + - qcom,ipq9574-dwc3
> - qcom,msm8953-dwc3
> - qcom,msm8994-dwc3
> - qcom,msm8996-dwc3
> @@ -132,11 +133,8 @@ required:
> - "#address-cells"
> - "#size-cells"
> - ranges
> - - power-domains
> - clocks
> - clock-names
> - - interrupts
> - - interrupt-names
>
> allOf:
> - if:
> @@ -242,6 +240,24 @@ allOf:
> compatible:
> contains:
> enum:
> + - qcom,ipq9574-dwc3
> + then:
> + properties:
> + clocks:
> + maxItems: 5
> + clock-names:
> + items:
> + - const: sys_noc_axi
> + - const: anoc_axi
Heh, do we really need entirely different clock names for each new variant?
Best regards,
Krzysztof
On Mon, Mar 27, 2023 at 01:02:52PM +0300, Dmitry Baryshkov wrote:
> On 27/03/2023 12:30, Varadarajan Narayanan wrote:
> >Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574
> >
> >Signed-off-by: Varadarajan Narayanan <[email protected]>
> >---
> > Changes in v4:
> > - Remove constraints not applicable to IPQ9574
> > Changes in v3:
> > - Update other mandatory fields to accomodate IPQ9574
> > Changes in v2:
> > - Updated sections missed in previous patch
> >---
> > .../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 25 ++++++++++++++++++++--
> > 1 file changed, 23 insertions(+), 2 deletions(-)
> >
> >diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
> >index e81a382..aa5b58c 100644
> >--- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
> >+++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
> >@@ -21,6 +21,7 @@ properties:
> > enum:
> > - qcom,ipq6018-qmp-usb3-phy
> > - qcom,ipq8074-qmp-usb3-phy
> >+ - qcom,ipq9574-qmp-usb3-phy
> > - qcom,msm8996-qmp-usb3-phy
> > - qcom,msm8998-qmp-usb3-phy
> > - qcom,qcm2290-qmp-usb3-phy
> >@@ -122,8 +123,6 @@ required:
> > - clock-names
> > - resets
> > - reset-names
> >- - vdda-phy-supply
> >- - vdda-pll-supply
>
> Same questions as for the qusb2 PHY. How is the PHY powered?
It is powered by always on regulators. Will create fixed
regulators and assign them to these.
Thanks
Varada
> > additionalProperties: false
>
> --
> With best wishes
> Dmitry
>
On Tue, Mar 28, 2023 at 09:07:08AM +0200, Krzysztof Kozlowski wrote:
> On 27/03/2023 11:30, Varadarajan Narayanan wrote:
> > Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574
> >
> > Signed-off-by: Varadarajan Narayanan <[email protected]>
> > ---
> > Changes in v4:
> > - Remove constraints not applicable to IPQ9574
> > Changes in v3:
> > - Update other mandatory fields to accomodate IPQ9574
> > Changes in v2:
> > - Updated sections missed in previous patch
> > ---
> > .../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 25 ++++++++++++++++++++--
> > 1 file changed, 23 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
> > index e81a382..aa5b58c 100644
> > --- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
> > @@ -21,6 +21,7 @@ properties:
> > enum:
> > - qcom,ipq6018-qmp-usb3-phy
> > - qcom,ipq8074-qmp-usb3-phy
> > + - qcom,ipq9574-qmp-usb3-phy
> > - qcom,msm8996-qmp-usb3-phy
> > - qcom,msm8998-qmp-usb3-phy
> > - qcom,qcm2290-qmp-usb3-phy
> > @@ -122,8 +123,6 @@ required:
> > - clock-names
> > - resets
> > - reset-names
> > - - vdda-phy-supply
> > - - vdda-pll-supply
> >
> > additionalProperties: false
> >
> > @@ -204,6 +203,28 @@ allOf:
> > compatible:
> > contains:
> > enum:
> > + - qcom,ipq9574-qmp-usb3-phy
> > + then:
> > + properties:
> > + clocks:
> > + maxItems: 3
> > + clock-names:
> > + items:
> > + - const: aux
> > + - const: cfg_ahb
> > + - const: pipe
>
> Isn't pipe the clock for child node?
Will be moving to a newer style binding (as specified in
qcom,sc8280xp-qmp-usb3-uni-phy.yaml). Will update accordingly
and post the patch.
Thanks
Varada
> Best regards,
> Krzysztof
>
On Tue, Mar 28, 2023 at 09:11:38AM +0200, Krzysztof Kozlowski wrote:
> On 27/03/2023 11:30, Varadarajan Narayanan wrote:
> > Document the IPQ9574 dwc3 compatible.
> >
> > Signed-off-by: Varadarajan Narayanan <[email protected]>
> > ---
> > Changes in v4:
> > - Update other relevant sections
> > - Remove constraints not applicable to IPQ9574
>
> No, that's not way to go. These are required.
Yes. Misinterpreted an earlier comment.
Will fix this.
> > ---
> > .../devicetree/bindings/usb/qcom,dwc3.yaml | 22 +++++++++++++++++++---
> > 1 file changed, 19 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> > index a2aabda..3fc8c3c 100644
> > --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> > +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> > @@ -17,6 +17,7 @@ properties:
> > - qcom,ipq6018-dwc3
> > - qcom,ipq8064-dwc3
> > - qcom,ipq8074-dwc3
> > + - qcom,ipq9574-dwc3
> > - qcom,msm8953-dwc3
> > - qcom,msm8994-dwc3
> > - qcom,msm8996-dwc3
> > @@ -132,11 +133,8 @@ required:
> > - "#address-cells"
> > - "#size-cells"
> > - ranges
> > - - power-domains
> > - clocks
> > - clock-names
> > - - interrupts
> > - - interrupt-names
> >
> > allOf:
> > - if:
> > @@ -242,6 +240,24 @@ allOf:
> > compatible:
> > contains:
> > enum:
> > + - qcom,ipq9574-dwc3
> > + then:
> > + properties:
> > + clocks:
> > + maxItems: 5
> > + clock-names:
> > + items:
> > + - const: sys_noc_axi
> > + - const: anoc_axi
>
> Heh, do we really need entirely different clock names for each new variant?
Will fix and post a new patch.
Thanks
Varada
> Best regards,
> Krzysztof
>
On Mon, Mar 27, 2023 at 12:57:36PM +0300, Dmitry Baryshkov wrote:
> On Mon, 27 Mar 2023 at 12:32, Varadarajan Narayanan
> <[email protected]> wrote:
> >
> > Updated USB QMP PHY Init sequence based on HPG for IPQ9574.
> > Reused clock and reset list from existing targets.
> >
> > Signed-off-by: Praveenkumar I <[email protected]>
> > Signed-off-by: Varadarajan Narayanan <[email protected]>
> > ---
> > Changes in v4:
> > - Use qmp_usb_offsets for register space access
> > Changes in v3:
> > - Fix hex captitalization
> > Changes in v2:
> > - Removed unused phy register offsets
> > - Moved the clock entries to the correct place
> > - Maintain sorted order
> > ---
> > drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 129 ++++++++++++++++++++++++++++++++
> > 1 file changed, 129 insertions(+)
> >
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > index a49711c..ed5f794 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > @@ -94,6 +94,7 @@ enum qphy_reg_layout {
> > QPHY_PCS_STATUS,
> > QPHY_PCS_AUTONOMOUS_MODE_CTRL,
> > QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
> > + QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
>
> This is unused
Will remove.
> > QPHY_PCS_POWER_DOWN_CONTROL,
> > /* Keep last to ensure regs_layout arrays are properly initialized */
> > QPHY_LAYOUT_SIZE
> > @@ -139,6 +140,97 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> > [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
> > };
> >
> > +static const unsigned int usb3phy_regs_layout[] = {
> > + [QPHY_SW_RESET] = 0x00,
> > + [QPHY_START_CTRL] = 0x08,
> > + [QPHY_PCS_STATUS] = 0x17c,
> > + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
> > + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
> > + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
> > +};
>
> This does not look correct. you are yousing QPHY_V3_PCS for the table,
> while your register layout corresponds to QPHY_V2_PCS registers.
> Please doublecheck this. Also, is there any reason to duplicate
> existing qmp_v2_usb3phy_regs_layout or qmp_v3_usb3phy_regs_layout?
Will check on this and post a new patch.
> > +
> > +static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> > + /* PLL and Loop filter settings */
> > + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> > + /* SSC settings */
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> > + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> > + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> > +};
> > +
> > static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
> > QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> > QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> > @@ -1510,6 +1602,10 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
> > }
> >
> > /* list of clocks required by phy */
> > +static const char * const ipq9574_phy_clk_l[] = {
> > + "aux", "cfg_ahb",
>
> No ref clock?
Will see if i can use msm8996_phy_clk_l itself.
> > +};
> > +
> > static const char * const msm8996_phy_clk_l[] = {
> > "aux", "cfg_ahb", "ref",
> > };
> > @@ -1558,6 +1654,14 @@ static const char * const qmp_phy_vreg_l[] = {
> > "vdda-phy", "vdda-pll",
> > };
> >
> > +static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
> > + .serdes = 0,
> > + .pcs = 0x800,
> > + .pcs_usb = 0x600,
>
> Are you confusing pcs_usb vs pcs_misc? There was no separate pcs_usb on v3 PHYs
Yes, my mistake. Will fix this.
Thanks
Varada
> > + .tx = 0x200,
> > + .rx = 0x400,
> > +};
> > +
> > static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
> > .serdes = 0,
> > .pcs = 0x0200,
> > @@ -1586,6 +1690,28 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
> > .regs = qmp_v3_usb3phy_regs_layout,
> > };
> >
> > +static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
> > + .lanes = 1,
> > +
> > + .offsets = &qmp_usb_offsets_ipq9574,
> > +
> > + .serdes_tbl = ipq9574_usb3_serdes_tbl,
> > + .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
> > + .tx_tbl = ipq9574_usb3_tx_tbl,
> > + .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
> > + .rx_tbl = ipq9574_usb3_rx_tbl,
> > + .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
> > + .pcs_tbl = ipq9574_usb3_pcs_tbl,
> > + .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
> > + .clk_list = ipq9574_phy_clk_l,
> > + .num_clks = ARRAY_SIZE(ipq9574_phy_clk_l),
> > + .reset_list = msm8996_usb3phy_reset_l,
> > + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> > + .vreg_list = qmp_phy_vreg_l,
> > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> > + .regs = usb3phy_regs_layout,
> > +};
> > +
> > static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
> > .lanes = 1,
> >
> > @@ -2589,6 +2715,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
> > .compatible = "qcom,ipq8074-qmp-usb3-phy",
> > .data = &ipq8074_usb3phy_cfg,
> > }, {
> > + .compatible = "qcom,ipq9574-qmp-usb3-phy",
> > + .data = &ipq9574_usb3phy_cfg,
> > + }, {
> > .compatible = "qcom,msm8996-qmp-usb3-phy",
> > .data = &msm8996_usb3phy_cfg,
> > }, {
> > --
> > 2.7.4
> >
>
>
> --
> With best wishes
> Dmitry
On Tue, Mar 28, 2023 at 09:09:09AM +0200, Krzysztof Kozlowski wrote:
> On 27/03/2023 11:30, Varadarajan Narayanan wrote:
> > Add USB phy and controller related nodes
> >
> > Signed-off-by: Varadarajan Narayanan <[email protected]>
> > ---
> > Changes in v4:
> > - Use newer bindings without subnodes
> > - Fix coding style issues
> >
> > Changes in v3:
> > - Insert the nodes at proper location
> >
> > Changes in v2:
> > - Fixed issues flagged by Krzysztof
> > - Fix issues reported by make dtbs_check
> > - Remove NOC related clocks (to be added with proper
> > interconnect support)
> > ---
> > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 83 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 83 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > index 2bb4053..5379c25 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > @@ -215,6 +215,45 @@
> > #size-cells = <1>;
> > ranges = <0 0 0 0xffffffff>;
> >
> > + qusb_phy_0: phy@7b000 {
> > + compatible = "qcom,ipq9574-qusb2-phy";
> > + reg = <0x0007b000 0x180>;
> > + #phy-cells = <0>;
> > +
> > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > + <&xo_board_clk>;
> > + clock-names = "cfg_ahb",
> > + "ref";
> > +
> > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> > + status = "disabled";
> > + };
> > +
> > + ssphy_0: phy@7d000 {
> > + compatible = "qcom,ipq9574-qmp-usb3-phy";
> > + reg = <0x0007d000 0xa00>;
> > + #clock-cells = <1>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
>
> Why do you need these three?
Don't need these. Have moved to qcom,sc8280xp-qmp-usb3-uni-phy.yaml
specification instead of qcom,msm8996-qmp-usb3-phy.yaml. Will
update accordingly and post.
> > +
> > + clocks = <&gcc GCC_USB0_AUX_CLK>,
> > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > + <&gcc GCC_USB0_PIPE_CLK>;
> > + clock-names = "aux",
> > + "cfg_ahb",
> > + "pipe";
> > +
> > + resets = <&gcc GCC_USB0_PHY_BCR>,
> > + <&gcc GCC_USB3PHY_0_PHY_BCR>;
> > + reset-names = "phy",
> > + "common";
> > + status = "disabled";
> > +
> > + #phy-cells = <0>;
> > + clock-output-names = "usb0_pipe_clk";
>
> Does not look like you tested the DTS against bindings. Please run `make
> dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
> for instructions).
Have addressed these and have created a new patch. Will post it
shortly. IPQ9574 doesn't have any power domains, hence don't have
power-domains entry in the DT node. make dtbs_check is giving the
following messages hope that is ok
/local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property
From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
/local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property
From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
>
> > + };
> > +
> > pcie0_phy: phy@84000 {
> > compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> > reg = <0x00084000 0x1bc>; /* Serdes PLL */
> > @@ -436,6 +475,50 @@
> > status = "disabled";
> > };
> >
> > + usb3: usb3@8a00000 {
>
> usb@
Will fix.
> > + compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
> > + reg = <0x08af8800 0x400>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
>
>
>
> > +
> > + clocks = <&gcc GCC_SNOC_USB_CLK>,
> > + <&gcc GCC_ANOC_USB_AXI_CLK>,
> > + <&gcc GCC_USB0_MASTER_CLK>,
> > + <&gcc GCC_USB0_SLEEP_CLK>,
> > + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> > +
> > + clock-names = "sys_noc_axi",
> > + "anoc_axi",
> > + "master",
> > + "sleep",
> > + "mock_utmi";
> > +
> > + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
> > + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> > + assigned-clock-rates = <200000000>,
> > + <24000000>;
> > +
> > + resets = <&gcc GCC_USB_BCR>;
> > + status = "disabled";
> > +
> > + dwc_0: usb@8a00000 {
> > + compatible = "snps,dwc3";
> > + reg = <0x8a00000 0xcd00>;
> > + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> > + clock-names = "ref";
> > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> > + phys = <&qusb_phy_0>, <&ssphy_0>;
> > + phy-names = "usb2-phy", "usb3-phy";
> > + tx-fifo-resize;
> > + snps,is-utmi-l1-suspend;
> > + snps,hird-threshold = /bits/ 8 <0x0>;
> > + snps,dis_u2_susphy_quirk;
> > + snps,dis_u3_susphy_quirk;
> > + dr_mode = "host";
>
> Are you saying that peripheral mode cannot work on this USB controller?
> Never?
Will move to board DTS.
Thanks
Varada
> Best regards,
> Krzysztof
>
On 30/03/2023 09:10, Varadarajan Narayanan wrote:
> On Mon, Mar 27, 2023 at 01:02:52PM +0300, Dmitry Baryshkov wrote:
>> On 27/03/2023 12:30, Varadarajan Narayanan wrote:
>>> Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574
>>>
>>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>>> ---
>>> Changes in v4:
>>> - Remove constraints not applicable to IPQ9574
>>> Changes in v3:
>>> - Update other mandatory fields to accomodate IPQ9574
>>> Changes in v2:
>>> - Updated sections missed in previous patch
>>> ---
>>> .../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 25 ++++++++++++++++++++--
>>> 1 file changed, 23 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
>>> index e81a382..aa5b58c 100644
>>> --- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
>>> +++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
>>> @@ -21,6 +21,7 @@ properties:
>>> enum:
>>> - qcom,ipq6018-qmp-usb3-phy
>>> - qcom,ipq8074-qmp-usb3-phy
>>> + - qcom,ipq9574-qmp-usb3-phy
>>> - qcom,msm8996-qmp-usb3-phy
>>> - qcom,msm8998-qmp-usb3-phy
>>> - qcom,qcm2290-qmp-usb3-phy
>>> @@ -122,8 +123,6 @@ required:
>>> - clock-names
>>> - resets
>>> - reset-names
>>> - - vdda-phy-supply
>>> - - vdda-pll-supply
>>
>> Same questions as for the qusb2 PHY. How is the PHY powered?
>
> It is powered by always on regulators. Will create fixed
> regulators and assign them to these.
always-on where? in DTS? Then it is not really related to this patch...
or you meant always-on power domains? Yet still device has power supplies.
Best regards,
Krzysztof