I notice that many net drivers set rx_copybreak to 1518 (the max packet size)
for non-i386 architectures. Once I thought I understood it and it seems
related to cache line alignment. However, I am not sure exactly about the
reason now. Can someone enlighten me a little bit?
Basically I try to understand whether for MIPS architectures we need to set
this value as well.
Please CC your reply to my email address.
TIA.
Jun
Jun Sun writes:
> I notice that many net drivers set rx_copybreak to 1518 (the max packet size)
> for non-i386 architectures. Once I thought I understood it and it seems
> related to cache line alignment. However, I am not sure exactly about the
> reason now. Can someone enlighten me a little bit?
Most non-x86 architectures take a large hit for unaligned accesses.
If the ethernet chip cannot land the beginning of the packet at an
arbitrary byte offset (a modulo 2 offset for ethernet is needed for an
aligned IP header) then the rx_copybreak is set to the ethernet MTU
so that all packets get copied into new buffers where they can have
their header aligned.
Later,
David S. Miller
[email protected]
> for non-i386 architectures. Once I thought I understood it and it seems
> related to cache line alignment. However, I am not sure exactly about the
> reason now. Can someone enlighten me a little bit?
A lot of pci net cards can only start packets on a 4 byte boundary. A lot
of CPU's need 4 byte aligned read/writes for performance. The ethernet header
is howerver 14 bytes long.
For CPU's with poor unaligned performance it turns out better to copy or
copy/checksum the data so the IP/TCP headers are aligned. If the card can
hit 16bit boundaries then you will see card drivers doing
alloc_skb(blah)
skb_reserve(skb, 2);
to align the header of he buffer so that the IP data is aligned