Hello kernel listees
I have a busmaster question I am hoping you can help me with.
If a PCI device is acting as a busmaster and the processor initiates a
read/write to another device on the PCI bus while the busmater-device is in
control of the bus what happens to the instructions initiated by the
processor? Are they never seen by the device that the processor
is trying to read/write?
Thanks for helping me with this,
Daniel
_________________________________________________________________
Get your FREE download of MSN Explorer at http://explorer.msn.com
On Sat, Apr 28, 2001 at 01:27:30AM -0500, daniel sheltraw wrote:
> I have a busmaster question I am hoping you can help me with.
> If a PCI device is acting as a busmaster and the processor initiates a
> read/write to another device on the PCI bus while the busmater-device is in
> control of the bus what happens to the instructions initiated by the
> processor? Are they never seen by the device that the processor
> is trying to read/write?
The access by the processor is delayed until the PCI arbiter allows the
CPU access to the PCI bus (how long depends on all sorts of things which
I won't go into, but its not necessarily held off until the end of the
busmaster transfer).
--
Russell King ([email protected]) The developer of ARM Linux
http://www.arm.linux.org.uk/personal/aboutme.html
daniel sheltraw wrote:
> Hello kernel listees
>
> I have a busmaster question I am hoping you can help me with.
> If a PCI device is acting as a busmaster and the processor initiates a
> read/write to another device on the PCI bus while the busmater-device is in
> control of the bus what happens to the instructions initiated by the
> processor? Are they never seen by the device that the processor
> is trying to read/write?
An excellent book about PCI is Mindshare's "PCI System Architecture"
Third (or later?) Edition.
In the scenerio you outlined, the device currently holding the bus
would continue until it's latency timer expired (if it already hadn't),
stalling the CPU,
then the master which has been granted access next to the bus would
start it's access. If the only other master requesting access is the CPU,
then it will get it. If there are others, then it is implementation dependent
who has highest arbitration priority.
Note that since main memory is not on the PCI bus, the CPU can cary on
unless it tries to access video memory, IDE registers, etc. for IO.