Hi Wei/Rob,
Now that all USB and PCI/PHY drivers/patches were upstreamed, the only
remaining bits for USB to work on both HiKey 960 and HiKey 970 and
for PCI to work on HiKey 970 are the devicetree logic.
Those patches add them.
Please apply.
Regards,
Mauro
John Stultz (1):
arm64: dts: HiSilicon: Add usb mux hub for HiKey 960
Manivannan Sadhasivam (1):
arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller
hardware
Mauro Carvalho Chehab (2):
arm64: dts: HiSilicon: Add support for HiKey 970 USB3 PHY
arm64: dts: HiSilicon: Add usb mux hub for HiKey 970
Yu Chen (1):
dt-bindings: misc: add schema for USB hub on Kirin devices
.../bindings/misc/hisilicon,hikey-usb.yaml | 87 ++++++++++
.../boot/dts/hisilicon/hi3660-hikey960.dts | 35 +++-
.../boot/dts/hisilicon/hi3670-hikey970.dts | 106 ++++++++++++
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 163 ++++++++++++++++++
4 files changed, 389 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/misc/hisilicon,hikey-usb.yaml
--
2.33.1
From: Manivannan Sadhasivam <[email protected]>
Add DTS bindings for the HiKey 970 board's PCIe hardware.
Co-developed-by: Mauro Carvalho Chehab <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
---
To mailbombing on a large number of people, only mailing lists were C/C on the cover.
See [PATCH 0/5] at: https://lore.kernel.org/all/[email protected]/
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 107 ++++++++++++++++++++++
1 file changed, 107 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 636c8817df7e..225dccbcb064 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -176,6 +176,12 @@ sctrl: sctrl@fff0a000 {
#clock-cells = <1>;
};
+ pmctrl: pmctrl@fff31000 {
+ compatible = "hisilicon,hi3670-pmctrl", "syscon";
+ reg = <0x0 0xfff31000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
iomcu: iomcu@ffd7e000 {
compatible = "hisilicon,hi3670-iomcu", "syscon";
reg = <0x0 0xffd7e000 0x0 0x1000>;
@@ -659,6 +665,107 @@ gpio28: gpio@fff1d000 {
clock-names = "apb_pclk";
};
+ pcie_phy: pcie-phy@fc000000 {
+ compatible = "hisilicon,hi970-pcie-phy";
+ reg = <0x0 0xfc000000 0x0 0x80000>;
+
+ phy-supply = <&ldo33>;
+
+ clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>,
+ <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3670_ACLK_GATE_PCIE>;
+ clock-names = "phy_ref", "aux",
+ "apb_phy", "apb_sys",
+ "aclk";
+
+ /* vboost iboost pre post main */
+ hisilicon,eye-diagram-param = <0xffffffff 0xffffffff
+ 0xffffffff 0xffffffff
+ 0xffffffff>;
+
+ #phy-cells = <0>;
+ };
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin970-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000000>,
+ <0x0 0xfc180000 0x0 0x1000>,
+ <0x0 0xf5000000 0x0 0x2000>;
+ reg-names = "dbi", "apb", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ phys = <&pcie_phy>;
+ ranges = <0x02000000 0x0 0x00000000
+ 0x0 0xf6000000
+ 0x0 0x02000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0x0 0 0 1
+ &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 2
+ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 3
+ &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 4
+ &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ reset-gpios = <&gpio7 0 0>;
+ hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>,
+ <&gpio20 6 0>;
+ pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0
+ reg = <0 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ pcie@0,0 { // Lane 0: upstream
+ reg = <0 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ pcie@1,0 { // Lane 4: M.2
+ reg = <0x0800 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reset-gpios = <&gpio3 1 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+
+ pcie@5,0 { // Lane 5: Mini PCIe
+ reg = <0x2800 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reset-gpios = <&gpio27 4 0 >;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+
+ pcie@7,0 { // Lane 6: Ethernet
+ reg = <0x3800 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reset-gpios = <&gpio25 2 0 >;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+ };
+ };
+
/* UFS */
ufs: ufs@ff3c0000 {
compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
--
2.33.1
Hi Mauro,
On 2021/11/16 19:59, Mauro Carvalho Chehab wrote:
> From: Manivannan Sadhasivam <[email protected]>
>
> Add DTS bindings for the HiKey 970 board's PCIe hardware.
>
> Co-developed-by: Mauro Carvalho Chehab <[email protected]>
> Signed-off-by: Manivannan Sadhasivam <[email protected]>
> Signed-off-by: Mauro Carvalho Chehab <[email protected]>
> ---
>
> To mailbombing on a large number of people, only mailing lists were C/C on the cover.
> See [PATCH 0/5] at: https://lore.kernel.org/all/[email protected]/
>
> arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 107 ++++++++++++++++++++++
> 1 file changed, 107 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> index 636c8817df7e..225dccbcb064 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> @@ -176,6 +176,12 @@ sctrl: sctrl@fff0a000 {
> #clock-cells = <1>;
> };
>
> + pmctrl: pmctrl@fff31000 {
> + compatible = "hisilicon,hi3670-pmctrl", "syscon";
The "hi3670-pmctrl" is not documented in the devicetree binding documents yet.
Could we remove this part this time?
Thanks!
Best Regards,
Wei
Add a compatible for the Power Management domain controller,
which is needed in order to control power for the PCI devices
on HiKey 970.
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
---
Documentation/devicetree/bindings/clock/hi3670-clock.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/hi3670-clock.txt b/Documentation/devicetree/bindings/clock/hi3670-clock.txt
index 66f3697eca78..8e9f12a3ba5b 100644
--- a/Documentation/devicetree/bindings/clock/hi3670-clock.txt
+++ b/Documentation/devicetree/bindings/clock/hi3670-clock.txt
@@ -15,6 +15,7 @@ Required Properties:
- "hisilicon,hi3670-iomcu"
- "hisilicon,hi3670-media1-crg"
- "hisilicon,hi3670-media2-crg"
+ - "hisilicon,hi3670-pmctrl"
- reg: physical base address of the controller and length of memory mapped
region.
--
2.33.1
Em Tue, 7 Dec 2021 16:09:16 +0800
Wei Xu <[email protected]> escreveu:
> Hi Mauro,
>
> On 2021/11/16 19:59, Mauro Carvalho Chehab wrote:
> > From: Manivannan Sadhasivam <[email protected]>
> >
> > Add DTS bindings for the HiKey 970 board's PCIe hardware.
> >
> > Co-developed-by: Mauro Carvalho Chehab <[email protected]>
> > Signed-off-by: Manivannan Sadhasivam <[email protected]>
> > Signed-off-by: Mauro Carvalho Chehab <[email protected]>
> > ---
> >
> > To mailbombing on a large number of people, only mailing lists were C/C on the cover.
> > See [PATCH 0/5] at: https://lore.kernel.org/all/[email protected]/
> >
> > arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 107 ++++++++++++++++++++++
> > 1 file changed, 107 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> > index 636c8817df7e..225dccbcb064 100644
> > --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> > +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> > @@ -176,6 +176,12 @@ sctrl: sctrl@fff0a000 {
> > #clock-cells = <1>;
> > };
> >
> > + pmctrl: pmctrl@fff31000 {
> > + compatible = "hisilicon,hi3670-pmctrl", "syscon";
>
> The "hi3670-pmctrl" is not documented in the devicetree binding documents yet.
> Could we remove this part this time?
Without that, the PCI PHY won't work.
IMO, the best would be to just add this compatible to hi3670-clock,
where it belongs.
Just sent a patch.
Regards,
Mauro
Hi Mauro,
On 2021/12/7 16:39, Mauro Carvalho Chehab wrote:
> Em Tue, 7 Dec 2021 16:09:16 +0800
> Wei Xu <[email protected]> escreveu:
>
>> Hi Mauro,
>>
>> On 2021/11/16 19:59, Mauro Carvalho Chehab wrote:
>>> From: Manivannan Sadhasivam <[email protected]>
>>>
>>> Add DTS bindings for the HiKey 970 board's PCIe hardware.
>>>
>>> Co-developed-by: Mauro Carvalho Chehab <[email protected]>
>>> Signed-off-by: Manivannan Sadhasivam <[email protected]>
>>> Signed-off-by: Mauro Carvalho Chehab <[email protected]>
>>> ---
>>>
>>> To mailbombing on a large number of people, only mailing lists were C/C on the cover.
>>> See [PATCH 0/5] at: https://lore.kernel.org/all/[email protected]/
>>>
>>> arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 107 ++++++++++++++++++++++
>>> 1 file changed, 107 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
>>> index 636c8817df7e..225dccbcb064 100644
>>> --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
>>> +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
>>> @@ -176,6 +176,12 @@ sctrl: sctrl@fff0a000 {
>>> #clock-cells = <1>;
>>> };
>>>
>>> + pmctrl: pmctrl@fff31000 {
>>> + compatible = "hisilicon,hi3670-pmctrl", "syscon";
>>
>> The "hi3670-pmctrl" is not documented in the devicetree binding documents yet.
>> Could we remove this part this time?
>
> Without that, the PCI PHY won't work.
>
> IMO, the best would be to just add this compatible to hi3670-clock,
> where it belongs.
>
> Just sent a patch.
Got it.
Thanks!
Best Regards,
Wei
>
> Regards,
> Mauro
>
> .
>