LinuxLists.cc - [RFC PATCH v2 0/8] Add support for 10G Ethernet SerDes on MT7988

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Subject: [RFC PATCH v2 3/8] net: pcs: pcs-mtk-lynxi: add platform driver for MT7988

Introduce a proper platform MFD driver for the LynxI (H)SGMII PCS which
is going to initially be used for the MT7988 SoC.

Signed-off-by: Daniel Golle <[email protected]>
---
drivers/net/pcs/pcs-mtk-lynxi.c | 170 ++++++++++++++++++++++++++++--
include/linux/pcs/pcs-mtk-lynxi.h | 1 +
2 files changed, 160 insertions(+), 11 deletions(-)

diff --git a/drivers/net/pcs/pcs-mtk-lynxi.c b/drivers/net/pcs/pcs-mtk-lynxi.c
index 8501dd365279b..558d6351399b5 100644
--- a/drivers/net/pcs/pcs-mtk-lynxi.c
+++ b/drivers/net/pcs/pcs-mtk-lynxi.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018-2019 MediaTek Inc.
-/* A library for MediaTek SGMII circuit
+/* A library and platform driver for the MediaTek LynxI SGMII circuit
*
* Author: Sean Wang <[email protected]>
* Author: Alexander Couzens <[email protected]>
@@ -8,11 +8,16 @@
*
*/

+#include <linux/clk.h>
#include <linux/mdio.h>
+#include <linux/mfd/syscon.h>
#include <linux/of.h>
+#include <linux/of_platform.h>
#include <linux/pcs/pcs-mtk-lynxi.h>
#include <linux/phylink.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include <linux/reset.h>

/* SGMII subsystem config registers */
/* BMCR (low 16) BMSR (high 16) */
@@ -65,6 +70,8 @@
#define SGMII_PN_SWAP_MASK GENMASK(1, 0)
#define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1))

+#define MTK_NETSYS_V3_AMA_RGC3 0x128
+
/* struct mtk_pcs_lynxi - This structure holds each sgmii regmap andassociated
* data
* @regmap: The register map pointing at the range used to setup
@@ -81,6 +88,10 @@ struct mtk_pcs_lynxi {
phy_interface_t interface;
struct phylink_pcs pcs;
u32 flags;
+ struct reset_control *rstc;
+ struct clk *sgmii_sel;
+ struct clk *sgmii_rx;
+ struct clk *sgmii_tx;
};

static struct mtk_pcs_lynxi *pcs_to_mtk_pcs_lynxi(struct phylink_pcs *pcs)
@@ -102,6 +113,17 @@ static void mtk_pcs_lynxi_get_state(struct phylink_pcs *pcs,
FIELD_GET(SGMII_LPA, adv));
}

+static void mtk_sgmii_reset(struct mtk_pcs_lynxi *mpcs)
+{
+ if (!mpcs->rstc)
+ return;
+
+ reset_control_assert(mpcs->rstc);
+ usleep_range(100, 500);
+ reset_control_deassert(mpcs->rstc);
+ mdelay(10);
+}
+
static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
phy_interface_t interface,
const unsigned long *advertising,
@@ -147,6 +169,7 @@ static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
SGMII_PHYA_PWD);

/* Reset SGMII PCS state */
+ mtk_sgmii_reset(mpcs);
regmap_set_bits(mpcs->regmap, SGMSYS_RESERVED_0,
SGMII_SW_RESET);

@@ -233,10 +256,29 @@ static void mtk_pcs_lynxi_link_up(struct phylink_pcs *pcs,
}
}

+static int mtk_pcs_lynxi_enable(struct phylink_pcs *pcs)
+{
+ struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
+
+ if (mpcs->sgmii_tx && mpcs->sgmii_rx) {
+ clk_prepare_enable(mpcs->sgmii_rx);
+ clk_prepare_enable(mpcs->sgmii_tx);
+ }
+
+ return 0;
+}
+
static void mtk_pcs_lynxi_disable(struct phylink_pcs *pcs)
{
struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);

+ regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
+
+ if (mpcs->sgmii_tx && mpcs->sgmii_rx) {
+ clk_disable_unprepare(mpcs->sgmii_tx);
+ clk_disable_unprepare(mpcs->sgmii_rx);
+ }
+
mpcs->interface = PHY_INTERFACE_MODE_NA;
}

@@ -246,11 +288,12 @@ static const struct phylink_pcs_ops mtk_pcs_lynxi_ops = {
.pcs_an_restart = mtk_pcs_lynxi_restart_an,
.pcs_link_up = mtk_pcs_lynxi_link_up,
.pcs_disable = mtk_pcs_lynxi_disable,
+ .pcs_enable = mtk_pcs_lynxi_enable,
};

-struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
- struct regmap *regmap, u32 ana_rgc3,
- u32 flags)
+static struct phylink_pcs *mtk_pcs_lynxi_init(struct device *dev, struct regmap *regmap,
+ u32 ana_rgc3, u32 flags,
+ struct mtk_pcs_lynxi *prealloc)
{
struct mtk_pcs_lynxi *mpcs;
u32 id, ver;
@@ -258,29 +301,33 @@ struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,

ret = regmap_read(regmap, SGMSYS_PCS_DEVICE_ID, &id);
if (ret < 0)
- return NULL;
+ return ERR_PTR(ret);

if (id != SGMII_LYNXI_DEV_ID) {
dev_err(dev, "unknown PCS device id %08x\n", id);
- return NULL;
+ return ERR_PTR(-ENODEV);
}

ret = regmap_read(regmap, SGMSYS_PCS_SCRATCH, &ver);
if (ret < 0)
- return NULL;
+ return ERR_PTR(ret);

ver = FIELD_GET(SGMII_DEV_VERSION, ver);
if (ver != 0x1) {
dev_err(dev, "unknown PCS device version %04x\n", ver);
- return NULL;
+ return ERR_PTR(-ENODEV);
}

dev_dbg(dev, "MediaTek LynxI SGMII PCS (id 0x%08x, ver 0x%04x)\n", id,
ver);

- mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
- if (!mpcs)
- return NULL;
+ if (prealloc) {
+ mpcs = prealloc;
+ } else {
+ mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
+ if (!mpcs)
+ return ERR_PTR(-ENOMEM);
+ };

mpcs->ana_rgc3 = ana_rgc3;
mpcs->regmap = regmap;
@@ -291,6 +338,13 @@ struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
mpcs->interface = PHY_INTERFACE_MODE_NA;

return &mpcs->pcs;
+};
+
+struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
+ struct regmap *regmap, u32 ana_rgc3,
+ u32 flags)
+{
+ return mtk_pcs_lynxi_init(dev, regmap, ana_rgc3, flags, NULL);
}
EXPORT_SYMBOL(mtk_pcs_lynxi_create);

@@ -303,4 +357,98 @@ void mtk_pcs_lynxi_destroy(struct phylink_pcs *pcs)
}
EXPORT_SYMBOL(mtk_pcs_lynxi_destroy);

+static int mtk_pcs_lynxi_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct mtk_pcs_lynxi *mpcs;
+ struct phylink_pcs *pcs;
+ struct regmap *regmap;
+ u32 flags = 0;
+
+ mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL);
+ if (!mpcs)
+ return -ENOMEM;
+
+ regmap = syscon_node_to_regmap(np->parent);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ if (of_property_read_bool(np->parent, "mediatek,pnswap"))
+ flags |= MTK_SGMII_FLAG_PN_SWAP;
+
+ mpcs->rstc = of_reset_control_get_shared(np->parent, NULL);
+ if (IS_ERR(mpcs->rstc))
+ return PTR_ERR(mpcs->rstc);
+
+ reset_control_deassert(mpcs->rstc);
+ mpcs->sgmii_sel = devm_clk_get_enabled(dev, "sgmii_sel");
+ if (IS_ERR(mpcs->sgmii_sel))
+ return PTR_ERR(mpcs->sgmii_sel);
+
+ mpcs->sgmii_rx = devm_clk_get(dev, "sgmii_rx");
+ if (IS_ERR(mpcs->sgmii_rx))
+ return PTR_ERR(mpcs->sgmii_rx);
+
+ mpcs->sgmii_tx = devm_clk_get(dev, "sgmii_tx");
+ if (IS_ERR(mpcs->sgmii_tx))
+ return PTR_ERR(mpcs->sgmii_tx);
+
+ pcs = mtk_pcs_lynxi_init(dev, regmap, (uintptr_t)of_device_get_match_data(dev),
+ flags, mpcs);
+ if (IS_ERR(pcs))
+ return PTR_ERR(pcs);
+
+ regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
+
+ platform_set_drvdata(pdev, mpcs);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_pcs_lynxi_of_match[] = {
+ { .compatible = "mediatek,mt7988-sgmii", .data = (void *)MTK_NETSYS_V3_AMA_RGC3 },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, mtk_pcs_lynxi_of_match);
+
+struct phylink_pcs *mtk_pcs_lynxi_select_pcs(struct device_node *np, phy_interface_t mode)
+{
+ struct platform_device *pdev;
+ struct mtk_pcs_lynxi *mpcs;
+
+ if (!np)
+ return NULL;
+
+ if (!of_device_is_available(np))
+ return ERR_PTR(-ENODEV);
+
+ if (!of_match_node(mtk_pcs_lynxi_of_match, np))
+ return ERR_PTR(-EINVAL);
+
+ pdev = of_find_device_by_node(np);
+ if (!pdev || !platform_get_drvdata(pdev)) {
+ if (pdev)
+ put_device(&pdev->dev);
+ return ERR_PTR(-EPROBE_DEFER);
+ }
+
+ mpcs = platform_get_drvdata(pdev);
+ put_device(&pdev->dev);
+
+ return &mpcs->pcs;
+}
+EXPORT_SYMBOL(mtk_pcs_lynxi_select_pcs);
+
+static struct platform_driver mtk_pcs_lynxi_driver = {
+ .driver = {
+ .name = "mtk-pcs-lynxi",
+ .of_match_table = mtk_pcs_lynxi_of_match,
+ },
+ .probe = mtk_pcs_lynxi_probe,
+};
+module_platform_driver(mtk_pcs_lynxi_driver);
+
+MODULE_AUTHOR("Daniel Golle <[email protected]>");
+MODULE_DESCRIPTION("MediaTek LynxI HSGMII PCS");
MODULE_LICENSE("GPL");
diff --git a/include/linux/pcs/pcs-mtk-lynxi.h b/include/linux/pcs/pcs-mtk-lynxi.h
index be3b4ab32f4a7..5db19d6a7261f 100644
--- a/include/linux/pcs/pcs-mtk-lynxi.h
+++ b/include/linux/pcs/pcs-mtk-lynxi.h
@@ -10,4 +10,5 @@ struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
struct regmap *regmap,
u32 ana_rgc3, u32 flags);
void mtk_pcs_lynxi_destroy(struct phylink_pcs *pcs);
+struct phylink_pcs *mtk_pcs_lynxi_select_pcs(struct device_node *np, phy_interface_t mode);
#endif
--
2.43.0

2023-12-06 01:44:53

[permalink] [raw]

Subject: [RFC PATCH v2 1/8] dt-bindings: phy: mediatek,xfi-pextp: add new bindings

Add bindings for the MediaTek PEXTP Ethernet SerDes PHY found in the
MediaTek MT7988 SoC which can operate at various interfaces modes:

* USXGMII
* 10GBase-R
* 5GBase-R
* 2500Base-X
* 1000Base-X
* Cisco SGMII (MAC side)

Signed-off-by: Daniel Golle <[email protected]>
---
.../bindings/phy/mediatek,xfi-pextp.yaml | 80 +++++++++++++++++++
1 file changed, 80 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml

diff --git a/Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml b/Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml
new file mode 100644
index 0000000000000..58c93368141e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,xfi-pextp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek XFI PEXTP SerDes PHY
+
+maintainers:
+ - Daniel Golle <[email protected]>
+
+description:
+ The MediaTek XFI PEXTP SerDes PHY provides the physical SerDes lanes
+ used by the MediaTek USXGMII PCS.
+
+properties:
+ $nodename:
+ pattern: "^phy@[0-9a-f]+$"
+
+ compatible:
+ const: mediatek,mt7988-xfi-pextp
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: XFI PHY clock
+ - description: XFI register clock
+
+ clock-names:
+ items:
+ - const: "xfipll"
+ - const: "topxtal"
+
+ resets:
+ items:
+ - description: PEXTP reset
+
+ mediatek,usxgmii-performance-errata:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ USXGMII0 on MT7988 suffers from a performance problem in 10GBase-R
+ mode which needs a work-around in the driver. The work-around is
+ enabled using this flag.
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mediatek,mt7988-clk.h>
+ #include <dt-bindings/reset/mediatek,mt7988-resets.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ phy@11f20000 {
+ compatible = "mediatek,mt7988-xfi-pextp";
+ reg = <0 0x11f20000 0 0x10000>;
+ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
+ <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
+ clock-names = "xfipll", "topxtal";
+ resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>;
+ mediatek,usxgmii-performance-errata;
+ #phy-cells = <0>;
+ };
+ };
+
+...
--
2.43.0

2023-12-06 01:45:45

[permalink] [raw]

Subject: [RFC PATCH v2 2/8] phy: add driver for MediaTek pextp 10GE SerDes PHY

Add driver for MediaTek's pextp 10 Gigabit/s Ethernet SerDes PHY which
can be found in the MT7988 SoC.

The PHY can operates only in PHY_MODE_ETHERNET, the submode is one of
PHY_INTERFACE_MODE_* corresponding to the supported modes:

* USXGMII
* 10GBase-R
* 5GBase-R
* 2500Base-X
* 1000Base-X
* Cisco SGMII (MAC side)

In order to work-around a performance issue present on the first of
two PEXTP present in MT7988 special tuning is applied which can be
selected by adding the mediatek,usxgmii-performance-errata property to
the device tree node.

There is no documentation what-so-ever for the pextp registers and
this driver is based on a GPL licensed implementation found in
MediaTek's SDK.

Signed-off-by: Daniel Golle <[email protected]>
---
MAINTAINERS | 1 +
drivers/phy/mediatek/Kconfig | 11 +
drivers/phy/mediatek/Makefile | 1 +
drivers/phy/mediatek/phy-mtk-pextp.c | 365 +++++++++++++++++++++++++++
4 files changed, 378 insertions(+)
create mode 100644 drivers/phy/mediatek/phy-mtk-pextp.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1ef2a16370619..1ea4555013a4d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13497,6 +13497,7 @@ L: [email protected]
S: Maintained
F: drivers/net/phy/mediatek-ge-soc.c
F: drivers/net/phy/mediatek-ge.c
+F: drivers/phy/mediatek/phy-mtk-pextp.c

MEDIATEK I2C CONTROLLER DRIVER
M: Qii Wang <[email protected]>
diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig
index 3125ecb5d119f..a7749a6d96541 100644
--- a/drivers/phy/mediatek/Kconfig
+++ b/drivers/phy/mediatek/Kconfig
@@ -13,6 +13,17 @@ config PHY_MTK_PCIE
callback for PCIe GEN3 port, it supports software efuse
initialization.

+config PHY_MTK_PEXTP
+ tristate "MediaTek PEXTP Driver"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ depends on OF && OF_ADDRESS
+ depends on HAS_IOMEM
+ select GENERIC_PHY
+ help
+ Say 'Y' here to add support for MediaTek pextp PHY driver.
+ The driver provides access to the Ethernet SerDes PHY supporting
+ various 1GE, 2.5GE, 5GE and 10GE modes.
+
config PHY_MTK_TPHY
tristate "MediaTek T-PHY Driver"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
index c9a50395533eb..ca60c7b9b02ac 100644
--- a/drivers/phy/mediatek/Makefile
+++ b/drivers/phy/mediatek/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
+obj-$(CONFIG_PHY_MTK_PEXTP) += phy-mtk-pextp.o

phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
diff --git a/drivers/phy/mediatek/phy-mtk-pextp.c b/drivers/phy/mediatek/phy-mtk-pextp.c
new file mode 100644
index 0000000000000..e5bfab86f95a5
--- /dev/null
+++ b/drivers/phy/mediatek/phy-mtk-pextp.c
@@ -0,0 +1,365 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/* MediaTek 10GE SerDes PHY driver
+ *
+ * Copyright (c) 2023 Daniel Golle <[email protected]>
+ * based on mtk_usxgmii.c found in MediaTek's SDK released under GPL-2.0
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Henry Yen <[email protected]>
+ */
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/netdevice.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/phy.h>
+#include <linux/phy/phy.h>
+
+struct mtk_pextp_phy {
+ void __iomem *base;
+ struct device *dev;
+ struct reset_control *reset;
+ struct clk *clk[2];
+ bool da_war;
+};
+
+static bool mtk_interface_mode_is_xgmii(phy_interface_t interface)
+{
+ switch (interface) {
+ case PHY_INTERFACE_MODE_INTERNAL:
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_5GBASER:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static void mtk_pextp_setup(struct mtk_pextp_phy *pextp, phy_interface_t interface)
+{
+ bool is_10g = (interface == PHY_INTERFACE_MODE_10GBASER ||
+ interface == PHY_INTERFACE_MODE_USXGMII);
+ bool is_2p5g = (interface == PHY_INTERFACE_MODE_2500BASEX);
+ bool is_5g = (interface == PHY_INTERFACE_MODE_5GBASER);
+
+ dev_dbg(pextp->dev, "setting up for mode %s\n", phy_modes(interface));
+
+ /* Setup operation mode */
+ if (is_10g)
+ iowrite32(0x00C9071C, pextp->base + 0x9024);
+ else
+ iowrite32(0x00D9071C, pextp->base + 0x9024);
+
+ if (is_5g)
+ iowrite32(0xAAA5A5AA, pextp->base + 0x2020);
+ else
+ iowrite32(0xAA8585AA, pextp->base + 0x2020);
+
+ if (is_2p5g || is_5g || is_10g) {
+ iowrite32(0x0C020707, pextp->base + 0x2030);
+ iowrite32(0x0E050F0F, pextp->base + 0x2034);
+ iowrite32(0x00140032, pextp->base + 0x2040);
+ } else {
+ iowrite32(0x0C020207, pextp->base + 0x2030);
+ iowrite32(0x0E05050F, pextp->base + 0x2034);
+ iowrite32(0x00200032, pextp->base + 0x2040);
+ }
+
+ if (is_2p5g || is_10g)
+ iowrite32(0x00C014AA, pextp->base + 0x50F0);
+ else if (is_5g)
+ iowrite32(0x00C018AA, pextp->base + 0x50F0);
+ else
+ iowrite32(0x00C014BA, pextp->base + 0x50F0);
+
+ if (is_5g) {
+ iowrite32(0x3777812B, pextp->base + 0x50E0);
+ iowrite32(0x005C9CFF, pextp->base + 0x506C);
+ iowrite32(0x9DFAFAFA, pextp->base + 0x5070);
+ iowrite32(0x273F3F3F, pextp->base + 0x5074);
+ iowrite32(0xA8883868, pextp->base + 0x5078);
+ iowrite32(0x14661466, pextp->base + 0x507C);
+ } else {
+ iowrite32(0x3777C12B, pextp->base + 0x50E0);
+ iowrite32(0x005F9CFF, pextp->base + 0x506C);
+ iowrite32(0x9D9DFAFA, pextp->base + 0x5070);
+ iowrite32(0x27273F3F, pextp->base + 0x5074);
+ iowrite32(0xA7883C68, pextp->base + 0x5078);
+ iowrite32(0x11661166, pextp->base + 0x507C);
+ }
+
+ if (is_2p5g || is_10g) {
+ iowrite32(0x0E000AAF, pextp->base + 0x5080);
+ iowrite32(0x08080D0D, pextp->base + 0x5084);
+ iowrite32(0x02030909, pextp->base + 0x5088);
+ } else if (is_5g) {
+ iowrite32(0x0E001ABF, pextp->base + 0x5080);
+ iowrite32(0x080B0D0D, pextp->base + 0x5084);
+ iowrite32(0x02050909, pextp->base + 0x5088);
+ } else {
+ iowrite32(0x0E000EAF, pextp->base + 0x5080);
+ iowrite32(0x08080E0D, pextp->base + 0x5084);
+ iowrite32(0x02030B09, pextp->base + 0x5088);
+ }
+
+ if (is_5g) {
+ iowrite32(0x0C000000, pextp->base + 0x50E4);
+ iowrite32(0x04000000, pextp->base + 0x50E8);
+ } else {
+ iowrite32(0x0C0C0000, pextp->base + 0x50E4);
+ iowrite32(0x04040000, pextp->base + 0x50E8);
+ }
+
+ if (is_2p5g || mtk_interface_mode_is_xgmii(interface))
+ iowrite32(0x0F0F0C06, pextp->base + 0x50EC);
+ else
+ iowrite32(0x0F0F0606, pextp->base + 0x50EC);
+
+ if (is_5g) {
+ iowrite32(0x50808C8C, pextp->base + 0x50A8);
+ iowrite32(0x18000000, pextp->base + 0x6004);
+ } else {
+ iowrite32(0x506E8C8C, pextp->base + 0x50A8);
+ iowrite32(0x18190000, pextp->base + 0x6004);
+ }
+
+ if (is_10g)
+ iowrite32(0x01423342, pextp->base + 0x00F8);
+ else if (is_5g)
+ iowrite32(0x00A132A1, pextp->base + 0x00F8);
+ else if (is_2p5g)
+ iowrite32(0x009C329C, pextp->base + 0x00F8);
+ else
+ iowrite32(0x00FA32FA, pextp->base + 0x00F8);
+
+ /* Force SGDT_OUT off and select PCS */
+ if (mtk_interface_mode_is_xgmii(interface))
+ iowrite32(0x80201F20, pextp->base + 0x00F4);
+ else
+ iowrite32(0x80201F21, pextp->base + 0x00F4);
+
+ /* Force GLB_CKDET_OUT */
+ iowrite32(0x00050C00, pextp->base + 0x0030);
+
+ /* Force AEQ on */
+ iowrite32(0x02002800, pextp->base + 0x0070);
+ ndelay(1020);
+
+ /* Setup DA default value */
+ iowrite32(0x00000020, pextp->base + 0x30B0);
+ iowrite32(0x00008A01, pextp->base + 0x3028);
+ iowrite32(0x0000A884, pextp->base + 0x302C);
+ iowrite32(0x00083002, pextp->base + 0x3024);
+ if (mtk_interface_mode_is_xgmii(interface)) {
+ iowrite32(0x00022220, pextp->base + 0x3010);
+ iowrite32(0x0F020A01, pextp->base + 0x5064);
+ iowrite32(0x06100600, pextp->base + 0x50B4);
+ if (interface == PHY_INTERFACE_MODE_USXGMII)
+ iowrite32(0x40704000, pextp->base + 0x3048);
+ else
+ iowrite32(0x47684100, pextp->base + 0x3048);
+ } else {
+ iowrite32(0x00011110, pextp->base + 0x3010);
+ iowrite32(0x40704000, pextp->base + 0x3048);
+ }
+
+ if (!mtk_interface_mode_is_xgmii(interface) && !is_2p5g)
+ iowrite32(0x0000C000, pextp->base + 0x3064);
+
+ if (interface == PHY_INTERFACE_MODE_USXGMII) {
+ iowrite32(0xA8000000, pextp->base + 0x3050);
+ iowrite32(0x000000AA, pextp->base + 0x3054);
+ } else if (mtk_interface_mode_is_xgmii(interface)) {
+ iowrite32(0x00000000, pextp->base + 0x3050);
+ iowrite32(0x00000000, pextp->base + 0x3054);
+ } else {
+ iowrite32(0xA8000000, pextp->base + 0x3050);
+ iowrite32(0x000000AA, pextp->base + 0x3054);
+ }
+
+ if (mtk_interface_mode_is_xgmii(interface))
+ iowrite32(0x00000F00, pextp->base + 0x306C);
+ else if (is_2p5g)
+ iowrite32(0x22000F00, pextp->base + 0x306C);
+ else
+ iowrite32(0x20200F00, pextp->base + 0x306C);
+
+ if (interface == PHY_INTERFACE_MODE_10GBASER && pextp->da_war)
+ iowrite32(0x0007B400, pextp->base + 0xA008);
+
+ if (mtk_interface_mode_is_xgmii(interface))
+ iowrite32(0x00040000, pextp->base + 0xA060);
+ else
+ iowrite32(0x00050000, pextp->base + 0xA060);
+
+ if (is_10g)
+ iowrite32(0x00000001, pextp->base + 0x90D0);
+ else if (is_5g)
+ iowrite32(0x00000003, pextp->base + 0x90D0);
+ else if (is_2p5g)
+ iowrite32(0x00000005, pextp->base + 0x90D0);
+ else
+ iowrite32(0x00000007, pextp->base + 0x90D0);
+
+ /* Release reset */
+ iowrite32(0x0200E800, pextp->base + 0x0070);
+ usleep_range(150, 500);
+
+ /* Switch to P0 */
+ iowrite32(0x0200C111, pextp->base + 0x0070);
+ ndelay(1020);
+ iowrite32(0x0200C101, pextp->base + 0x0070);
+ usleep_range(15, 50);
+
+ if (mtk_interface_mode_is_xgmii(interface)) {
+ /* Switch to Gen3 */
+ iowrite32(0x0202C111, pextp->base + 0x0070);
+ } else {
+ /* Switch to Gen2 */
+ iowrite32(0x0201C111, pextp->base + 0x0070);
+ }
+ ndelay(1020);
+ if (mtk_interface_mode_is_xgmii(interface))
+ iowrite32(0x0202C101, pextp->base + 0x0070);
+ else
+ iowrite32(0x0201C101, pextp->base + 0x0070);
+ usleep_range(100, 500);
+ iowrite32(0x00000030, pextp->base + 0x30B0);
+ if (mtk_interface_mode_is_xgmii(interface))
+ iowrite32(0x80201F00, pextp->base + 0x00F4);
+ else
+ iowrite32(0x80201F01, pextp->base + 0x00F4);
+
+ iowrite32(0x30000000, pextp->base + 0x3040);
+ usleep_range(400, 1000);
+}
+
+static int mtk_pextp_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+{
+ struct mtk_pextp_phy *pextp = phy_get_drvdata(phy);
+
+ if (mode != PHY_MODE_ETHERNET)
+ return -EINVAL;
+
+ switch (submode) {
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_5GBASER:
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_USXGMII:
+ mtk_pextp_setup(pextp, submode);
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int mtk_pextp_reset(struct phy *phy)
+{
+ struct mtk_pextp_phy *pextp = phy_get_drvdata(phy);
+
+ reset_control_assert(pextp->reset);
+ usleep_range(100, 500);
+ reset_control_deassert(pextp->reset);
+ usleep_range(1, 10);
+
+ return 0;
+}
+
+static int mtk_pextp_power_on(struct phy *phy)
+{
+ struct mtk_pextp_phy *pextp = phy_get_drvdata(phy);
+ int ret;
+
+ ret = clk_prepare_enable(pextp->clk[0]);
+ if (ret)
+ return ret;
+
+ return clk_prepare_enable(pextp->clk[1]);
+}
+
+static int mtk_pextp_power_off(struct phy *phy)
+{
+ struct mtk_pextp_phy *pextp = phy_get_drvdata(phy);
+
+ clk_disable_unprepare(pextp->clk[1]);
+ clk_disable_unprepare(pextp->clk[0]);
+
+ return 0;
+}
+
+static const struct phy_ops mtk_pextp_ops = {
+ .power_on = mtk_pextp_power_on,
+ .power_off = mtk_pextp_power_off,
+ .set_mode = mtk_pextp_set_mode,
+ .reset = mtk_pextp_reset,
+ .owner = THIS_MODULE,
+};
+
+static int mtk_pextp_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct phy_provider *phy_provider;
+ struct mtk_pextp_phy *pextp;
+ struct phy *phy;
+
+ if (!np)
+ return -ENODEV;
+
+ pextp = devm_kzalloc(&pdev->dev, sizeof(*pextp), GFP_KERNEL);
+ if (!pextp)
+ return -ENOMEM;
+
+ pextp->base = devm_of_iomap(&pdev->dev, np, 0, NULL);
+ if (!pextp->base)
+ return -EIO;
+
+ pextp->dev = &pdev->dev;
+ pextp->clk[0] = devm_clk_get(&pdev->dev, "topxtal");
+ if (IS_ERR(pextp->clk[0]))
+ return PTR_ERR(pextp->clk[0]);
+
+ pextp->clk[1] = devm_clk_get(&pdev->dev, "xfipll");
+ if (IS_ERR(pextp->clk[1]))
+ return PTR_ERR(pextp->clk[1]);
+
+ pextp->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(pextp->reset))
+ return PTR_ERR(pextp->reset);
+
+ pextp->da_war = of_property_read_bool(np, "mediatek,usxgmii-performance-errata");
+
+ phy = devm_phy_create(&pdev->dev, NULL, &mtk_pextp_ops);
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
+
+ phy_set_drvdata(phy, pextp);
+
+ phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id mtk_pextp_match[] = {
+ { .compatible = "mediatek,mt7988-xfi-pextp", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, mtk_pextp_match);
+
+static struct platform_driver mtk_pextp_driver = {
+ .probe = mtk_pextp_probe,
+ .driver = {
+ .name = "mtk-pextp",
+ .of_match_table = mtk_pextp_match,
+ },
+};
+module_platform_driver(mtk_pextp_driver);
+
+MODULE_DESCRIPTION("MediaTek pextp SerDes PHY driver");
+MODULE_AUTHOR("Daniel Golle <[email protected]>");
+MODULE_LICENSE("GPL");
--
2.43.0

2023-12-06 01:45:55

[permalink] [raw]

Subject: [RFC PATCH v2 7/8] dt-bindings: net: mediatek,net: fix and complete mt7988-eth binding

Complete support for MT7988 which comes with 3 MACs, SRAM for DMA
descriptors and uses a dedicated PCS for the SerDes units.

Fixes: c94a9aabec36 ("dt-bindings: net: mediatek,net: add mt7988-eth binding")
Signed-off-by: Daniel Golle <[email protected]>
---
.../devicetree/bindings/net/mediatek,net.yaml | 148 +++++++++++++++++-
1 file changed, 146 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml
index 030d106bc7d3f..ca0667c51c1c2 100644
--- a/Documentation/devicetree/bindings/net/mediatek,net.yaml
+++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml
@@ -28,7 +28,10 @@ properties:
- ralink,rt5350-eth

reg:
- maxItems: 1
+ minItems: 1
+ items:
+ - description: Base of registers used to program the ethernet controller
+ - description: SRAM region used for DMA descriptors

clocks: true
clock-names: true
@@ -115,6 +118,9 @@ allOf:
- mediatek,mt7623-eth
then:
properties:
+ reg:
+ maxItems: 1
+
interrupts:
maxItems: 3

@@ -149,6 +155,9 @@ allOf:
- mediatek,mt7621-eth
then:
properties:
+ reg:
+ maxItems: 1
+
interrupts:
maxItems: 1

@@ -174,6 +183,9 @@ allOf:
const: mediatek,mt7622-eth
then:
properties:
+ reg:
+ maxItems: 1
+
interrupts:
maxItems: 3

@@ -215,6 +227,9 @@ allOf:
const: mediatek,mt7629-eth
then:
properties:
+ reg:
+ maxItems: 1
+
interrupts:
maxItems: 3

@@ -257,6 +272,9 @@ allOf:
const: mediatek,mt7981-eth
then:
properties:
+ reg:
+ maxItems: 1
+
interrupts:
minItems: 4

@@ -295,6 +313,9 @@ allOf:
const: mediatek,mt7986-eth
then:
properties:
+ reg:
+ maxItems: 1
+
interrupts:
minItems: 4

@@ -333,8 +354,13 @@ allOf:
const: mediatek,mt7988-eth
then:
properties:
+ reg:
+ maxItems: 2
+ minItems: 2
+
interrupts:
minItems: 4
+ maxItems: 4

clocks:
minItems: 24
@@ -368,7 +394,7 @@ allOf:
- const: top_netsys_warp_sel

patternProperties:
- "^mac@[0-1]$":
+ "^mac@[0-2]$":
type: object
unevaluatedProperties: false
allOf:
@@ -382,6 +408,9 @@ patternProperties:
reg:
maxItems: 1

+ phys:
+ maxItems: 1
+
required:
- reg
- compatible
@@ -559,3 +588,118 @@ examples:
};
};
};
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/mediatek,mt7988-clk.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ethernet@15100000 {
+ compatible = "mediatek,mt7988-eth";
+ reg = <0 0x15100000 0 0x80000>, <0 0x15400000 0 0x380000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
+ <&ethsys CLK_ETHDMA_XGP2_EN>,
+ <&ethsys CLK_ETHDMA_XGP3_EN>,
+ <&ethsys CLK_ETHDMA_FE_EN>,
+ <&ethsys CLK_ETHDMA_GP2_EN>,
+ <&ethsys CLK_ETHDMA_GP1_EN>,
+ <&ethsys CLK_ETHDMA_GP3_EN>,
+ <&ethsys CLK_ETHDMA_ESW_EN>,
+ <&ethsys CLK_ETHDMA_CRYPT0_EN>,
+ <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
+ <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
+ <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
+ <&topckgen CLK_TOP_ETH_GMII_SEL>,
+ <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
+ <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
+ <&topckgen CLK_TOP_ETH_SYS_SEL>,
+ <&topckgen CLK_TOP_ETH_XGMII_SEL>,
+ <&topckgen CLK_TOP_ETH_MII_SEL>,
+ <&topckgen CLK_TOP_NETSYS_SEL>,
+ <&topckgen CLK_TOP_NETSYS_500M_SEL>,
+ <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
+ <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
+ <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
+ <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
+
+ clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
+ "gp3", "esw", "crypto",
+ "ethwarp_wocpu2", "ethwarp_wocpu1",
+ "ethwarp_wocpu0", "top_eth_gmii_sel",
+ "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
+ "top_eth_sys_sel", "top_eth_xgmii_sel",
+ "top_eth_mii_sel", "top_netsys_sel",
+ "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
+ "top_netsys_sync_250m_sel",
+ "top_netsys_ppefb_250m_sel",
+ "top_netsys_warp_sel";
+ assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
+ <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
+ <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
+ <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
+ <&topckgen CLK_TOP_SGM_0_SEL>,
+ <&topckgen CLK_TOP_SGM_1_SEL>;
+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
+ <&topckgen CLK_TOP_NET1PLL_D4>,
+ <&topckgen CLK_TOP_NET1PLL_D8_D4>,
+ <&topckgen CLK_TOP_NET1PLL_D8_D4>,
+ <&apmixedsys CLK_APMIXED_SGMPLL>,
+ <&apmixedsys CLK_APMIXED_SGMPLL>;
+ mediatek,ethsys = <&ethsys>;
+ mediatek,infracfg = <&topmisc>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "internal"; /* CPU port of built-in 1GE switch */
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-handle = <&int_2p5g_phy>;
+ };
+
+ mac@2 {
+ compatible = "mediatek,eth-mac";
+ reg = <2>;
+ pcs-handle = <&usxgmiisys0>;
+ phy-handle = <&phy0>;
+ };
+
+ mdio_bus: mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* external PHY */
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ /* internal 2.5G PHY */
+ int_2p5g_phy: ethernet-phy@15 {
+ reg = <15>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ phy-mode = "internal";
+ };
+ };
+ };
+ };
--
2.43.0

2023-12-06 01:45:56

[permalink] [raw]

Subject: [RFC PATCH v2 4/8] dt-bindings: net: pcs: add bindings for MediaTek USXGMII PCS

MediaTek's USXGMII can be found in the MT7988 SoC. We need to access
it in order to configure and monitor the Ethernet SerDes link in
USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped
legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those
interface modes are also available.

Signed-off-by: Daniel Golle <[email protected]>
---
.../bindings/net/pcs/mediatek,usxgmii.yaml | 100 ++++++++++++++++++
1 file changed, 100 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml

diff --git a/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
new file mode 100644
index 0000000000000..9a798c0d2fdd7
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/pcs/mediatek,usxgmii.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek USXGMII PCS
+
+maintainers:
+ - Daniel Golle <[email protected]>
+
+description:
+ The MediaTek USXGMII PCS provides physical link control and status
+ for USXGMII, 10GBase-R and 5GBase-R links on the SerDes interfaces
+ provided by the PEXTP PHY.
+ In order to also support legacy 2500Base-X, 1000Base-X and Cisco
+ SGMII an existing mediatek,*-sgmiisys LynxI PCS is wrapped to
+ provide those interfaces modes on the same SerDes interfaces shared
+ with the USXGMII PCS.
+
+properties:
+ $nodename:
+ pattern: "^pcs@[0-9a-f]+$"
+
+ compatible:
+ const: mediatek,mt7988-usxgmiisys
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: USXGMII top-level clock
+ - description: SGMII top-level clock
+ - description: SGMII subsystem TX clock
+ - description: SGMII subsystem RX clock
+ - description: XFI PLL clock
+
+ clock-names:
+ items:
+ - const: usxgmii
+ - const: sgmii_sel
+ - const: sgmii_tx
+ - const: sgmii_rx
+ - const: xfi_pll
+
+ phys:
+ items:
+ - description: PEXTP SerDes PHY
+
+ mediatek,sgmiisys:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon node of the corresponding SGMII LynxI PCS.
+
+ resets:
+ items:
+ - description: XFI reset
+ - description: SGMII reset
+
+ reset-names:
+ items:
+ - const: xfi
+ - const: sgmii
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - phys
+ - mediatek,sgmiisys
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mediatek,mt7988-clk.h>
+ #include <dt-bindings/reset/mediatek,mt7988-resets.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ usxgmiisys0: pcs@10080000 {
+ compatible = "mediatek,mt7988-usxgmiisys";
+ reg = <0 0x10080000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
+ <&topckgen CLK_TOP_SGM_0_SEL>,
+ <&sgmiisys0 CLK_SGM0_TX_EN>,
+ <&sgmiisys0 CLK_SGM0_RX_EN>,
+ <&xfi_pll CLK_XFIPLL_PLL_EN>;
+ clock-names = "usxgmii", "sgmii_sel", "sgmii_tx", "sgmii_rx", "xfi_pll";
+ resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>,
+ <&watchdog MT7988_TOPRGU_SGMII0_GRST>;
+ reset-names = "xfi", "sgmii";
+ phys = <&xfi_pextp0>;
+ mediatek,sgmiisys = <&sgmiisys0>;
+ };
+ };
--
2.43.0

2023-12-06 01:45:58

[permalink] [raw]

Subject: [RFC PATCH v2 6/8] dt-bindings: net: mediatek: remove wrongly added clocks and SerDes

Several clocks as well as both sgmiisys phandles were added by mistake
to the Ethernet bindings for MT7988.

This happened because the vendor driver which served as a reference
uses a high number of syscon phandles to access various parts of the
SoC which wasn't acceptable upstream. Hence several parts which have
never previously been supported (such SerDes PHY and USXGMII PCS) have
been moved to separate drivers which also result in a much more sane
device tree.

Quickly align the bindings with the upcoming reality of the drivers
actually adding full support for this SoC.

Fixes: c94a9aabec36 ("dt-bindings: net: mediatek,net: add mt7988-eth binding")
Signed-off-by: Daniel Golle <[email protected]>
---
.../devicetree/bindings/net/mediatek,net.yaml | 32 ++++---------------
1 file changed, 7 insertions(+), 25 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml
index e74502a0afe86..030d106bc7d3f 100644
--- a/Documentation/devicetree/bindings/net/mediatek,net.yaml
+++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml
@@ -337,32 +337,23 @@ allOf:
minItems: 4

clocks:
- minItems: 34
- maxItems: 34
+ minItems: 24
+ maxItems: 24

clock-names:
items:
- - const: crypto
+ - const: xgp1
+ - const: xgp2
+ - const: xgp3
- const: fe
- const: gp2
- const: gp1
- const: gp3
+ - const: esw
+ - const: crypto
- const: ethwarp_wocpu2
- const: ethwarp_wocpu1
- const: ethwarp_wocpu0
- - const: esw
- - const: netsys0
- - const: netsys1
- - const: sgmii_tx250m
- - const: sgmii_rx250m
- - const: sgmii2_tx250m
- - const: sgmii2_rx250m
- - const: top_usxgmii0_sel
- - const: top_usxgmii1_sel
- - const: top_sgm0_sel
- - const: top_sgm1_sel
- - const: top_xfi_phy0_xtal_sel
- - const: top_xfi_phy1_xtal_sel
- const: top_eth_gmii_sel
- const: top_eth_refck_50m_sel
- const: top_eth_sys_200m_sel
@@ -375,15 +366,6 @@ allOf:
- const: top_netsys_sync_250m_sel
- const: top_netsys_ppefb_250m_sel
- const: top_netsys_warp_sel
- - const: wocpu1
- - const: wocpu0
- - const: xgp1
- - const: xgp2
- - const: xgp3
-
- mediatek,sgmiisys:
- minItems: 2
- maxItems: 2

patternProperties:
"^mac@[0-1]$":
--
2.43.0

2023-12-06 01:46:00

[permalink] [raw]

Subject: [RFC PATCH v2 5/8] net: pcs: add driver for MediaTek USXGMII PCS

Add driver for USXGMII PCS found in the MediaTek MT7988 SoC and supporting
USXGMII, 10GBase-R and 5GBase-R interface modes. In order to support
Cisco SGMII, 1000Base-X and 2500Base-X via the also present LynxI PCS
create a wrapped PCS taking care of the components shared between the
new USXGMII PCS and the legacy LynxI PCS.

Signed-off-by: Daniel Golle <[email protected]>
---
.../bindings/net/pcs/mediatek,usxgmii.yaml | 46 +-
MAINTAINERS | 2 +
drivers/net/pcs/Kconfig | 11 +
drivers/net/pcs/Makefile | 1 +
drivers/net/pcs/pcs-mtk-usxgmii.c | 413 ++++++++++++++++++
include/linux/pcs/pcs-mtk-usxgmii.h | 26 ++
6 files changed, 456 insertions(+), 43 deletions(-)
create mode 100644 drivers/net/pcs/pcs-mtk-usxgmii.c
create mode 100644 include/linux/pcs/pcs-mtk-usxgmii.h

diff --git a/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
index 9a798c0d2fdd7..0cdaa3545edb0 100644
--- a/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
@@ -31,70 +31,30 @@ properties:
clocks:
items:
- description: USXGMII top-level clock
- - description: SGMII top-level clock
- - description: SGMII subsystem TX clock
- - description: SGMII subsystem RX clock
- - description: XFI PLL clock
-
- clock-names:
- items:
- - const: usxgmii
- - const: sgmii_sel
- - const: sgmii_tx
- - const: sgmii_rx
- - const: xfi_pll
-
- phys:
- items:
- - description: PEXTP SerDes PHY
-
- mediatek,sgmiisys:
- $ref: /schemas/types.yaml#/definitions/phandle
- description:
- Phandle to the syscon node of the corresponding SGMII LynxI PCS.

resets:
items:
- description: XFI reset
- - description: SGMII reset
-
- reset-names:
- items:
- - const: xfi
- - const: sgmii

required:
- compatible
- reg
- clocks
- - clock-names
- - phys
- - mediatek,sgmiisys
- resets
- - reset-names

additionalProperties: false

examples:
- |
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
- #include <dt-bindings/reset/mediatek,mt7988-resets.h>
+ #define MT7988_TOPRGU_XFI0_GRST 12
soc {
#address-cells = <2>;
#size-cells = <2>;
usxgmiisys0: pcs@10080000 {
compatible = "mediatek,mt7988-usxgmiisys";
reg = <0 0x10080000 0 0x1000>;
- clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
- <&topckgen CLK_TOP_SGM_0_SEL>,
- <&sgmiisys0 CLK_SGM0_TX_EN>,
- <&sgmiisys0 CLK_SGM0_RX_EN>,
- <&xfi_pll CLK_XFIPLL_PLL_EN>;
- clock-names = "usxgmii", "sgmii_sel", "sgmii_tx", "sgmii_rx", "xfi_pll";
- resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>,
- <&watchdog MT7988_TOPRGU_SGMII0_GRST>;
- reset-names = "xfi", "sgmii";
- phys = <&xfi_pextp0>;
- mediatek,sgmiisys = <&sgmiisys0>;
+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
+ resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
};
};
diff --git a/MAINTAINERS b/MAINTAINERS
index 1ea4555013a4d..13fe7ffb10f7d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13487,7 +13487,9 @@ M: Daniel Golle <[email protected]>
L: [email protected]
S: Maintained
F: drivers/net/pcs/pcs-mtk-lynxi.c
+F: drivers/net/pcs/pcs-mtk-usxgmii.c
F: include/linux/pcs/pcs-mtk-lynxi.h
+F: include/linux/pcs/pcs-mtk-usxgmii.h

MEDIATEK ETHERNET PHY DRIVERS
M: Daniel Golle <[email protected]>
diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index 87cf308fc6d8b..55a6865bdaba3 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -25,6 +25,17 @@ config PCS_MTK_LYNXI
This module provides helpers to phylink for managing the LynxI PCS
which is part of MediaTek's SoC and Ethernet switch ICs.

+config PCS_MTK_USXGMII
+ tristate "MediaTek USXGMII PCS"
+ select PCS_MTK_LYNXI
+ select PHY_MTK_PEXTP
+ select PHYLINK
+ help
+ This module provides a driver for MediaTek's USXGMII PCS supporting
+ 10GBase-R, 5GBase-R and USXGMII interface modes.
+ 1000Base-X, 2500Base-X and Cisco SGMII are supported on the same
+ differential pairs via an embedded LynxI PHY.
+
config PCS_RZN1_MIIC
tristate "Renesas RZ/N1 MII converter"
depends on OF && (ARCH_RZN1 || COMPILE_TEST)
diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
index fb1694192ae63..cc355152ca1ca 100644
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
@@ -6,4 +6,5 @@ pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-nxp.o pcs-xpcs-wx.o
obj-$(CONFIG_PCS_XPCS) += pcs_xpcs.o
obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o
obj-$(CONFIG_PCS_MTK_LYNXI) += pcs-mtk-lynxi.o
+obj-$(CONFIG_PCS_MTK_USXGMII) += pcs-mtk-usxgmii.o
obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o
diff --git a/drivers/net/pcs/pcs-mtk-usxgmii.c b/drivers/net/pcs/pcs-mtk-usxgmii.c
new file mode 100644
index 0000000000000..e895aae3999fe
--- /dev/null
+++ b/drivers/net/pcs/pcs-mtk-usxgmii.c
@@ -0,0 +1,413 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 MediaTek Inc.
+ * Author: Henry Yen <[email protected]>
+ * Daniel Golle <[email protected]>
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mdio.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/reset.h>
+#include <linux/pcs/pcs-mtk-usxgmii.h>
+#include <linux/platform_device.h>
+
+/* USXGMII subsystem config registers */
+/* Register to control speed */
+#define RG_PHY_TOP_SPEED_CTRL1 0x80c
+#define USXGMII_RATE_UPDATE_MODE BIT(31)
+#define USXGMII_MAC_CK_GATED BIT(29)
+#define USXGMII_IF_FORCE_EN BIT(28)
+#define USXGMII_RATE_ADAPT_MODE GENMASK(10, 8)
+#define USXGMII_RATE_ADAPT_MODE_X1 0
+#define USXGMII_RATE_ADAPT_MODE_X2 1
+#define USXGMII_RATE_ADAPT_MODE_X4 2
+#define USXGMII_RATE_ADAPT_MODE_X10 3
+#define USXGMII_RATE_ADAPT_MODE_X100 4
+#define USXGMII_RATE_ADAPT_MODE_X5 5
+#define USXGMII_RATE_ADAPT_MODE_X50 6
+#define USXGMII_XFI_RX_MODE GENMASK(6, 4)
+#define USXGMII_XFI_TX_MODE GENMASK(2, 0)
+#define USXGMII_XFI_MODE_10G 0
+#define USXGMII_XFI_MODE_5G 1
+#define USXGMII_XFI_MODE_2P5G 3
+
+/* Register to control PCS AN */
+#define RG_PCS_AN_CTRL0 0x810
+#define USXGMII_AN_RESTART BIT(31)
+#define USXGMII_AN_SYNC_CNT GENMASK(30, 11)
+#define USXGMII_AN_ENABLE BIT(0)
+
+#define RG_PCS_AN_CTRL2 0x818
+#define USXGMII_LINK_TIMER_IDLE_DETECT GENMASK(29, 20)
+#define USXGMII_LINK_TIMER_COMP_ACK_DETECT GENMASK(19, 10)
+#define USXGMII_LINK_TIMER_AN_RESTART GENMASK(9, 0)
+
+/* Register to read PCS AN status */
+#define RG_PCS_AN_STS0 0x81c
+#define USXGMII_LPA GENMASK(15, 0)
+#define USXGMII_LPA_LATCH BIT(31)
+
+/* Register to read PCS link status */
+#define RG_PCS_RX_STATUS0 0x904
+#define RG_PCS_RX_STATUS_UPDATE BIT(16)
+#define RG_PCS_RX_LINK_STATUS BIT(2)
+
+/* struct mtk_usxgmii_pcs - This structure holds each usxgmii PCS
+ * @pcs: Phylink PCS structure
+ * @dev: Pointer to device structure
+ * @base: IO memory to access PCS hardware
+ * @clk: Pointer to USXGMII clk
+ * @reset: Pointer to USXGMII reset control
+ * @interface: Currently selected interface mode
+ * @neg_mode: Currently used phylink neg_mode
+ */
+struct mtk_usxgmii_pcs {
+ struct phylink_pcs pcs;
+ struct device *dev;
+ void __iomem *base;
+ struct clk *clk;
+ struct reset_control *reset;
+ phy_interface_t interface;
+ unsigned int neg_mode;
+};
+
+static u32 mtk_r32(struct mtk_usxgmii_pcs *mpcs, unsigned int reg)
+{
+ return ioread32(mpcs->base + reg);
+}
+
+static void mtk_m32(struct mtk_usxgmii_pcs *mpcs, unsigned int reg, u32 mask, u32 set)
+{
+ u32 val;
+
+ val = ioread32(mpcs->base + reg);
+ val &= ~mask;
+ val |= set;
+ iowrite32(val, mpcs->base + reg);
+}
+
+static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs)
+{
+ return container_of(pcs, struct mtk_usxgmii_pcs, pcs);
+}
+
+static void mtk_usxgmii_reset(struct mtk_usxgmii_pcs *mpcs)
+{
+ reset_control_assert(mpcs->reset);
+ usleep_range(100, 500);
+ reset_control_deassert(mpcs->reset);
+
+ mdelay(10);
+}
+
+static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface,
+ const unsigned long *advertising,
+ bool permit_pause_to_mac)
+{
+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
+ unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0;
+ bool mode_changed = false;
+
+ if (interface == PHY_INTERFACE_MODE_USXGMII) {
+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | USXGMII_AN_ENABLE;
+ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
+ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
+ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
+ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_10G) |
+ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_10G);
+ } else if (interface == PHY_INTERFACE_MODE_10GBASER) {
+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF);
+ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
+ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
+ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
+ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_10G) |
+ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_10G);
+ adapt_mode = USXGMII_RATE_UPDATE_MODE;
+ } else if (interface == PHY_INTERFACE_MODE_5GBASER) {
+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF);
+ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) |
+ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) |
+ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D);
+ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_5G) |
+ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_5G);
+ adapt_mode = USXGMII_RATE_UPDATE_MODE;
+ } else {
+ return -EINVAL;
+ }
+
+ adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1);
+
+ if (mpcs->interface != interface) {
+ mpcs->interface = interface;
+ mode_changed = true;
+ }
+
+ mtk_usxgmii_reset(mpcs);
+
+ /* Setup USXGMII AN ctrl */
+ mtk_m32(mpcs, RG_PCS_AN_CTRL0,
+ USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
+ an_ctrl);
+
+ mtk_m32(mpcs, RG_PCS_AN_CTRL2,
+ USXGMII_LINK_TIMER_IDLE_DETECT |
+ USXGMII_LINK_TIMER_COMP_ACK_DETECT |
+ USXGMII_LINK_TIMER_AN_RESTART,
+ link_timer);
+
+ mpcs->neg_mode = neg_mode;
+
+ /* Gated MAC CK */
+ mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
+ USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED);
+
+ /* Enable interface force mode */
+ mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
+ USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN);
+
+ /* Setup USXGMII adapt mode */
+ mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
+ USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE,
+ adapt_mode);
+
+ /* Setup USXGMII speed */
+ mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
+ USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE,
+ xfi_mode);
+
+ usleep_range(1, 10);
+
+ /* Un-gated MAC CK */
+ mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1, USXGMII_MAC_CK_GATED, 0);
+
+ usleep_range(1, 10);
+
+ /* Disable interface force mode for the AN mode */
+ if (an_ctrl & USXGMII_AN_ENABLE)
+ mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1, USXGMII_IF_FORCE_EN, 0);
+
+ return mode_changed;
+}
+
+static void mtk_usxgmii_pcs_get_fixed_speed(struct mtk_usxgmii_pcs *mpcs,
+ struct phylink_link_state *state)
+{
+ u32 val = mtk_r32(mpcs, RG_PHY_TOP_SPEED_CTRL1);
+ int speed;
+
+ /* Calculate speed from interface speed and rate adapt mode */
+ switch (FIELD_GET(USXGMII_XFI_RX_MODE, val)) {
+ case USXGMII_XFI_MODE_10G:
+ speed = 10000;
+ break;
+ case USXGMII_XFI_MODE_5G:
+ speed = 5000;
+ break;
+ case USXGMII_XFI_MODE_2P5G:
+ speed = 2500;
+ break;
+ default:
+ state->speed = SPEED_UNKNOWN;
+ return;
+ }
+
+ switch (FIELD_GET(USXGMII_RATE_ADAPT_MODE, val)) {
+ case USXGMII_RATE_ADAPT_MODE_X100:
+ speed /= 100;
+ break;
+ case USXGMII_RATE_ADAPT_MODE_X50:
+ speed /= 50;
+ break;
+ case USXGMII_RATE_ADAPT_MODE_X10:
+ speed /= 10;
+ break;
+ case USXGMII_RATE_ADAPT_MODE_X5:
+ speed /= 5;
+ break;
+ case USXGMII_RATE_ADAPT_MODE_X4:
+ speed /= 4;
+ break;
+ case USXGMII_RATE_ADAPT_MODE_X2:
+ speed /= 2;
+ break;
+ case USXGMII_RATE_ADAPT_MODE_X1:
+ break;
+ default:
+ state->speed = SPEED_UNKNOWN;
+ return;
+ }
+
+ state->speed = speed;
+ state->duplex = DUPLEX_FULL;
+}
+
+static void mtk_usxgmii_pcs_get_an_state(struct mtk_usxgmii_pcs *mpcs,
+ struct phylink_link_state *state)
+{
+ u16 lpa;
+
+ /* Refresh LPA by toggling LPA_LATCH */
+ mtk_m32(mpcs, RG_PCS_AN_STS0, USXGMII_LPA_LATCH, USXGMII_LPA_LATCH);
+ ndelay(1020);
+ mtk_m32(mpcs, RG_PCS_AN_STS0, USXGMII_LPA_LATCH, 0);
+ ndelay(1020);
+ lpa = FIELD_GET(USXGMII_LPA, mtk_r32(mpcs, RG_PCS_AN_STS0));
+
+ phylink_decode_usxgmii_word(state, lpa);
+}
+
+static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs,
+ struct phylink_link_state *state)
+{
+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
+
+ /* Refresh USXGMII link status by toggling RG_PCS_AN_STATUS_UPDATE */
+ mtk_m32(mpcs, RG_PCS_RX_STATUS0, RG_PCS_RX_STATUS_UPDATE,
+ RG_PCS_RX_STATUS_UPDATE);
+ ndelay(1020);
+ mtk_m32(mpcs, RG_PCS_RX_STATUS0, RG_PCS_RX_STATUS_UPDATE, 0);
+ ndelay(1020);
+
+ /* Read USXGMII link status */
+ state->link = FIELD_GET(RG_PCS_RX_LINK_STATUS,
+ mtk_r32(mpcs, RG_PCS_RX_STATUS0));
+
+ /* Continuously repeat re-configuration sequence until link comes up */
+ if (!state->link) {
+ mtk_usxgmii_pcs_config(pcs, mpcs->neg_mode,
+ state->interface, NULL, false);
+ return;
+ }
+
+ if (FIELD_GET(USXGMII_AN_ENABLE, mtk_r32(mpcs, RG_PCS_AN_CTRL0)))
+ mtk_usxgmii_pcs_get_an_state(mpcs, state);
+ else
+ mtk_usxgmii_pcs_get_fixed_speed(mpcs, state);
+}
+
+static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs)
+{
+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
+
+ mtk_m32(mpcs, RG_PCS_AN_CTRL0, USXGMII_AN_RESTART, USXGMII_AN_RESTART);
+}
+
+static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface,
+ int speed, int duplex)
+{
+ /* Reconfiguring USXGMII to ensure the quality of the RX signal
+ * after the line side link up.
+ */
+ mtk_usxgmii_pcs_config(pcs, neg_mode, interface, NULL, false);
+}
+
+static void mtk_usxgmii_pcs_disable(struct phylink_pcs *pcs)
+{
+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
+
+ mpcs->interface = PHY_INTERFACE_MODE_NA;
+ mpcs->neg_mode = -1;
+}
+
+static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = {
+ .pcs_config = mtk_usxgmii_pcs_config,
+ .pcs_get_state = mtk_usxgmii_pcs_get_state,
+ .pcs_an_restart = mtk_usxgmii_pcs_restart_an,
+ .pcs_link_up = mtk_usxgmii_pcs_link_up,
+ .pcs_disable = mtk_usxgmii_pcs_disable,
+};
+
+static int mtk_usxgmii_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_usxgmii_pcs *mpcs;
+
+ mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL);
+ if (!mpcs)
+ return -ENOMEM;
+
+ mpcs->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(mpcs->base))
+ return PTR_ERR(mpcs->base);
+
+ mpcs->dev = dev;
+ mpcs->pcs.ops = &mtk_usxgmii_pcs_ops;
+ mpcs->pcs.poll = true;
+ mpcs->pcs.neg_mode = true;
+ mpcs->interface = PHY_INTERFACE_MODE_NA;
+ mpcs->neg_mode = -1;
+
+ mpcs->clk = devm_clk_get_enabled(mpcs->dev, NULL);
+ if (IS_ERR(mpcs->clk))
+ return PTR_ERR(mpcs->clk);
+
+ mpcs->reset = devm_reset_control_get_shared(dev, NULL);
+ if (IS_ERR(mpcs->reset))
+ return PTR_ERR(mpcs->reset);
+
+ reset_control_deassert(mpcs->reset);
+
+ platform_set_drvdata(pdev, mpcs);
+
+ return 0;
+}
+
+static int mtk_usxgmii_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static const struct of_device_id mtk_usxgmii_of_mtable[] = {
+ { .compatible = "mediatek,mt7988-usxgmiisys" },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, mtk_usxgmii_of_mtable);
+
+struct phylink_pcs *mtk_usxgmii_select_pcs(struct device_node *np, phy_interface_t mode)
+{
+ struct platform_device *pdev;
+ struct mtk_usxgmii_pcs *mpcs;
+
+ if (!np)
+ return NULL;
+
+ if (!of_device_is_available(np))
+ return ERR_PTR(-ENODEV);
+
+ if (!of_match_node(mtk_usxgmii_of_mtable, np))
+ return ERR_PTR(-EINVAL);
+
+ pdev = of_find_device_by_node(np);
+ if (!pdev || !platform_get_drvdata(pdev)) {
+ if (pdev)
+ put_device(&pdev->dev);
+ return ERR_PTR(-EPROBE_DEFER);
+ }
+
+ mpcs = platform_get_drvdata(pdev);
+ put_device(&pdev->dev);
+
+ return &mpcs->pcs;
+}
+EXPORT_SYMBOL(mtk_usxgmii_select_pcs);
+
+static struct platform_driver mtk_usxgmii_driver = {
+ .driver = {
+ .name = "mtk_usxgmii",
+ .suppress_bind_attrs = true,
+ .of_match_table = mtk_usxgmii_of_mtable,
+ },
+ .probe = mtk_usxgmii_probe,
+ .remove = mtk_usxgmii_remove,
+};
+module_platform_driver(mtk_usxgmii_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MediaTek USXGMII PCS driver");
+MODULE_AUTHOR("Daniel Golle <[email protected]>");
diff --git a/include/linux/pcs/pcs-mtk-usxgmii.h b/include/linux/pcs/pcs-mtk-usxgmii.h
new file mode 100644
index 0000000000000..346b88bdf7a6e
--- /dev/null
+++ b/include/linux/pcs/pcs-mtk-usxgmii.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LINUX_PCS_MTK_USXGMII_H
+#define __LINUX_PCS_MTK_USXGMII_H
+
+#include <linux/phylink.h>
+
+/**
+ * mtk_usxgmii_select_pcs() - Get MediaTek PCS instance
+ * @np: Pointer to device node indentifying a MediaTek USXGMII PCS
+ * @mode: Ethernet PHY interface mode
+ *
+ * Return PCS identified by a device node and the PHY interface mode in use
+ *
+ * Return: Pointer to phylink PCS instance of NULL
+ */
+#if IS_ENABLED(CONFIG_PCS_MTK_USXGMII)
+struct phylink_pcs *mtk_usxgmii_select_pcs(struct device_node *np, phy_interface_t mode);
+#else
+static inline struct phylink_pcs *mtk_usxgmii_select_pcs(struct device_node *np,
+ phy_interface_t mode)
+{
+ return NULL;
+}
+#endif /* IS_ENABLED(CONFIG_PCS_MTK_USXGMII) */
+
+#endif /* __LINUX_PCS_MTK_USXGMII_H */
--
2.43.0

2023-12-06 01:46:19

[permalink] [raw]

Subject: [RFC PATCH v2 8/8] net: ethernet: mtk_eth_soc: add paths and SerDes modes for MT7988

MT7988 comes with a built-in 2.5G PHY as well as SerDes lanes to
connect external PHYs or transceivers in USXGMII, 10GBase-R, 5GBase-R,
2500Base-X, 1000Base-X and Cisco SGMII interface modes.

Implement support for configuring for the new paths to SerDes interfaces
and the internal 2.5G PHY.

Add USXGMII PCS driver for 10GBase-R, 5GBase-R and USXGMII mode, and
setup the new PHYA on MT7988 to access the also still existing old
LynxI PCS for 1000Base-X, 2500Base-X and Cisco SGMII PCS interface
modes.

Signed-off-by: Daniel Golle <[email protected]>
---
drivers/net/ethernet/mediatek/mtk_eth_path.c | 122 +++++++-
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 284 +++++++++++++++++--
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 107 +++++--
3 files changed, 462 insertions(+), 51 deletions(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_path.c b/drivers/net/ethernet/mediatek/mtk_eth_path.c
index 7c27a19c4d8f4..3f4f4cfe6a233 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
@@ -31,10 +31,20 @@ static const char *mtk_eth_path_name(u64 path)
return "gmac2_rgmii";
case MTK_ETH_PATH_GMAC2_SGMII:
return "gmac2_sgmii";
+ case MTK_ETH_PATH_GMAC2_2P5GPHY:
+ return "gmac2_2p5gphy";
case MTK_ETH_PATH_GMAC2_GEPHY:
return "gmac2_gephy";
+ case MTK_ETH_PATH_GMAC3_SGMII:
+ return "gmac3_sgmii";
case MTK_ETH_PATH_GDM1_ESW:
return "gdm1_esw";
+ case MTK_ETH_PATH_GMAC1_USXGMII:
+ return "gmac1_usxgmii";
+ case MTK_ETH_PATH_GMAC2_USXGMII:
+ return "gmac2_usxgmii";
+ case MTK_ETH_PATH_GMAC3_USXGMII:
+ return "gmac3_usxgmii";
default:
return "unknown path";
}
@@ -127,6 +137,27 @@ static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, u64 path)
return 0;
}

+static int set_mux_gmac2_to_2p5gphy(struct mtk_eth *eth, u64 path)
+{
+ int ret;
+
+ if (path == MTK_ETH_PATH_GMAC2_2P5GPHY) {
+ ret = regmap_clear_bits(eth->ethsys, ETHSYS_SYSCFG0, SYSCFG0_SGMII_GMAC2_V2);
+ if (ret)
+ return ret;
+
+ /* Setup mux to 2p5g PHY */
+ ret = regmap_clear_bits(eth->infra, TOP_MISC_NETSYS_PCS_MUX, MUX_G2_USXGMII_SEL);
+ if (ret)
+ return ret;
+
+ dev_dbg(eth->dev, "path %s in %s updated\n",
+ mtk_eth_path_name(path), __func__);
+ }
+
+ return 0;
+}
+
static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path)
{
unsigned int val = 0;
@@ -165,7 +196,48 @@ static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path)
return 0;
}

-static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
+static int set_mux_gmac123_to_usxgmii(struct mtk_eth *eth, u64 path)
+{
+ unsigned int val = 0;
+ bool updated = true;
+ int mac_id = 0;
+
+ /* Disable SYSCFG1 SGMII */
+ regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
+
+ switch (path) {
+ case MTK_ETH_PATH_GMAC1_USXGMII:
+ val &= ~(u32)SYSCFG0_SGMII_GMAC1_V2;
+ mac_id = MTK_GMAC1_ID;
+ break;
+ case MTK_ETH_PATH_GMAC2_USXGMII:
+ val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2;
+ mac_id = MTK_GMAC2_ID;
+ break;
+ case MTK_ETH_PATH_GMAC3_USXGMII:
+ val &= ~(u32)SYSCFG0_SGMII_GMAC3_V2;
+ mac_id = MTK_GMAC3_ID;
+ break;
+ default:
+ updated = false;
+ };
+
+ if (updated) {
+ regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
+ SYSCFG0_SGMII_MASK, val);
+
+ if (mac_id == MTK_GMAC2_ID)
+ regmap_set_bits(eth->infra, TOP_MISC_NETSYS_PCS_MUX,
+ MUX_G2_USXGMII_SEL);
+ }
+
+ dev_dbg(eth->dev, "path %s in %s updated = %d\n",
+ mtk_eth_path_name(path), __func__, updated);
+
+ return 0;
+}
+
+static int set_mux_gmac123_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
{
unsigned int val = 0;
bool updated = true;
@@ -182,6 +254,9 @@ static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
case MTK_ETH_PATH_GMAC2_SGMII:
val |= SYSCFG0_SGMII_GMAC2_V2;
break;
+ case MTK_ETH_PATH_GMAC3_SGMII:
+ val |= SYSCFG0_SGMII_GMAC3_V2;
+ break;
default:
updated = false;
}
@@ -209,6 +284,10 @@ static const struct mtk_eth_muxc mtk_eth_muxc[] = {
.name = "mux_u3_gmac2_to_qphy",
.cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY,
.set_path = set_mux_u3_gmac2_to_qphy,
+ }, {
+ .name = "mux_gmac2_to_2p5gphy",
+ .cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY,
+ .set_path = set_mux_gmac2_to_2p5gphy,
}, {
.name = "mux_gmac1_gmac2_to_sgmii_rgmii",
.cap_bit = MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII,
@@ -216,7 +295,15 @@ static const struct mtk_eth_muxc mtk_eth_muxc[] = {
}, {
.name = "mux_gmac12_to_gephy_sgmii",
.cap_bit = MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII,
- .set_path = set_mux_gmac12_to_gephy_sgmii,
+ .set_path = set_mux_gmac123_to_gephy_sgmii,
+ }, {
+ .name = "mux_gmac123_to_gephy_sgmii",
+ .cap_bit = MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII,
+ .set_path = set_mux_gmac123_to_gephy_sgmii,
+ }, {
+ .name = "mux_gmac123_to_usxgmii",
+ .cap_bit = MTK_ETH_MUX_GMAC123_TO_USXGMII,
+ .set_path = set_mux_gmac123_to_usxgmii,
},
};

@@ -249,12 +336,39 @@ static int mtk_eth_mux_setup(struct mtk_eth *eth, u64 path)
return err;
}

+int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id)
+{
+ u64 path;
+
+ path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_USXGMII :
+ (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_USXGMII :
+ MTK_ETH_PATH_GMAC3_USXGMII;
+
+ /* Setup proper MUXes along the path */
+ return mtk_eth_mux_setup(eth, path);
+}
+
int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)
{
u64 path;

- path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII :
- MTK_ETH_PATH_GMAC2_SGMII;
+ path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_SGMII :
+ (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_SGMII :
+ MTK_ETH_PATH_GMAC3_SGMII;
+
+ /* Setup proper MUXes along the path */
+ return mtk_eth_mux_setup(eth, path);
+}
+
+int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id)
+{
+ u64 path = 0;
+
+ if (mac_id == MTK_GMAC2_ID)
+ path = MTK_ETH_PATH_GMAC2_2P5GPHY;
+
+ if (!path)
+ return -EINVAL;

/* Setup proper MUXes along the path */
return mtk_eth_mux_setup(eth, path);
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index a6e91573f8dae..8663903d541f3 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -22,6 +22,8 @@
#include <linux/pinctrl/devinfo.h>
#include <linux/phylink.h>
#include <linux/pcs/pcs-mtk-lynxi.h>
+#include <linux/pcs/pcs-mtk-usxgmii.h>
+#include <linux/phy/phy.h>
#include <linux/jhash.h>
#include <linux/bitfield.h>
#include <net/dsa.h>
@@ -260,12 +262,8 @@ static const char * const mtk_clks_source_name[] = {
"ethwarp_wocpu2",
"ethwarp_wocpu1",
"ethwarp_wocpu0",
- "top_usxgmii0_sel",
- "top_usxgmii1_sel",
"top_sgm0_sel",
"top_sgm1_sel",
- "top_xfi_phy0_xtal_sel",
- "top_xfi_phy1_xtal_sel",
"top_eth_gmii_sel",
"top_eth_refck_50m_sel",
"top_eth_sys_200m_sel",
@@ -508,6 +506,30 @@ static void mtk_setup_bridge_switch(struct mtk_eth *eth)
MTK_GSW_CFG);
}

+static bool mtk_check_gmac23_idle(struct mtk_mac *mac)
+{
+ u32 mac_fsm, gdm_fsm;
+
+ mac_fsm = mtk_r32(mac->hw, MTK_MAC_FSM(mac->id));
+
+ switch (mac->id) {
+ case MTK_GMAC2_ID:
+ gdm_fsm = mtk_r32(mac->hw, MTK_FE_GDM2_FSM);
+ break;
+ case MTK_GMAC3_ID:
+ gdm_fsm = mtk_r32(mac->hw, MTK_FE_GDM3_FSM);
+ break;
+ default:
+ return true;
+ };
+
+ if ((mac_fsm & 0xFFFF0000) == 0x01010000 &&
+ (gdm_fsm & 0xFFFF0000) == 0x00000000)
+ return true;
+
+ return false;
+}
+
static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
phy_interface_t interface)
{
@@ -516,6 +538,21 @@ static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
struct mtk_eth *eth = mac->hw;
unsigned int sid;

+ if (mtk_is_netsys_v3_or_greater(eth)) {
+ switch (interface) {
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ case PHY_INTERFACE_MODE_SGMII:
+ return mtk_pcs_lynxi_select_pcs(mac->sgmii_pcs_of_node, interface);
+ case PHY_INTERFACE_MODE_5GBASER:
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_USXGMII:
+ return mtk_usxgmii_select_pcs(mac->usxgmii_pcs_of_node, interface);
+ default:
+ return NULL;
+ }
+ }
+
if (interface == PHY_INTERFACE_MODE_SGMII ||
phy_interface_mode_is_8023z(interface)) {
sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
@@ -567,7 +604,22 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
goto init_err;
}
break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_5GBASER:
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
+ err = mtk_gmac_usxgmii_path_setup(eth, mac->id);
+ if (err)
+ goto init_err;
+ }
+ break;
case PHY_INTERFACE_MODE_INTERNAL:
+ if (mac->id == MTK_GMAC2_ID &&
+ MTK_HAS_CAPS(eth->soc->caps, MTK_2P5GPHY)) {
+ err = mtk_gmac_2p5gphy_path_setup(eth, mac->id);
+ if (err)
+ goto init_err;
+ }
break;
default:
goto err_phy;
@@ -614,8 +666,6 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
-
- mac->interface = state->interface;
}

/* SGMII */
@@ -632,21 +682,40 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,

/* Save the syscfg0 value for mac_finish */
mac->syscfg0 = val;
- } else if (phylink_autoneg_inband(mode)) {
+ } else if (state->interface != PHY_INTERFACE_MODE_USXGMII &&
+ state->interface != PHY_INTERFACE_MODE_10GBASER &&
+ state->interface != PHY_INTERFACE_MODE_5GBASER &&
+ phylink_autoneg_inband(mode)) {
dev_err(eth->dev,
- "In-band mode not supported in non SGMII mode!\n");
+ "In-band mode not supported in non-SerDes modes!\n");
return;
}

/* Setup gmac */
- if (mtk_is_netsys_v3_or_greater(eth) &&
- mac->interface == PHY_INTERFACE_MODE_INTERNAL) {
- mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
- mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
+ if (mtk_is_netsys_v3_or_greater(eth)) {
+ if (mtk_interface_mode_is_xgmii(state->interface)) {
+ mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
+ mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));

- mtk_setup_bridge_switch(eth);
+ if (mac->id == MTK_GMAC1_ID)
+ mtk_setup_bridge_switch(eth);
+ } else {
+ mtk_w32(eth, 0, MTK_GDMA_EG_CTRL(mac->id));
+
+ /* FIXME: In current hardware design, we have to reset FE
+ * when swtiching XGDM to GDM. Therefore, here trigger an SER
+ * to let GDM go back to the initial state.
+ */
+ if ((mtk_interface_mode_is_xgmii(mac->interface) ||
+ mac->interface == PHY_INTERFACE_MODE_NA) &&
+ !mtk_check_gmac23_idle(mac) &&
+ !test_bit(MTK_RESETTING, &eth->state))
+ schedule_work(&eth->pending_work);
+ }
}

+ mac->interface = state->interface;
+
return;

err_phy:
@@ -659,6 +728,18 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
mac->id, phy_modes(state->interface), err);
}

+static int mtk_mac_prepare(struct phylink_config *config, unsigned int mode,
+ phy_interface_t interface)
+{
+ struct mtk_mac *mac = container_of(config, struct mtk_mac,
+ phylink_config);
+
+ if (mac->pextp && mac->interface != interface)
+ phy_reset(mac->pextp);
+
+ return 0;
+}
+
static int mtk_mac_finish(struct phylink_config *config, unsigned int mode,
phy_interface_t interface)
{
@@ -667,6 +748,10 @@ static int mtk_mac_finish(struct phylink_config *config, unsigned int mode,
struct mtk_eth *eth = mac->hw;
u32 mcr_cur, mcr_new;

+ /* Setup PMA/PMD */
+ if (mac->pextp)
+ phy_set_mode_ext(mac->pextp, PHY_MODE_ETHERNET, interface);
+
/* Enable SGMII */
if (interface == PHY_INTERFACE_MODE_SGMII ||
phy_interface_mode_is_8023z(interface))
@@ -692,10 +777,13 @@ static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
{
struct mtk_mac *mac = container_of(config, struct mtk_mac,
phylink_config);
- u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));

- mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
- mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
+ if (!mtk_interface_mode_is_xgmii(interface)) {
+ mtk_m32(mac->hw, MAC_MCR_TX_EN | MAC_MCR_RX_EN, 0, MTK_MAC_MCR(mac->id));
+ mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0, MTK_XGMAC_STS(mac->id));
+ } else if (mac->id != MTK_GMAC1_ID) {
+ mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE, XMAC_MCR_TRX_DISABLE, MTK_XMAC_MCR(mac->id));
+ }
}

static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
@@ -767,13 +855,11 @@ static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
}

-static void mtk_mac_link_up(struct phylink_config *config,
- struct phy_device *phy,
- unsigned int mode, phy_interface_t interface,
- int speed, int duplex, bool tx_pause, bool rx_pause)
+static void mtk_gdm_mac_link_up(struct mtk_mac *mac,
+ struct phy_device *phy,
+ unsigned int mode, phy_interface_t interface,
+ int speed, int duplex, bool tx_pause, bool rx_pause)
{
- struct mtk_mac *mac = container_of(config, struct mtk_mac,
- phylink_config);
u32 mcr;

mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
@@ -807,9 +893,63 @@ static void mtk_mac_link_up(struct phylink_config *config,
mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
}

+static void mtk_xgdm_mac_link_up(struct mtk_mac *mac,
+ struct phy_device *phy,
+ unsigned int mode, phy_interface_t interface,
+ int speed, int duplex, bool tx_pause, bool rx_pause)
+{
+ u32 mcr, force_link = 0;
+
+ if (mac->id == MTK_GMAC1_ID)
+ return;
+
+ /* Eliminate the interference(before link-up) caused by PHY noise */
+ mtk_m32(mac->hw, XMAC_LOGIC_RST, 0, MTK_XMAC_LOGIC_RST(mac->id));
+ mdelay(20);
+ mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR, MTK_XMAC_CNT_CTRL(mac->id));
+
+ if (mac->interface == PHY_INTERFACE_MODE_INTERNAL || mac->id == MTK_GMAC3_ID)
+ force_link = MTK_XGMAC_FORCE_LINK(mac->id);
+
+ mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), force_link, MTK_XGMAC_STS(mac->id));
+
+ mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
+ mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC | XMAC_MCR_TRX_DISABLE);
+ /* Configure pause modes -
+ * phylink will avoid these for half duplex
+ */
+ if (tx_pause)
+ mcr |= XMAC_MCR_FORCE_TX_FC;
+ if (rx_pause)
+ mcr |= XMAC_MCR_FORCE_RX_FC;
+
+ mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
+}
+
+static void mtk_mac_link_up(struct phylink_config *config,
+ struct phy_device *phy,
+ unsigned int mode, phy_interface_t interface,
+ int speed, int duplex, bool tx_pause, bool rx_pause)
+{
+ struct mtk_mac *mac = container_of(config, struct mtk_mac,
+ phylink_config);
+
+ if (mtk_interface_mode_is_xgmii(interface))
+ mtk_xgdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
+ tx_pause, rx_pause);
+ else
+ mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
+ tx_pause, rx_pause);
+
+ /* Repeat pextp setup to tune link */
+ if (mac->pextp)
+ phy_set_mode_ext(mac->pextp, PHY_MODE_ETHERNET, interface);
+}
+
static const struct phylink_mac_ops mtk_phylink_ops = {
.mac_select_pcs = mtk_mac_select_pcs,
.mac_config = mtk_mac_config,
+ .mac_prepare = mtk_mac_prepare,
.mac_finish = mtk_mac_finish,
.mac_link_down = mtk_mac_link_down,
.mac_link_up = mtk_mac_link_up,
@@ -3359,6 +3499,9 @@ static int mtk_open(struct net_device *dev)
struct mtk_eth *eth = mac->hw;
int i, err;

+ if (mac->pextp)
+ phy_power_on(mac->pextp);
+
err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
if (err) {
netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
@@ -3488,6 +3631,9 @@ static int mtk_stop(struct net_device *dev)
for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
mtk_ppe_stop(eth->ppe[i]);

+ if (mac->pextp)
+ phy_power_off(mac->pextp);
+
return 0;
}

@@ -4487,6 +4633,7 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
const __be32 *_id = of_get_property(np, "reg", NULL);
phy_interface_t phy_mode;
struct phylink *phylink;
+ struct phylink_pcs *pcs = NULL;
struct mtk_mac *mac;
int id, err;
int txqs = 1;
@@ -4521,16 +4668,39 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
mac->id = id;
mac->hw = eth;
mac->of_node = np;
+ mac->sgmii_pcs_of_node = of_parse_phandle(mac->of_node, "pcs-handle", 0);
+ if (mac->sgmii_pcs_of_node) {
+ pcs = mtk_pcs_lynxi_select_pcs(mac->sgmii_pcs_of_node, PHY_INTERFACE_MODE_NA);
+ if (IS_ERR(pcs)) {
+ if (PTR_ERR(pcs) != -EPROBE_DEFER)
+ dev_err(eth->dev, "cannot select SGMII PCS, error %ld\n",
+ PTR_ERR(pcs));
+
+ return PTR_ERR(pcs);
+ }
+ }

- err = of_get_ethdev_address(mac->of_node, eth->netdev[id]);
- if (err == -EPROBE_DEFER)
- return err;
+ mac->usxgmii_pcs_of_node = of_parse_phandle(mac->of_node, "pcs-handle", 1);
+ if (mac->usxgmii_pcs_of_node) {
+ pcs = mtk_usxgmii_select_pcs(mac->usxgmii_pcs_of_node, PHY_INTERFACE_MODE_NA);
+ if (IS_ERR(pcs)) {
+ if (PTR_ERR(pcs) != -EPROBE_DEFER)
+ dev_err(eth->dev, "cannot select USXGMII PCS, error %ld\n",
+ PTR_ERR(pcs));

- if (err) {
- /* If the mac address is invalid, use random mac address */
- eth_hw_addr_random(eth->netdev[id]);
- dev_err(eth->dev, "generated random MAC address %pM\n",
- eth->netdev[id]->dev_addr);
+ return PTR_ERR(pcs);
+ }
+ }
+
+ if (pcs && mtk_is_netsys_v3_or_greater(eth)) {
+ mac->pextp = devm_of_phy_get(eth->dev, mac->of_node, NULL);
+ if (IS_ERR(mac->pextp)) {
+ if (PTR_ERR(mac->pextp) != -EPROBE_DEFER)
+ dev_err(eth->dev, "cannot get PHY, error %ld\n",
+ PTR_ERR(mac->pextp));
+
+ return PTR_ERR(mac->pextp);
+ }
}

memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
@@ -4613,8 +4783,21 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
phy_interface_zero(mac->phylink_config.supported_interfaces);
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
mac->phylink_config.supported_interfaces);
+ } else if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_USXGMII)) {
+ mac->phylink_config.mac_capabilities |= MAC_5000FD | MAC_10000FD;
+ __set_bit(PHY_INTERFACE_MODE_5GBASER,
+ mac->phylink_config.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_10GBASER,
+ mac->phylink_config.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII,
+ mac->phylink_config.supported_interfaces);
}

+ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_2P5GPHY) &&
+ id == MTK_GMAC2_ID)
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ mac->phylink_config.supported_interfaces);
+
phylink = phylink_create(&mac->phylink_config,
of_fwnode_handle(mac->of_node),
phy_mode, &mtk_phylink_ops);
@@ -4665,6 +4848,26 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
return err;
}

+static int mtk_mac_assign_address(struct mtk_eth *eth, int i, bool test_defer_only)
+{
+ int err = of_get_ethdev_address(eth->mac[i]->of_node, eth->netdev[i]);
+
+ if (err == -EPROBE_DEFER)
+ return err;
+
+ if (test_defer_only)
+ return 0;
+
+ if (err) {
+ /* If the mac address is invalid, use random mac address */
+ eth_hw_addr_random(eth->netdev[i]);
+ dev_err(eth->dev, "generated random MAC address %pM\n",
+ eth->netdev[i]);
+ }
+
+ return 0;
+}
+
void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
{
struct net_device *dev, *tmp;
@@ -4808,7 +5011,8 @@ static int mtk_probe(struct platform_device *pdev)
regmap_write(cci, 0, 3);
}

- if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII) &&
+ !mtk_is_netsys_v3_or_greater(eth)) {
err = mtk_sgmii_init(eth);

if (err)
@@ -4919,6 +5123,24 @@ static int mtk_probe(struct platform_device *pdev)
}
}

+ for (i = 0; i < MTK_MAX_DEVS; i++) {
+ if (!eth->netdev[i])
+ continue;
+
+ err = mtk_mac_assign_address(eth, i, true);
+ if (err)
+ goto err_deinit_hw;
+ }
+
+ for (i = 0; i < MTK_MAX_DEVS; i++) {
+ if (!eth->netdev[i])
+ continue;
+
+ err = mtk_mac_assign_address(eth, i, false);
+ if (err)
+ goto err_deinit_hw;
+ }
+
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
err = devm_request_irq(eth->dev, eth->irq[0],
mtk_handle_irq, 0,
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 9ae3b8a71d0e6..c021fc6efe0f5 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -15,6 +15,7 @@
#include <linux/u64_stats_sync.h>
#include <linux/refcount.h>
#include <linux/phylink.h>
+#include <linux/reset.h>
#include <linux/rhashtable.h>
#include <linux/dim.h>
#include <linux/bitfield.h>
@@ -503,6 +504,21 @@
#define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
#define INTF_MODE_RGMII_10_100 0

+/* XFI Mac control registers */
+#define MTK_XMAC_BASE(x) (0x12000 + (((x) - 1) * 0x1000))
+#define MTK_XMAC_MCR(x) (MTK_XMAC_BASE(x))
+#define XMAC_MCR_TRX_DISABLE 0xf
+#define XMAC_MCR_FORCE_TX_FC BIT(5)
+#define XMAC_MCR_FORCE_RX_FC BIT(4)
+
+/* XFI Mac logic reset registers */
+#define MTK_XMAC_LOGIC_RST(x) (MTK_XMAC_BASE(x) + 0x10)
+#define XMAC_LOGIC_RST BIT(0)
+
+/* XFI Mac count global control */
+#define MTK_XMAC_CNT_CTRL(x) (MTK_XMAC_BASE(x) + 0x100)
+#define XMAC_GLB_CNTCLR BIT(0)
+
/* GPIO port control registers for GMAC 2*/
#define GPIO_OD33_CTRL8 0x4c0
#define GPIO_BIAS_CTRL 0xed0
@@ -528,6 +544,7 @@
#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
#define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
#define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
+#define SYSCFG0_SGMII_GMAC3_V2 BIT(7)

/* ethernet subsystem clock register */
@@ -566,6 +583,11 @@
#define GEPHY_MAC_SEL BIT(1)

/* Top misc registers */
+#define TOP_MISC_NETSYS_PCS_MUX 0x84
+#define NETSYS_PCS_MUX_MASK GENMASK(1, 0)
+#define MUX_G2_USXGMII_SEL BIT(1)
+#define MUX_HSGMII1_G1_SEL BIT(0)
+
#define USB_PHY_SWITCH_REG 0x218
#define QPHY_SEL_MASK GENMASK(1, 0)
#define SGMII_QPHY_SEL 0x2
@@ -590,6 +612,8 @@
#define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
#define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)

+/* Debug Purpose Register */
+#define MTK_PSE_FQFC_CFG 0x100
#define MTK_FE_CDM1_FSM 0x220
#define MTK_FE_CDM2_FSM 0x224
#define MTK_FE_CDM3_FSM 0x238
@@ -598,6 +622,11 @@
#define MTK_FE_CDM6_FSM 0x328
#define MTK_FE_GDM1_FSM 0x228
#define MTK_FE_GDM2_FSM 0x22C
+#define MTK_FE_GDM3_FSM 0x23C
+#define MTK_FE_PSE_FREE 0x240
+#define MTK_FE_DROP_FQ 0x244
+#define MTK_FE_DROP_FC 0x248
+#define MTK_FE_DROP_PPE 0x24C

#define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100))

@@ -722,12 +751,8 @@ enum mtk_clks_map {
MTK_CLK_ETHWARP_WOCPU2,
MTK_CLK_ETHWARP_WOCPU1,
MTK_CLK_ETHWARP_WOCPU0,
- MTK_CLK_TOP_USXGMII_SBUS_0_SEL,
- MTK_CLK_TOP_USXGMII_SBUS_1_SEL,
MTK_CLK_TOP_SGM_0_SEL,
MTK_CLK_TOP_SGM_1_SEL,
- MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,
- MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,
MTK_CLK_TOP_ETH_GMII_SEL,
MTK_CLK_TOP_ETH_REFCK_50M_SEL,
MTK_CLK_TOP_ETH_SYS_200M_SEL,
@@ -798,19 +823,9 @@ enum mtk_clks_map {
BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
BIT_ULL(MTK_CLK_CRYPTO) | \
- BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
- BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
- BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
- BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
- BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \
- BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \
- BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \
- BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \
- BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \
- BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \
BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
@@ -944,6 +959,8 @@ enum mkt_eth_capabilities {
MTK_RGMII_BIT = 0,
MTK_TRGMII_BIT,
MTK_SGMII_BIT,
+ MTK_USXGMII_BIT,
+ MTK_2P5GPHY_BIT,
MTK_ESW_BIT,
MTK_GEPHY_BIT,
MTK_MUX_BIT,
@@ -964,8 +981,11 @@ enum mkt_eth_capabilities {
MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
+ MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT,
MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
+ MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT,
+ MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT,

/* PATH BITS */
MTK_ETH_PATH_GMAC1_RGMII_BIT,
@@ -973,14 +993,21 @@ enum mkt_eth_capabilities {
MTK_ETH_PATH_GMAC1_SGMII_BIT,
MTK_ETH_PATH_GMAC2_RGMII_BIT,
MTK_ETH_PATH_GMAC2_SGMII_BIT,
+ MTK_ETH_PATH_GMAC2_2P5GPHY_BIT,
MTK_ETH_PATH_GMAC2_GEPHY_BIT,
+ MTK_ETH_PATH_GMAC3_SGMII_BIT,
MTK_ETH_PATH_GDM1_ESW_BIT,
+ MTK_ETH_PATH_GMAC1_USXGMII_BIT,
+ MTK_ETH_PATH_GMAC2_USXGMII_BIT,
+ MTK_ETH_PATH_GMAC3_USXGMII_BIT,
};

/* Supported hardware group on SoCs */
#define MTK_RGMII BIT_ULL(MTK_RGMII_BIT)
#define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT)
#define MTK_SGMII BIT_ULL(MTK_SGMII_BIT)
+#define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT)
+#define MTK_2P5GPHY BIT_ULL(MTK_2P5GPHY_BIT)
#define MTK_ESW BIT_ULL(MTK_ESW_BIT)
#define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
#define MTK_MUX BIT_ULL(MTK_MUX_BIT)
@@ -1003,10 +1030,16 @@ enum mkt_eth_capabilities {
BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
+#define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \
+ BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT)
#define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
#define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
+#define MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII \
+ BIT_ULL(MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT)
+#define MTK_ETH_MUX_GMAC123_TO_USXGMII \
+ BIT_ULL(MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT)

/* Supported path present on SoCs */
#define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
@@ -1014,8 +1047,13 @@ enum mkt_eth_capabilities {
#define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
#define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
#define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
+#define MTK_ETH_PATH_GMAC2_2P5GPHY BIT_ULL(MTK_ETH_PATH_GMAC2_2P5GPHY_BIT)
#define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
+#define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT)
#define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
+#define MTK_ETH_PATH_GMAC1_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC1_USXGMII_BIT)
+#define MTK_ETH_PATH_GMAC2_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC2_USXGMII_BIT)
+#define MTK_ETH_PATH_GMAC3_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC3_USXGMII_BIT)

#define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
@@ -1023,7 +1061,12 @@ enum mkt_eth_capabilities {
#define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
#define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
#define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
+#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY)
+#define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII)
#define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
+#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII)
+#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII)
+#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII)

/* MUXes present on SoCs */
/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
@@ -1042,10 +1085,20 @@ enum mkt_eth_capabilities {
(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
MTK_SHARED_SGMII)

+/* 2: GMAC2 -> XGMII */
+#define MTK_MUX_GMAC2_TO_2P5GPHY \
+ (MTK_ETH_MUX_GMAC2_TO_2P5GPHY | MTK_MUX | MTK_INFRA)
+
/* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
#define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)

+#define MTK_MUX_GMAC123_TO_GEPHY_SGMII \
+ (MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX)
+
+#define MTK_MUX_GMAC123_TO_USXGMII \
+ (MTK_ETH_MUX_GMAC123_TO_USXGMII | MTK_MUX | MTK_INFRA)
+
#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))

#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
@@ -1077,8 +1130,12 @@ enum mkt_eth_capabilities {
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
MTK_RSTCTRL_PPE1 | MTK_SRAM)

-#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_QDMA | \
- MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)
+#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC1_SGMII | \
+ MTK_GMAC2_2P5GPHY | MTK_GMAC2_SGMII | MTK_GMAC2_USXGMII | \
+ MTK_GMAC3_SGMII | MTK_GMAC3_USXGMII | \
+ MTK_MUX_GMAC123_TO_GEPHY_SGMII | \
+ MTK_MUX_GMAC123_TO_USXGMII | MTK_MUX_GMAC2_TO_2P5GPHY | \
+ MTK_QDMA | MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)

struct mtk_tx_dma_desc_info {
dma_addr_t addr;
@@ -1313,6 +1370,9 @@ struct mtk_mac {
phy_interface_t interface;
int speed;
struct device_node *of_node;
+ struct device_node *sgmii_pcs_of_node;
+ struct device_node *usxgmii_pcs_of_node;
+ struct phy *pextp;
struct phylink *phylink;
struct phylink_config phylink_config;
struct mtk_eth *hw;
@@ -1421,6 +1481,19 @@ static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth)
return MTK_FOE_IB2_MULTICAST;
}

+static inline bool mtk_interface_mode_is_xgmii(phy_interface_t interface)
+{
+ switch (interface) {
+ case PHY_INTERFACE_MODE_INTERNAL:
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_5GBASER:
+ return true;
+ default:
+ return false;
+ }
+}
+
/* read the hardware status register */
void mtk_stats_update_mac(struct mtk_mac *mac);

@@ -1429,8 +1502,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);

int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
+int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id);
int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
+int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id);

int mtk_eth_offload_init(struct mtk_eth *eth);
int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
--
2.43.0

2023-12-06 03:39:55

[permalink] [raw]

Subject: Re: [RFC PATCH v2 1/8] dt-bindings: phy: mediatek,xfi-pextp: add new bindings

On Wed, 06 Dec 2023 01:43:55 +0000, Daniel Golle wrote:
> Add bindings for the MediaTek PEXTP Ethernet SerDes PHY found in the
> MediaTek MT7988 SoC which can operate at various interfaces modes:
>
> * USXGMII
> * 10GBase-R
> * 5GBase-R
> * 2500Base-X
> * 1000Base-X
> * Cisco SGMII (MAC side)
>
> Signed-off-by: Daniel Golle <[email protected]>
> ---
> .../bindings/phy/mediatek,xfi-pextp.yaml | 80 +++++++++++++++++++
> 1 file changed, 80 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml
>

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:
./Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml:33:16: [error] string value is redundantly quoted with any quotes (quoted-strings)
./Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml:34:16: [error] string value is redundantly quoted with any quotes (quoted-strings)

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.example.dts:18:18: fatal error: dt-bindings/clock/mediatek,mt7988-clk.h: No such file or directory
18 | #include <dt-bindings/clock/mediatek,mt7988-clk.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[2]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1424: dt_binding_check] Error 2
make: *** [Makefile:234: __sub-make] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/f57cc2bfadca35219707a0af507ad6e2e354e311.1701826319.git.daniel@makrotopia.org

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

2023-12-06 03:40:13

[permalink] [raw]

Subject: Re: [RFC PATCH v2 6/8] dt-bindings: net: mediatek: remove wrongly added clocks and SerDes

On Wed, 06 Dec 2023 01:44:51 +0000, Daniel Golle wrote:
> Several clocks as well as both sgmiisys phandles were added by mistake
> to the Ethernet bindings for MT7988.
>
> This happened because the vendor driver which served as a reference
> uses a high number of syscon phandles to access various parts of the
> SoC which wasn't acceptable upstream. Hence several parts which have
> never previously been supported (such SerDes PHY and USXGMII PCS) have
> been moved to separate drivers which also result in a much more sane
> device tree.
>
> Quickly align the bindings with the upcoming reality of the drivers
> actually adding full support for this SoC.
>
> Fixes: c94a9aabec36 ("dt-bindings: net: mediatek,net: add mt7988-eth binding")
> Signed-off-by: Daniel Golle <[email protected]>
> ---
> .../devicetree/bindings/net/mediatek,net.yaml | 32 ++++---------------
> 1 file changed, 7 insertions(+), 25 deletions(-)
>

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.example.dts:18:18: fatal error: dt-bindings/clock/mediatek,mt7988-clk.h: No such file or directory
make[2]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.example.dtb] Error 1

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/e2214e904cde9a9d64ec1e87ac38560f7ac35a1f.1701826319.git.daniel@makrotopia.org

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

2023-12-06 03:40:14

[permalink] [raw]

Subject: Re: [RFC PATCH v2 7/8] dt-bindings: net: mediatek,net: fix and complete mt7988-eth binding

On Wed, 06 Dec 2023 01:45:02 +0000, Daniel Golle wrote:
> Complete support for MT7988 which comes with 3 MACs, SRAM for DMA
> descriptors and uses a dedicated PCS for the SerDes units.
>
> Fixes: c94a9aabec36 ("dt-bindings: net: mediatek,net: add mt7988-eth binding")
> Signed-off-by: Daniel Golle <[email protected]>
> ---
> .../devicetree/bindings/net/mediatek,net.yaml | 148 +++++++++++++++++-
> 1 file changed, 146 insertions(+), 2 deletions(-)
>

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/net/mediatek,net.example.dts:231:18: fatal error: dt-bindings/clock/mediatek,mt7988-clk.h: No such file or directory
231 | #include <dt-bindings/clock/mediatek,mt7988-clk.h>
make[2]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/net/mediatek,net.example.dtb] Error 1

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/567c6aaa64ecb4872056bc0105c70153fd9d9b50.1701826319.git.daniel@makrotopia.org

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

2023-12-06 03:40:51

[permalink] [raw]

Subject: Re: [RFC PATCH v2 4/8] dt-bindings: net: pcs: add bindings for MediaTek USXGMII PCS

On Wed, 06 Dec 2023 01:44:27 +0000, Daniel Golle wrote:
> MediaTek's USXGMII can be found in the MT7988 SoC. We need to access
> it in order to configure and monitor the Ethernet SerDes link in
> USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped
> legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those
> interface modes are also available.
>
> Signed-off-by: Daniel Golle <[email protected]>
> ---
> .../bindings/net/pcs/mediatek,usxgmii.yaml | 100 ++++++++++++++++++
> 1 file changed, 100 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
>

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.example.dts:18:18: fatal error: dt-bindings/clock/mediatek,mt7988-clk.h: No such file or directory
make[2]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.example.dtb] Error 1

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/14c3eb3022fac2af105950eb161990ecfb17c016.1701826319.git.daniel@makrotopia.org

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

2023-12-06 03:41:21

[permalink] [raw]

Subject: Re: [RFC PATCH v2 5/8] net: pcs: add driver for MediaTek USXGMII PCS

On Wed, 06 Dec 2023 01:44:38 +0000, Daniel Golle wrote:
> Add driver for USXGMII PCS found in the MediaTek MT7988 SoC and supporting
> USXGMII, 10GBase-R and 5GBase-R interface modes. In order to support
> Cisco SGMII, 1000Base-X and 2500Base-X via the also present LynxI PCS
> create a wrapped PCS taking care of the components shared between the
> new USXGMII PCS and the legacy LynxI PCS.
>
> Signed-off-by: Daniel Golle <[email protected]>
> ---
> .../bindings/net/pcs/mediatek,usxgmii.yaml | 46 +-
> MAINTAINERS | 2 +
> drivers/net/pcs/Kconfig | 11 +
> drivers/net/pcs/Makefile | 1 +
> drivers/net/pcs/pcs-mtk-usxgmii.c | 413 ++++++++++++++++++
> include/linux/pcs/pcs-mtk-usxgmii.h | 26 ++
> 6 files changed, 456 insertions(+), 43 deletions(-)
> create mode 100644 drivers/net/pcs/pcs-mtk-usxgmii.c
> create mode 100644 include/linux/pcs/pcs-mtk-usxgmii.h
>

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/3cd8af5e44554c2db2d7898494ee813967206bd9.1701826319.git.daniel@makrotopia.org

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

2023-12-06 09:38:40

[permalink] [raw]

Subject: Re: [RFC PATCH v2 3/8] net: pcs: pcs-mtk-lynxi: add platform driver for MT7988

Hello Daniel,

My two cents below :

On Wed, 6 Dec 2023 01:44:17 +0000
Daniel Golle <[email protected]> wrote:

> Introduce a proper platform MFD driver for the LynxI (H)SGMII PCS which
> is going to initially be used for the MT7988 SoC.
>
> Signed-off-by: Daniel Golle <[email protected]>

[ ... ]

> +static int mtk_pcs_lynxi_enable(struct phylink_pcs *pcs)
> +{
> + struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
> +
> + if (mpcs->sgmii_tx && mpcs->sgmii_rx) {
> + clk_prepare_enable(mpcs->sgmii_rx);
> + clk_prepare_enable(mpcs->sgmii_tx);

You can use the clk_bulk_prepare_enable() here

> + }
> +
> + return 0;
> +}
> +
> static void mtk_pcs_lynxi_disable(struct phylink_pcs *pcs)
> {
> struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
>
> + regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
> +
> + if (mpcs->sgmii_tx && mpcs->sgmii_rx) {
> + clk_disable_unprepare(mpcs->sgmii_tx);
> + clk_disable_unprepare(mpcs->sgmii_rx);

and clk_bulk_disable_unprepare() here

[...]

> +static int mtk_pcs_lynxi_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct mtk_pcs_lynxi *mpcs;
> + struct phylink_pcs *pcs;
> + struct regmap *regmap;
> + u32 flags = 0;
> +
> + mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL);
> + if (!mpcs)
> + return -ENOMEM;
> +
> + regmap = syscon_node_to_regmap(np->parent);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + if (of_property_read_bool(np->parent, "mediatek,pnswap"))
> + flags |= MTK_SGMII_FLAG_PN_SWAP;
> +
> + mpcs->rstc = of_reset_control_get_shared(np->parent, NULL);
> + if (IS_ERR(mpcs->rstc))
> + return PTR_ERR(mpcs->rstc);
> +
> + reset_control_deassert(mpcs->rstc);
> + mpcs->sgmii_sel = devm_clk_get_enabled(dev, "sgmii_sel");
> + if (IS_ERR(mpcs->sgmii_sel))
> + return PTR_ERR(mpcs->sgmii_sel);
> +
> + mpcs->sgmii_rx = devm_clk_get(dev, "sgmii_rx");
> + if (IS_ERR(mpcs->sgmii_rx))
> + return PTR_ERR(mpcs->sgmii_rx);
> +
> + mpcs->sgmii_tx = devm_clk_get(dev, "sgmii_tx");
> + if (IS_ERR(mpcs->sgmii_tx))
> + return PTR_ERR(mpcs->sgmii_tx);

and clk bulk operations here as well ?

Maxime

2023-12-06 09:46:29

[permalink] [raw]

Subject: Re: [RFC PATCH v2 2/8] phy: add driver for MediaTek pextp 10GE SerDes PHY

Hello Daniel,

On Wed, 6 Dec 2023 01:44:08 +0000
Daniel Golle <[email protected]> wrote:

> Add driver for MediaTek's pextp 10 Gigabit/s Ethernet SerDes PHY which
> can be found in the MT7988 SoC.
>
> The PHY can operates only in PHY_MODE_ETHERNET, the submode is one of
> PHY_INTERFACE_MODE_* corresponding to the supported modes:
>
> * USXGMII
> * 10GBase-R
> * 5GBase-R
> * 2500Base-X
> * 1000Base-X
> * Cisco SGMII (MAC side)
>
> In order to work-around a performance issue present on the first of
> two PEXTP present in MT7988 special tuning is applied which can be
> selected by adding the mediatek,usxgmii-performance-errata property to
> the device tree node.
>
> There is no documentation what-so-ever for the pextp registers and
> this driver is based on a GPL licensed implementation found in
> MediaTek's SDK.
>
> Signed-off-by: Daniel Golle <[email protected]>
> ---

[...]

> +
> +static int mtk_pextp_power_on(struct phy *phy)
> +{
> + struct mtk_pextp_phy *pextp = phy_get_drvdata(phy);
> + int ret;
> +
> + ret = clk_prepare_enable(pextp->clk[0]);
> + if (ret)
> + return ret;
> +
> + return clk_prepare_enable(pextp->clk[1]);
> +}

clk_bulk operations could be used here

> +static int mtk_pextp_power_off(struct phy *phy)
> +{
> + struct mtk_pextp_phy *pextp = phy_get_drvdata(phy);
> +
> + clk_disable_unprepare(pextp->clk[1]);
> + clk_disable_unprepare(pextp->clk[0]);
> +
> + return 0;
> +}

Here

> +static const struct phy_ops mtk_pextp_ops = {
> + .power_on = mtk_pextp_power_on,
> + .power_off = mtk_pextp_power_off,
> + .set_mode = mtk_pextp_set_mode,
> + .reset = mtk_pextp_reset,
> + .owner = THIS_MODULE,
> +};
> +
> +static int mtk_pextp_probe(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct phy_provider *phy_provider;
> + struct mtk_pextp_phy *pextp;
> + struct phy *phy;
> +
> + if (!np)
> + return -ENODEV;
> +
> + pextp = devm_kzalloc(&pdev->dev, sizeof(*pextp), GFP_KERNEL);
> + if (!pextp)
> + return -ENOMEM;
> +
> + pextp->base = devm_of_iomap(&pdev->dev, np, 0, NULL);
> + if (!pextp->base)
> + return -EIO;
> +
> + pextp->dev = &pdev->dev;
> + pextp->clk[0] = devm_clk_get(&pdev->dev, "topxtal");
> + if (IS_ERR(pextp->clk[0]))
> + return PTR_ERR(pextp->clk[0]);
> +
> + pextp->clk[1] = devm_clk_get(&pdev->dev, "xfipll");
> + if (IS_ERR(pextp->clk[1]))
> + return PTR_ERR(pextp->clk[1]);

And here as well.

Thanks,

Maxime

2023-12-06 09:59:01

[permalink] [raw]

Subject: Re: [RFC PATCH v2 5/8] net: pcs: add driver for MediaTek USXGMII PCS

Hello Daniel,

On Wed, 6 Dec 2023 01:44:38 +0000
Daniel Golle <[email protected]> wrote:

> Add driver for USXGMII PCS found in the MediaTek MT7988 SoC and supporting
> USXGMII, 10GBase-R and 5GBase-R interface modes. In order to support
> Cisco SGMII, 1000Base-X and 2500Base-X via the also present LynxI PCS
> create a wrapped PCS taking care of the components shared between the
> new USXGMII PCS and the legacy LynxI PCS.
>
> Signed-off-by: Daniel Golle <[email protected]>
> ---

[...]

> +
> +static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
> + phy_interface_t interface,
> + const unsigned long *advertising,
> + bool permit_pause_to_mac)
> +{
> + struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
> + unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0;
> + bool mode_changed = false;

Reverse christmas tree ordering can be used here (longest lines first)

> +
> + if (interface == PHY_INTERFACE_MODE_USXGMII) {
> + an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | USXGMII_AN_ENABLE;
> + link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
> + FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
> + FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
> + xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_10G) |
> + FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_10G);
> + } else if (interface == PHY_INTERFACE_MODE_10GBASER) {
> + an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF);
> + link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
> + FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
> + FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
> + xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_10G) |
> + FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_10G);
> + adapt_mode = USXGMII_RATE_UPDATE_MODE;
> + } else if (interface == PHY_INTERFACE_MODE_5GBASER) {
> + an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF);
> + link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) |
> + FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) |
> + FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D);
> + xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_5G) |
> + FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_5G);
> + adapt_mode = USXGMII_RATE_UPDATE_MODE;
> + } else {
> + return -EINVAL;
> + }
> +
> + adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1);
> +
> + if (mpcs->interface != interface) {
> + mpcs->interface = interface;
> + mode_changed = true;
> + }
> +
> + mtk_usxgmii_reset(mpcs);
> +
> + /* Setup USXGMII AN ctrl */
> + mtk_m32(mpcs, RG_PCS_AN_CTRL0,
> + USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
> + an_ctrl);
> +
> + mtk_m32(mpcs, RG_PCS_AN_CTRL2,
> + USXGMII_LINK_TIMER_IDLE_DETECT |
> + USXGMII_LINK_TIMER_COMP_ACK_DETECT |
> + USXGMII_LINK_TIMER_AN_RESTART,
> + link_timer);
> +
> + mpcs->neg_mode = neg_mode;
> +
> + /* Gated MAC CK */
> + mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
> + USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED);
> +
> + /* Enable interface force mode */
> + mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
> + USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN);
> +
> + /* Setup USXGMII adapt mode */
> + mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
> + USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE,
> + adapt_mode);
> +
> + /* Setup USXGMII speed */
> + mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
> + USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE,
> + xfi_mode);
> +
> + usleep_range(1, 10);
> +
> + /* Un-gated MAC CK */
> + mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1, USXGMII_MAC_CK_GATED, 0);
> +
> + usleep_range(1, 10);
> +
> + /* Disable interface force mode for the AN mode */
> + if (an_ctrl & USXGMII_AN_ENABLE)
> + mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1, USXGMII_IF_FORCE_EN, 0);
> +
> + return mode_changed;
> +}
> +

[...]

> +static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs,
> + struct phylink_link_state *state)
> +{
> + struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
> +
> + /* Refresh USXGMII link status by toggling RG_PCS_AN_STATUS_UPDATE */
> + mtk_m32(mpcs, RG_PCS_RX_STATUS0, RG_PCS_RX_STATUS_UPDATE,
> + RG_PCS_RX_STATUS_UPDATE);
> + ndelay(1020);
> + mtk_m32(mpcs, RG_PCS_RX_STATUS0, RG_PCS_RX_STATUS_UPDATE, 0);
> + ndelay(1020);
> +
> + /* Read USXGMII link status */
> + state->link = FIELD_GET(RG_PCS_RX_LINK_STATUS,
> + mtk_r32(mpcs, RG_PCS_RX_STATUS0));
> +
> + /* Continuously repeat re-configuration sequence until link comes up */
> + if (!state->link) {
> + mtk_usxgmii_pcs_config(pcs, mpcs->neg_mode,
> + state->interface, NULL, false);
> + return;

.pcs_get_state() isn't called only for link state polling,but also when querying
the link state from ethtool, from phylink_ethtool_ksettings_get().

As mtk_usxgmii_pcs_config triggers a pcs reset and reconfiguration, won't this disrupt
the link ?

Thanks,

Maxime

2023-12-06 13:34:18

[permalink] [raw]

Subject: Re: [RFC PATCH v2 5/8] net: pcs: add driver for MediaTek USXGMII PCS

On Wed, Dec 06, 2023 at 01:44:38AM +0000, Daniel Golle wrote:
> Add driver for USXGMII PCS found in the MediaTek MT7988 SoC and supporting
> USXGMII, 10GBase-R and 5GBase-R interface modes. In order to support
> Cisco SGMII, 1000Base-X and 2500Base-X via the also present LynxI PCS
> create a wrapped PCS taking care of the components shared between the
> new USXGMII PCS and the legacy LynxI PCS.
>
> Signed-off-by: Daniel Golle <[email protected]>
> ---
> .../bindings/net/pcs/mediatek,usxgmii.yaml | 46 +-

Why are you changing the binding you just added?

In any case, bindings are separate patches.

> MAINTAINERS | 2 +
> drivers/net/pcs/Kconfig | 11 +
> drivers/net/pcs/Makefile | 1 +
> drivers/net/pcs/pcs-mtk-usxgmii.c | 413 ++++++++++++++++++
> include/linux/pcs/pcs-mtk-usxgmii.h | 26 ++
> 6 files changed, 456 insertions(+), 43 deletions(-)
> create mode 100644 drivers/net/pcs/pcs-mtk-usxgmii.c
> create mode 100644 include/linux/pcs/pcs-mtk-usxgmii.h

2023-12-06 13:38:23

[permalink] [raw]

Subject: Re: [RFC PATCH v2 5/8] net: pcs: add driver for MediaTek USXGMII PCS

On Wed, Dec 06, 2023 at 07:34:03AM -0600, Rob Herring wrote:
> On Wed, Dec 06, 2023 at 01:44:38AM +0000, Daniel Golle wrote:
> > Add driver for USXGMII PCS found in the MediaTek MT7988 SoC and supporting
> > USXGMII, 10GBase-R and 5GBase-R interface modes. In order to support
> > Cisco SGMII, 1000Base-X and 2500Base-X via the also present LynxI PCS
> > create a wrapped PCS taking care of the components shared between the
> > new USXGMII PCS and the legacy LynxI PCS.
> >
> > Signed-off-by: Daniel Golle <[email protected]>
> > ---
> > .../bindings/net/pcs/mediatek,usxgmii.yaml | 46 +-
>
> Why are you changing the binding you just added?

Oh, that change slipped into the wrong commit by accident, sorry about
that, I will fix it in the next iteration.

>
> In any case, bindings are separate patches.
>
> > MAINTAINERS | 2 +
> > drivers/net/pcs/Kconfig | 11 +
> > drivers/net/pcs/Makefile | 1 +
> > drivers/net/pcs/pcs-mtk-usxgmii.c | 413 ++++++++++++++++++
> > include/linux/pcs/pcs-mtk-usxgmii.h | 26 ++
> > 6 files changed, 456 insertions(+), 43 deletions(-)
> > create mode 100644 drivers/net/pcs/pcs-mtk-usxgmii.c
> > create mode 100644 include/linux/pcs/pcs-mtk-usxgmii.h

2023-12-06 13:38:51

[permalink] [raw]

Subject: Re: [RFC PATCH v2 7/8] dt-bindings: net: mediatek,net: fix and complete mt7988-eth binding

On Wed, Dec 06, 2023 at 01:45:02AM +0000, Daniel Golle wrote:
> Complete support for MT7988 which comes with 3 MACs, SRAM for DMA
> descriptors and uses a dedicated PCS for the SerDes units.
>
> Fixes: c94a9aabec36 ("dt-bindings: net: mediatek,net: add mt7988-eth binding")
> Signed-off-by: Daniel Golle <[email protected]>
> ---
> .../devicetree/bindings/net/mediatek,net.yaml | 148 +++++++++++++++++-
> 1 file changed, 146 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml
> index 030d106bc7d3f..ca0667c51c1c2 100644
> --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml
> +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml
> @@ -28,7 +28,10 @@ properties:
> - ralink,rt5350-eth
>
> reg:
> - maxItems: 1
> + minItems: 1
> + items:
> + - description: Base of registers used to program the ethernet controller
> + - description: SRAM region used for DMA descriptors

Is this a dedicated SRAM for this purpose, or a common one partitioned
up. mmio-sram and a phandle is how to do the latter.

>
> clocks: true
> clock-names: true
> @@ -115,6 +118,9 @@ allOf:
> - mediatek,mt7623-eth
> then:
> properties:
> + reg:
> + maxItems: 1
> +
> interrupts:
> maxItems: 3
>
> @@ -149,6 +155,9 @@ allOf:
> - mediatek,mt7621-eth
> then:
> properties:
> + reg:
> + maxItems: 1
> +
> interrupts:
> maxItems: 1
>
> @@ -174,6 +183,9 @@ allOf:
> const: mediatek,mt7622-eth
> then:
> properties:
> + reg:
> + maxItems: 1
> +
> interrupts:
> maxItems: 3
>
> @@ -215,6 +227,9 @@ allOf:
> const: mediatek,mt7629-eth
> then:
> properties:
> + reg:
> + maxItems: 1
> +
> interrupts:
> maxItems: 3
>
> @@ -257,6 +272,9 @@ allOf:
> const: mediatek,mt7981-eth
> then:
> properties:
> + reg:
> + maxItems: 1
> +
> interrupts:
> minItems: 4
>
> @@ -295,6 +313,9 @@ allOf:
> const: mediatek,mt7986-eth
> then:
> properties:
> + reg:
> + maxItems: 1
> +
> interrupts:
> minItems: 4
>
> @@ -333,8 +354,13 @@ allOf:
> const: mediatek,mt7988-eth
> then:
> properties:
> + reg:
> + maxItems: 2

Don't need maxItems here. That's already the max.

> + minItems: 2
> +
> interrupts:
> minItems: 4
> + maxItems: 4
>
> clocks:
> minItems: 24
> @@ -368,7 +394,7 @@ allOf:
> - const: top_netsys_warp_sel
>
> patternProperties:
> - "^mac@[0-1]$":
> + "^mac@[0-2]$":
> type: object
> unevaluatedProperties: false
> allOf:
> @@ -382,6 +408,9 @@ patternProperties:
> reg:
> maxItems: 1
>
> + phys:
> + maxItems: 1
> +
> required:
> - reg
> - compatible
> @@ -559,3 +588,118 @@ examples:
> };
> };
> };
> +
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/clock/mediatek,mt7988-clk.h>

Why is fixing the binding needing a new example? Is this example really
different enough to justify a whole other example?

> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + ethernet@15100000 {
> + compatible = "mediatek,mt7988-eth";
> + reg = <0 0x15100000 0 0x80000>, <0 0x15400000 0 0x380000>;
> + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
> + <&ethsys CLK_ETHDMA_XGP2_EN>,
> + <&ethsys CLK_ETHDMA_XGP3_EN>,
> + <&ethsys CLK_ETHDMA_FE_EN>,
> + <&ethsys CLK_ETHDMA_GP2_EN>,
> + <&ethsys CLK_ETHDMA_GP1_EN>,
> + <&ethsys CLK_ETHDMA_GP3_EN>,
> + <&ethsys CLK_ETHDMA_ESW_EN>,
> + <&ethsys CLK_ETHDMA_CRYPT0_EN>,
> + <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
> + <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
> + <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
> + <&topckgen CLK_TOP_ETH_GMII_SEL>,
> + <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
> + <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
> + <&topckgen CLK_TOP_ETH_SYS_SEL>,
> + <&topckgen CLK_TOP_ETH_XGMII_SEL>,
> + <&topckgen CLK_TOP_ETH_MII_SEL>,
> + <&topckgen CLK_TOP_NETSYS_SEL>,
> + <&topckgen CLK_TOP_NETSYS_500M_SEL>,
> + <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
> + <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
> + <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
> + <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
> +
> + clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
> + "gp3", "esw", "crypto",
> + "ethwarp_wocpu2", "ethwarp_wocpu1",
> + "ethwarp_wocpu0", "top_eth_gmii_sel",
> + "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
> + "top_eth_sys_sel", "top_eth_xgmii_sel",
> + "top_eth_mii_sel", "top_netsys_sel",
> + "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
> + "top_netsys_sync_250m_sel",
> + "top_netsys_ppefb_250m_sel",
> + "top_netsys_warp_sel";
> + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
> + <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
> + <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
> + <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
> + <&topckgen CLK_TOP_SGM_0_SEL>,
> + <&topckgen CLK_TOP_SGM_1_SEL>;
> + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
> + <&topckgen CLK_TOP_NET1PLL_D4>,
> + <&topckgen CLK_TOP_NET1PLL_D8_D4>,
> + <&topckgen CLK_TOP_NET1PLL_D8_D4>,
> + <&apmixedsys CLK_APMIXED_SGMPLL>,
> + <&apmixedsys CLK_APMIXED_SGMPLL>;
> + mediatek,ethsys = <&ethsys>;
> + mediatek,infracfg = <&topmisc>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mac@0 {
> + compatible = "mediatek,eth-mac";
> + reg = <0>;
> + phy-mode = "internal"; /* CPU port of built-in 1GE switch */
> +
> + fixed-link {
> + speed = <10000>;
> + full-duplex;
> + pause;
> + };
> + };
> +
> + mac@1 {
> + compatible = "mediatek,eth-mac";
> + reg = <1>;
> + phy-handle = <&int_2p5g_phy>;
> + };
> +
> + mac@2 {
> + compatible = "mediatek,eth-mac";
> + reg = <2>;
> + pcs-handle = <&usxgmiisys0>;
> + phy-handle = <&phy0>;
> + };
> +
> + mdio_bus: mdio-bus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* external PHY */
> + phy0: ethernet-phy@0 {
> + reg = <0>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> +
> + /* internal 2.5G PHY */
> + int_2p5g_phy: ethernet-phy@15 {
> + reg = <15>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + phy-mode = "internal";
> + };
> + };
> + };
> + };
> --
> 2.43.0

2023-12-06 16:09:30

[permalink] [raw]

Subject: Re: [RFC PATCH v2 7/8] dt-bindings: net: mediatek,net: fix and complete mt7988-eth binding

On Wed, Dec 06, 2023 at 07:38:16AM -0600, Rob Herring wrote:
> On Wed, Dec 06, 2023 at 01:45:02AM +0000, Daniel Golle wrote:
> > Complete support for MT7988 which comes with 3 MACs, SRAM for DMA
> > descriptors and uses a dedicated PCS for the SerDes units.
> >
> > Fixes: c94a9aabec36 ("dt-bindings: net: mediatek,net: add mt7988-eth binding")
> > Signed-off-by: Daniel Golle <[email protected]>
> > ---
> > .../devicetree/bindings/net/mediatek,net.yaml | 148 +++++++++++++++++-
> > 1 file changed, 146 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml
> > index 030d106bc7d3f..ca0667c51c1c2 100644
> > --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml
> > +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml
> > @@ -28,7 +28,10 @@ properties:
> > - ralink,rt5350-eth
> >
> > reg:
> > - maxItems: 1
> > + minItems: 1
> > + items:
> > + - description: Base of registers used to program the ethernet controller
> > + - description: SRAM region used for DMA descriptors
>
> Is this a dedicated SRAM for this purpose, or a common one partitioned
> up. mmio-sram and a phandle is how to do the latter.

The SRAM memory sits just next to the Ethernet and dedicated for this
purpose, at least in theory. I'm not aware of the internal details here.

>
> >
> > clocks: true
> > clock-names: true
> > @@ -115,6 +118,9 @@ allOf:
> > - mediatek,mt7623-eth
> > then:
> > properties:
> > + reg:
> > + maxItems: 1
> > +
> > interrupts:
> > maxItems: 3
> >
> > @@ -149,6 +155,9 @@ allOf:
> > - mediatek,mt7621-eth
> > then:
> > properties:
> > + reg:
> > + maxItems: 1
> > +
> > interrupts:
> > maxItems: 1
> >
> > @@ -174,6 +183,9 @@ allOf:
> > const: mediatek,mt7622-eth
> > then:
> > properties:
> > + reg:
> > + maxItems: 1
> > +
> > interrupts:
> > maxItems: 3
> >
> > @@ -215,6 +227,9 @@ allOf:
> > const: mediatek,mt7629-eth
> > then:
> > properties:
> > + reg:
> > + maxItems: 1
> > +
> > interrupts:
> > maxItems: 3
> >
> > @@ -257,6 +272,9 @@ allOf:
> > const: mediatek,mt7981-eth
> > then:
> > properties:
> > + reg:
> > + maxItems: 1
> > +
> > interrupts:
> > minItems: 4
> >
> > @@ -295,6 +313,9 @@ allOf:
> > const: mediatek,mt7986-eth
> > then:
> > properties:
> > + reg:
> > + maxItems: 1
> > +
> > interrupts:
> > minItems: 4
> >
> > @@ -333,8 +354,13 @@ allOf:
> > const: mediatek,mt7988-eth
> > then:
> > properties:
> > + reg:
> > + maxItems: 2
>
> Don't need maxItems here. That's already the max.

Ack.

>
> > + minItems: 2
> > +
> > interrupts:
> > minItems: 4
> > + maxItems: 4
> >
> > clocks:
> > minItems: 24
> > @@ -368,7 +394,7 @@ allOf:
> > - const: top_netsys_warp_sel
> >
> > patternProperties:
> > - "^mac@[0-1]$":
> > + "^mac@[0-2]$":
> > type: object
> > unevaluatedProperties: false
> > allOf:
> > @@ -382,6 +408,9 @@ patternProperties:
> > reg:
> > maxItems: 1
> >
> > + phys:
> > + maxItems: 1
> > +
> > required:
> > - reg
> > - compatible
> > @@ -559,3 +588,118 @@ examples:
> > };
> > };
> > };
> > +
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #include <dt-bindings/clock/mediatek,mt7988-clk.h>
>
>
> Why is fixing the binding needing a new example? Is this example really
> different enough to justify a whole other example?

Starting from MT7988 the PCS needs to be referenced as pcs-handle in the
MAC node, so that is a bit different. If you don't think that justifies
including the additional example I will drop that.

>
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + ethernet@15100000 {
> > + compatible = "mediatek,mt7988-eth";
> > + reg = <0 0x15100000 0 0x80000>, <0 0x15400000 0 0x380000>;
> > + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > + clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
> > + <&ethsys CLK_ETHDMA_XGP2_EN>,
> > + <&ethsys CLK_ETHDMA_XGP3_EN>,
> > + <&ethsys CLK_ETHDMA_FE_EN>,
> > + <&ethsys CLK_ETHDMA_GP2_EN>,
> > + <&ethsys CLK_ETHDMA_GP1_EN>,
> > + <&ethsys CLK_ETHDMA_GP3_EN>,
> > + <&ethsys CLK_ETHDMA_ESW_EN>,
> > + <&ethsys CLK_ETHDMA_CRYPT0_EN>,
> > + <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
> > + <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
> > + <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
> > + <&topckgen CLK_TOP_ETH_GMII_SEL>,
> > + <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
> > + <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
> > + <&topckgen CLK_TOP_ETH_SYS_SEL>,
> > + <&topckgen CLK_TOP_ETH_XGMII_SEL>,
> > + <&topckgen CLK_TOP_ETH_MII_SEL>,
> > + <&topckgen CLK_TOP_NETSYS_SEL>,
> > + <&topckgen CLK_TOP_NETSYS_500M_SEL>,
> > + <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
> > + <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
> > + <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
> > + <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
> > +
> > + clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
> > + "gp3", "esw", "crypto",
> > + "ethwarp_wocpu2", "ethwarp_wocpu1",
> > + "ethwarp_wocpu0", "top_eth_gmii_sel",
> > + "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
> > + "top_eth_sys_sel", "top_eth_xgmii_sel",
> > + "top_eth_mii_sel", "top_netsys_sel",
> > + "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
> > + "top_netsys_sync_250m_sel",
> > + "top_netsys_ppefb_250m_sel",
> > + "top_netsys_warp_sel";
> > + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
> > + <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
> > + <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
> > + <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
> > + <&topckgen CLK_TOP_SGM_0_SEL>,
> > + <&topckgen CLK_TOP_SGM_1_SEL>;
> > + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
> > + <&topckgen CLK_TOP_NET1PLL_D4>,
> > + <&topckgen CLK_TOP_NET1PLL_D8_D4>,
> > + <&topckgen CLK_TOP_NET1PLL_D8_D4>,
> > + <&apmixedsys CLK_APMIXED_SGMPLL>,
> > + <&apmixedsys CLK_APMIXED_SGMPLL>;
> > + mediatek,ethsys = <&ethsys>;
> > + mediatek,infracfg = <&topmisc>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + mac@0 {
> > + compatible = "mediatek,eth-mac";
> > + reg = <0>;
> > + phy-mode = "internal"; /* CPU port of built-in 1GE switch */
> > +
> > + fixed-link {
> > + speed = <10000>;
> > + full-duplex;
> > + pause;
> > + };
> > + };
> > +
> > + mac@1 {
> > + compatible = "mediatek,eth-mac";
> > + reg = <1>;
> > + phy-handle = <&int_2p5g_phy>;
> > + };
> > +
> > + mac@2 {
> > + compatible = "mediatek,eth-mac";
> > + reg = <2>;
> > + pcs-handle = <&usxgmiisys0>;
> > + phy-handle = <&phy0>;
> > + };
> > +
> > + mdio_bus: mdio-bus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + /* external PHY */
> > + phy0: ethernet-phy@0 {
> > + reg = <0>;
> > + compatible = "ethernet-phy-ieee802.3-c45";
> > + };
> > +
> > + /* internal 2.5G PHY */
> > + int_2p5g_phy: ethernet-phy@15 {
> > + reg = <15>;
> > + compatible = "ethernet-phy-ieee802.3-c45";
> > + phy-mode = "internal";
> > + };
> > + };
> > + };
> > + };
> > --
> > 2.43.0

2023-12-06 17:52:21

[permalink] [raw]

Subject: Re: [RFC PATCH v2 3/8] net: pcs: pcs-mtk-lynxi: add platform driver for MT7988

On Wed, Dec 06, 2023 at 01:44:17AM +0000, Daniel Golle wrote:
> +struct phylink_pcs *mtk_pcs_lynxi_select_pcs(struct device_node *np, phy_interface_t mode)
> +{
> + struct platform_device *pdev;
> + struct mtk_pcs_lynxi *mpcs;
> +
> + if (!np)
> + return NULL;
> +
> + if (!of_device_is_available(np))
> + return ERR_PTR(-ENODEV);
> +
> + if (!of_match_node(mtk_pcs_lynxi_of_match, np))
> + return ERR_PTR(-EINVAL);
> +
> + pdev = of_find_device_by_node(np);
> + if (!pdev || !platform_get_drvdata(pdev)) {
> + if (pdev)
> + put_device(&pdev->dev);
> + return ERR_PTR(-EPROBE_DEFER);
> + }
> +
> + mpcs = platform_get_drvdata(pdev);
> + put_device(&pdev->dev);
> +
> + return &mpcs->pcs;
> +}
> +EXPORT_SYMBOL(mtk_pcs_lynxi_select_pcs);

If you're going to play games like this, then you must mark the driver
with .suppress_bind_attrs = true to remove the bind/unbind attributes
in userspace that could wreak havoc with the above - because there is
_nothing_ that guarantees that the memory you're returning from this
function will remain intact. Basically, it's racy.

Also, I'm not sure I approve of using the "select_pcs" suffix (I
haven't spotted _where_ you use this, but returning EPROBE_DEFER to
phylink's mac_select_pcs() method doesn't do anything to defer any
probe, so that's an entirely misleading error code.

If we are going to have device drivers for PCS, then we need to
seriously think about how we look up PCS and return the phylink_pcs
pointer - and also how we handle the PCS device going away. None of
that should be coded into _any_ PCS driver.

--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

2023-12-06 17:56:57

[permalink] [raw]

Subject: Re: [RFC PATCH v2 5/8] net: pcs: add driver for MediaTek USXGMII PCS

On Wed, Dec 06, 2023 at 01:44:38AM +0000, Daniel Golle wrote:
> +struct phylink_pcs *mtk_usxgmii_select_pcs(struct device_node *np, phy_interface_t mode)
> +{
> + struct platform_device *pdev;
> + struct mtk_usxgmii_pcs *mpcs;
> +
> + if (!np)
> + return NULL;
> +
> + if (!of_device_is_available(np))
> + return ERR_PTR(-ENODEV);
> +
> + if (!of_match_node(mtk_usxgmii_of_mtable, np))
> + return ERR_PTR(-EINVAL);
> +
> + pdev = of_find_device_by_node(np);
> + if (!pdev || !platform_get_drvdata(pdev)) {
> + if (pdev)
> + put_device(&pdev->dev);
> + return ERR_PTR(-EPROBE_DEFER);
> + }
> +
> + mpcs = platform_get_drvdata(pdev);
> + put_device(&pdev->dev);
> +
> + return &mpcs->pcs;
> +}
> +EXPORT_SYMBOL(mtk_usxgmii_select_pcs);

All the same arguments apply here as per the lynxi driver.

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RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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2023-12-06 17:58:49

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Subject: Re: [RFC PATCH v2 5/8] net: pcs: add driver for MediaTek USXGMII PCS

On Wed, Dec 06, 2023 at 10:58:38AM +0100, Maxime Chevallier wrote:
> On Wed, 6 Dec 2023 01:44:38 +0000
> Daniel Golle <[email protected]> wrote:
> > + /* Read USXGMII link status */
> > + state->link = FIELD_GET(RG_PCS_RX_LINK_STATUS,
> > + mtk_r32(mpcs, RG_PCS_RX_STATUS0));
> > +
> > + /* Continuously repeat re-configuration sequence until link comes up */
> > + if (!state->link) {
> > + mtk_usxgmii_pcs_config(pcs, mpcs->neg_mode,
> > + state->interface, NULL, false);
> > + return;
>
> .pcs_get_state() isn't called only for link state polling,but also when querying
> the link state from ethtool, from phylink_ethtool_ksettings_get().
>
> As mtk_usxgmii_pcs_config triggers a pcs reset and reconfiguration, won't this disrupt
> the link ?

Highly likely if there's a race, but note that mtk_usxgmii_pcs_config()
only gets called if the link is *down*. I guess some IPs need a bit of
kicking to work properly.

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RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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2023-12-06 18:56:35

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Subject: Re: [RFC PATCH v2 8/8] net: ethernet: mtk_eth_soc: add paths and SerDes modes for MT7988

On Wed, Dec 06, 2023 at 01:45:17AM +0000, Daniel Golle wrote:
> @@ -516,6 +538,21 @@ static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
> struct mtk_eth *eth = mac->hw;
> unsigned int sid;
>
> + if (mtk_is_netsys_v3_or_greater(eth)) {
> + switch (interface) {
> + case PHY_INTERFACE_MODE_1000BASEX:
> + case PHY_INTERFACE_MODE_2500BASEX:
> + case PHY_INTERFACE_MODE_SGMII:
> + return mtk_pcs_lynxi_select_pcs(mac->sgmii_pcs_of_node, interface);
> + case PHY_INTERFACE_MODE_5GBASER:
> + case PHY_INTERFACE_MODE_10GBASER:
> + case PHY_INTERFACE_MODE_USXGMII:
> + return mtk_usxgmii_select_pcs(mac->usxgmii_pcs_of_node, interface);

From what I can see, neither of these two "select_pcs" methods that
you're calling makes any use of the "interface" you pass to them.
I'm not sure what they _could_ do with it either, given that what
you're effectively doing here is getting the phylink_pcs structure from
the driver, and each one only has a single phylink_pcs.

--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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2023-12-06 18:58:26

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Subject: Re: [RFC PATCH v2 5/8] net: pcs: add driver for MediaTek USXGMII PCS

On Wed, 6 Dec 2023 17:58:08 +0000
"Russell King (Oracle)" <[email protected]> wrote:

> On Wed, Dec 06, 2023 at 10:58:38AM +0100, Maxime Chevallier wrote:
> > On Wed, 6 Dec 2023 01:44:38 +0000
> > Daniel Golle <[email protected]> wrote:
> > > + /* Read USXGMII link status */
> > > + state->link = FIELD_GET(RG_PCS_RX_LINK_STATUS,
> > > + mtk_r32(mpcs, RG_PCS_RX_STATUS0));
> > > +
> > > + /* Continuously repeat re-configuration sequence until link comes up */
> > > + if (!state->link) {
> > > + mtk_usxgmii_pcs_config(pcs, mpcs->neg_mode,
> > > + state->interface, NULL, false);
> > > + return;
> >
> > .pcs_get_state() isn't called only for link state polling,but also when querying
> > the link state from ethtool, from phylink_ethtool_ksettings_get().
> >
> > As mtk_usxgmii_pcs_config triggers a pcs reset and reconfiguration, won't this disrupt
> > the link ?
>
> Highly likely if there's a race, but note that mtk_usxgmii_pcs_config()
> only gets called if the link is *down*. I guess some IPs need a bit of
> kicking to work properly.
>
Ah right that's true, it should be OK then.

Thanks,

Maxime

2023-12-06 19:53:03

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Subject: Re: [RFC PATCH v2 8/8] net: ethernet: mtk_eth_soc: add paths and SerDes modes for MT7988

On Wed, Dec 06, 2023 at 06:55:50PM +0000, Russell King (Oracle) wrote:
> On Wed, Dec 06, 2023 at 01:45:17AM +0000, Daniel Golle wrote:
> > @@ -516,6 +538,21 @@ static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
> > struct mtk_eth *eth = mac->hw;
> > unsigned int sid;
> >
> > + if (mtk_is_netsys_v3_or_greater(eth)) {
> > + switch (interface) {
> > + case PHY_INTERFACE_MODE_1000BASEX:
> > + case PHY_INTERFACE_MODE_2500BASEX:
> > + case PHY_INTERFACE_MODE_SGMII:
> > + return mtk_pcs_lynxi_select_pcs(mac->sgmii_pcs_of_node, interface);
> > + case PHY_INTERFACE_MODE_5GBASER:
> > + case PHY_INTERFACE_MODE_10GBASER:
> > + case PHY_INTERFACE_MODE_USXGMII:
> > + return mtk_usxgmii_select_pcs(mac->usxgmii_pcs_of_node, interface);
>
> From what I can see, neither of these two "select_pcs" methods that
> you're calling makes any use of the "interface" you pass to them.
> I'm not sure what they _could_ do with it either, given that what
> you're effectively doing here is getting the phylink_pcs structure from
> the driver, and each one only has a single phylink_pcs.

Yes, you are right, the interface parameter isn't used, I will drop
it from both mtk_*_select_pcs() prototypes.

In the long run we may want something like
struct phylink_pcs *of_pcs_get(struct device_node *np, phy_interface_t interface)
provided by a to-be-built drivers/net/pcs/core.c...

2023-12-06 20:23:47

[permalink] [raw]

Subject: Re: [RFC PATCH v2 8/8] net: ethernet: mtk_eth_soc: add paths and SerDes modes for MT7988

On Wed, Dec 06, 2023 at 07:52:23PM +0000, Daniel Golle wrote:
> On Wed, Dec 06, 2023 at 06:55:50PM +0000, Russell King (Oracle) wrote:
> > On Wed, Dec 06, 2023 at 01:45:17AM +0000, Daniel Golle wrote:
> > > @@ -516,6 +538,21 @@ static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
> > > struct mtk_eth *eth = mac->hw;
> > > unsigned int sid;
> > >
> > > + if (mtk_is_netsys_v3_or_greater(eth)) {
> > > + switch (interface) {
> > > + case PHY_INTERFACE_MODE_1000BASEX:
> > > + case PHY_INTERFACE_MODE_2500BASEX:
> > > + case PHY_INTERFACE_MODE_SGMII:
> > > + return mtk_pcs_lynxi_select_pcs(mac->sgmii_pcs_of_node, interface);
> > > + case PHY_INTERFACE_MODE_5GBASER:
> > > + case PHY_INTERFACE_MODE_10GBASER:
> > > + case PHY_INTERFACE_MODE_USXGMII:
> > > + return mtk_usxgmii_select_pcs(mac->usxgmii_pcs_of_node, interface);
> >
> > From what I can see, neither of these two "select_pcs" methods that
> > you're calling makes any use of the "interface" you pass to them.
> > I'm not sure what they _could_ do with it either, given that what
> > you're effectively doing here is getting the phylink_pcs structure from
> > the driver, and each one only has a single phylink_pcs.
>
> Yes, you are right, the interface parameter isn't used, I will drop
> it from both mtk_*_select_pcs() prototypes.
>
> In the long run we may want something like
> struct phylink_pcs *of_pcs_get(struct device_node *np, phy_interface_t interface)
> provided by a to-be-built drivers/net/pcs/core.c...

Again... it's not as simple as that. As soon as we get into the
situation that some _other_ driver becomes responsible for providing
the struct phylink_pcs pointer, we _then_ need to have some way of
dealing with that device going away.

By that I mean that the memory pointed to returned from such a function
that you are proposing above could be freed - or worse could be unmapped
from the kernel address space, and the same goes for the operations
structure as well - even more so if the "ops" are part of module data
and the module is unloaded.

As I know how these discussions go (it's not my first time bringing up
these kinds of multi-driver interations), no, locking the module into
memory doesn't work, and shows a lack of a full understanding of the
problem.

We need to have a way that when a PCS device is removed, that is
propagated up the management levels and causes the PCS to be gracefully
removed from the network driver (in other words, from phylink).

I won't accept a hack that sticky-plasters around the problem - not for
code that I am involved in actively maintaining - and sticky-plastering
around this class of problem seems to happen all too often in the
kernel.

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RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

2023-12-06 20:48:02

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Subject: Re: [RFC PATCH v2 8/8] net: ethernet: mtk_eth_soc: add paths and SerDes modes for MT7988

Hi Russell,

thank for going into my patch in depth and taking your time for an
elaborate and constructive answer.

On Wed, Dec 06, 2023 at 08:23:05PM +0000, Russell King (Oracle) wrote:
> On Wed, Dec 06, 2023 at 07:52:23PM +0000, Daniel Golle wrote:
> > On Wed, Dec 06, 2023 at 06:55:50PM +0000, Russell King (Oracle) wrote:
> > > On Wed, Dec 06, 2023 at 01:45:17AM +0000, Daniel Golle wrote:
> > > > @@ -516,6 +538,21 @@ static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
> > > > struct mtk_eth *eth = mac->hw;
> > > > unsigned int sid;
> > > >
> > > > + if (mtk_is_netsys_v3_or_greater(eth)) {
> > > > + switch (interface) {
> > > > + case PHY_INTERFACE_MODE_1000BASEX:
> > > > + case PHY_INTERFACE_MODE_2500BASEX:
> > > > + case PHY_INTERFACE_MODE_SGMII:
> > > > + return mtk_pcs_lynxi_select_pcs(mac->sgmii_pcs_of_node, interface);
> > > > + case PHY_INTERFACE_MODE_5GBASER:
> > > > + case PHY_INTERFACE_MODE_10GBASER:
> > > > + case PHY_INTERFACE_MODE_USXGMII:
> > > > + return mtk_usxgmii_select_pcs(mac->usxgmii_pcs_of_node, interface);
> > >
> > > From what I can see, neither of these two "select_pcs" methods that
> > > you're calling makes any use of the "interface" you pass to them.
> > > I'm not sure what they _could_ do with it either, given that what
> > > you're effectively doing here is getting the phylink_pcs structure from
> > > the driver, and each one only has a single phylink_pcs.
> >
> > Yes, you are right, the interface parameter isn't used, I will drop
> > it from both mtk_*_select_pcs() prototypes.
> >
> > In the long run we may want something like
> > struct phylink_pcs *of_pcs_get(struct device_node *np, phy_interface_t interface)
> > provided by a to-be-built drivers/net/pcs/core.c...
>
> Again... it's not as simple as that. As soon as we get into the
> situation that some _other_ driver becomes responsible for providing
> the struct phylink_pcs pointer, we _then_ need to have some way of
> dealing with that device going away.

I assume you are referring to struct phylink_pcs *of_pcs_get(...),
right? And true, it'd be quite a complex piece of infrastructure.

>
> By that I mean that the memory pointed to returned from such a function
> that you are proposing above could be freed - or worse could be unmapped
> from the kernel address space, and the same goes for the operations
> structure as well - even more so if the "ops" are part of module data
> and the module is unloaded.
>
> As I know how these discussions go (it's not my first time bringing up
> these kinds of multi-driver interations), no, locking the module into
> memory doesn't work, and shows a lack of a full understanding of the
> problem.
>
> We need to have a way that when a PCS device is removed, that is
> propagated up the management levels and causes the PCS to be gracefully
> removed from the network driver (in other words, from phylink).

I see -- spontanous removal of the PCS may not be a practical problem
on that very hardware, but from the driver model point of view, it is.

Should the callback for removal be implemented as part of the network
driver or are you suggesting to add such infrastructure to phylink?

>
> I won't accept a hack that sticky-plasters around the problem - not for
> code that I am involved in actively maintaining - and sticky-plastering
> around this class of problem seems to happen all too often in the
> kernel.

Oh yes, I can see that every day when testing various SFP modules with
exposed PHYs -- and often get stackdumps thrown at me when I remove
them...

2023-12-07 00:08:09