2016-11-28 13:55:15

by Zumeng Chen

Subject: [PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly

When a hardware issue happened as described by inline comments, the register
write pattern looks like the following:

<write ~MACB_BIT(RE)>
+ wmb();
<write MACB_BIT(RE)>

There might be a memory barrier between these two write operations, so add wmb
to ensure an flip from 0 to 1 for NCR.

Signed-off-by: Zumeng Chen <[email protected]>
---

V2 changes:

Add the same wmb for at91ether as well based on reviewer's suggestion.

Cheers,
drivers/net/ethernet/cadence/macb.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 533653b..6d7cfa7 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -1156,6 +1156,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
if (status & MACB_BIT(RXUBR)) {
ctrl = macb_readl(bp, NCR);
macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
+ wmb();
macb_writel(bp, NCR, ctrl | MACB_BIT(RE));

if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
@@ -2770,6 +2771,7 @@ static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
if (intstatus & MACB_BIT(RXUBR)) {
ctl = macb_readl(lp, NCR);
macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
+ wmb();
macb_writel(lp, NCR, ctl | MACB_BIT(RE));
}

--
2.4.11

2016-11-28 14:05:02

by Nicolas Ferre

Subject: Re: [PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly

Le 28/11/2016 ? 14:55, Zumeng Chen a ?crit :
> When a hardware issue happened as described by inline comments, the register
> write pattern looks like the following:
>
> <write ~MACB_BIT(RE)>
> + wmb();
> <write MACB_BIT(RE)>
>
> There might be a memory barrier between these two write operations, so add wmb
> to ensure an flip from 0 to 1 for NCR.
>
> Signed-off-by: Zumeng Chen <[email protected]>

Acked-by: Nicolas Ferre <[email protected]>

Thanks, best regards,

> ---
>
> V2 changes:
>
> Add the same wmb for at91ether as well based on reviewer's suggestion.
>
> Cheers,
> drivers/net/ethernet/cadence/macb.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
> index 533653b..6d7cfa7 100644
> --- a/drivers/net/ethernet/cadence/macb.c
> +++ b/drivers/net/ethernet/cadence/macb.c
> @@ -1156,6 +1156,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
> if (status & MACB_BIT(RXUBR)) {
> ctrl = macb_readl(bp, NCR);
> macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
> + wmb();
> macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
>
> if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
> @@ -2770,6 +2771,7 @@ static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
> if (intstatus & MACB_BIT(RXUBR)) {
> ctl = macb_readl(lp, NCR);
> macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
> + wmb();
> macb_writel(lp, NCR, ctl | MACB_BIT(RE));
> }
>
>


--
Nicolas Ferre

2016-11-30 01:34:22

by David Miller

Subject: Re: [PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly

From: Zumeng Chen <[email protected]>
Date: Mon, 28 Nov 2016 21:55:00 +0800

> When a hardware issue happened as described by inline comments, the register
> write pattern looks like the following:
>
> <write ~MACB_BIT(RE)>
> + wmb();
> <write MACB_BIT(RE)>
>
> There might be a memory barrier between these two write operations, so add wmb
> to ensure an flip from 0 to 1 for NCR.
>
> Signed-off-by: Zumeng Chen <[email protected]>
> ---
>
> V2 changes:
>
> Add the same wmb for at91ether as well based on reviewer's suggestion.

Applied, thanks.