Merge Qualcomm-specific idle-state binding with generic one.
Signed-off-by: David Heidelberg <[email protected]>
---
v4:
- drop Linux-specific details
- integrate compatible into existing block
- added surrounding patches fixing node names
v3:
- integrate into idle-state.yml
- original patch name was:
"[v2] dt-bindings: arm/msm/qcom,idle-state convert to YAML"
.../bindings/arm/msm/qcom,idle-state.txt | 84 -------------------
.../devicetree/bindings/cpu/idle-states.yaml | 80 +++++++++++++++++-
2 files changed, 76 insertions(+), 88 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
deleted file mode 100644
index 606b4b1b709d..000000000000
--- a/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
+++ /dev/null
@@ -1,84 +0,0 @@
-QCOM Idle States for cpuidle driver
-
-ARM provides idle-state node to define the cpuidle states, as defined in [1].
-cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
-states. Idle states have different enter/exit latency and residency values.
-The idle states supported by the QCOM SoC are defined as -
-
- * Standby
- * Retention
- * Standalone Power Collapse (Standalone PC or SPC)
- * Power Collapse (PC)
-
-Standby: Standby does a little more in addition to architectural clock gating.
-When the WFI instruction is executed the ARM core would gate its internal
-clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
-trigger to execute the SPM state machine. The SPM state machine waits for the
-interrupt to trigger the core back in to active. This triggers the cache
-hierarchy to enter standby states, when all cpus are idle. An interrupt brings
-the SPM state machine out of its wait, the next step is to ensure that the
-cache hierarchy is also out of standby, and then the cpu is allowed to resume
-execution. This state is defined as a generic ARM WFI state by the ARM cpuidle
-driver and is not defined in the DT. The SPM state machine should be
-configured to execute this state by default and after executing every other
-state below.
-
-Retention: Retention is a low power state where the core is clock gated and
-the memory and the registers associated with the core are retained. The
-voltage may be reduced to the minimum value needed to keep the processor
-registers active. The SPM should be configured to execute the retention
-sequence and would wait for interrupt, before restoring the cpu to execution
-state. Retention may have a slightly higher latency than Standby.
-
-Standalone PC: A cpu can power down and warmboot if there is a sufficient time
-between the time it enters idle and the next known wake up. SPC mode is used
-to indicate a core entering a power down state without consulting any other
-cpu or the system resources. This helps save power only on that core. The SPM
-sequence for this idle state is programmed to power down the supply to the
-core, wait for the interrupt, restore power to the core, and ensure the
-system state including cache hierarchy is ready before allowing core to
-resume. Applying power and resetting the core causes the core to warmboot
-back into Elevation Level (EL) which trampolines the control back to the
-kernel. Entering a power down state for the cpu, needs to be done by trapping
-into a EL. Failing to do so, would result in a crash enforced by the warm boot
-code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
-be flushed in s/w, before powering down the core.
-
-Power Collapse: This state is similar to the SPC mode, but distinguishes
-itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
-modes. In a hierarchical power domain SoC, this means L2 and other caches can
-be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
-voltages reduced, provided all cpus enter this state. Since the span of low
-power modes possible at this state is vast, the exit latency and the residency
-of this low power mode would be considered high even though at a cpu level,
-this essentially is cpu power down. The SPM in this state also may handshake
-with the Resource power manager (RPM) processor in the SoC to indicate a
-complete application processor subsystem shut down.
-
-The idle-state for QCOM SoCs are distinguished by the compatible property of
-the idle-states device node.
-
-The devicetree representation of the idle state should be -
-
-Required properties:
-
-- compatible: Must be one of -
- "qcom,idle-state-ret",
- "qcom,idle-state-spc",
- "qcom,idle-state-pc",
- and "arm,idle-state".
-
-Other required and optional properties are specified in [1].
-
-Example:
-
- idle-states {
- CPU_SPC: spc {
- compatible = "qcom,idle-state-spc", "arm,idle-state";
- entry-latency-us = <150>;
- exit-latency-us = <200>;
- min-residency-us = <2000>;
- };
- };
-
-[1]. Documentation/devicetree/bindings/cpu/idle-states.yaml
diff --git a/Documentation/devicetree/bindings/cpu/idle-states.yaml b/Documentation/devicetree/bindings/cpu/idle-states.yaml
index b3a5356f9916..15abc786a978 100644
--- a/Documentation/devicetree/bindings/cpu/idle-states.yaml
+++ b/Documentation/devicetree/bindings/cpu/idle-states.yaml
@@ -243,7 +243,64 @@ description: |+
just supports idle_standby, an idle-states node is not required.
===========================================
- 6 - References
+ 6 - Qualcomm specific STATES
+ ===========================================
+
+ Idle states have different enter/exit latency and residency values.
+ The idle states supported by the QCOM SoC are defined as -
+
+ * Standby
+ * Retention
+ * Standalone Power Collapse (Standalone PC or SPC)
+ * Power Collapse (PC)
+
+ Standby: Standby does a little more in addition to architectural clock gating.
+ When the WFI instruction is executed the ARM core would gate its internal
+ clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
+ trigger to execute the SPM state machine. The SPM state machine waits for the
+ interrupt to trigger the core back in to active. This triggers the cache
+ hierarchy to enter standby states, when all cpus are idle. An interrupt brings
+ the SPM state machine out of its wait, the next step is to ensure that the
+ cache hierarchy is also out of standby, and then the cpu is allowed to resume
+ execution. This state is defined as a generic ARM WFI state by the ARM cpuidle
+ driver and is not defined in the DT. The SPM state machine should be
+ configured to execute this state by default and after executing every other
+ state below.
+
+ Retention: Retention is a low power state where the core is clock gated and
+ the memory and the registers associated with the core are retained. The
+ voltage may be reduced to the minimum value needed to keep the processor
+ registers active. The SPM should be configured to execute the retention
+ sequence and would wait for interrupt, before restoring the cpu to execution
+ state. Retention may have a slightly higher latency than Standby.
+
+ Standalone PC: A cpu can power down and warmboot if there is a sufficient time
+ between the time it enters idle and the next known wake up. SPC mode is used
+ to indicate a core entering a power down state without consulting any other
+ cpu or the system resources. This helps save power only on that core. The SPM
+ sequence for this idle state is programmed to power down the supply to the
+ core, wait for the interrupt, restore power to the core, and ensure the
+ system state including cache hierarchy is ready before allowing core to
+ resume. Applying power and resetting the core causes the core to warmboot
+ back into Elevation Level (EL) which trampolines the control back to the
+ kernel. Entering a power down state for the cpu, needs to be done by trapping
+ into a EL. Failing to do so, would result in a crash enforced by the warm boot
+ code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
+ be flushed in s/w, before powering down the core.
+
+ Power Collapse: This state is similar to the SPC mode, but distinguishes
+ itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
+ modes. In a hierarchical power domain SoC, this means L2 and other caches can
+ be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
+ voltages reduced, provided all cpus enter this state. Since the span of low
+ power modes possible at this state is vast, the exit latency and the residency
+ of this low power mode would be considered high even though at a cpu level,
+ this essentially is cpu power down. The SPM in this state also may handshake
+ with the Resource power manager (RPM) processor in the SoC to indicate a
+ complete application processor subsystem shut down.
+
+ ===========================================
+ 7 - References
===========================================
[1] ARM Linux Kernel documentation - CPUs bindings
@@ -301,9 +358,15 @@ patternProperties:
properties:
compatible:
- enum:
- - arm,idle-state
- - riscv,idle-state
+ oneOf:
+ - const: arm,idle-state
+ - items:
+ - enum:
+ - qcom,idle-state-ret
+ - qcom,idle-state-spc
+ - qcom,idle-state-pc
+ - const: arm,idle-state
+ - const: riscv,idle-state
arm,psci-suspend-param:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -852,4 +915,13 @@ examples:
};
};
+ // Example 4 - Qualcomm SPC
+ idle-states {
+ cpu_spc: cpu-spc {
+ compatible = "qcom,idle-state-spc", "arm,idle-state";
+ entry-latency-us = <150>;
+ exit-latency-us = <200>;
+ min-residency-us = <2000>;
+ };
+ };
...
--
2.42.0
Required for dt-schema validation.
Signed-off-by: David Heidelberg <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 2 +-
arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 2 +-
arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
index 59fd86b9fb47..d2ae13a67382 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
@@ -87,7 +87,7 @@ L2: l2-cache {
};
idle-states {
- CPU_SPC: spc {
+ CPU_SPC: cpu-spc {
compatible = "qcom,idle-state-spc",
"arm,idle-state";
entry-latency-us = <400>;
diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
index 2b1f9d0fb510..bdf64895c55c 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
@@ -79,7 +79,7 @@ L2: l2-cache {
};
idle-states {
- CPU_SPC: spc {
+ CPU_SPC: cpu-spc {
compatible = "qcom,idle-state-spc",
"arm,idle-state";
entry-latency-us = <150>;
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
index 76006c3c4af2..e82b2d184735 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
@@ -85,7 +85,7 @@ L2: l2-cache {
};
idle-states {
- CPU_SPC: spc {
+ CPU_SPC: cpu-spc {
compatible = "qcom,idle-state-spc",
"arm,idle-state";
entry-latency-us = <150>;
--
2.42.0
compatible must be qcom,idle-state-spc AND arm,idle-state.
Fixes: d468f825b3fd ("ARM: dts: qcom: msm8916: Add include for SMP without PSCI on ARM32")
Signed-off-by: David Heidelberg <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi
index 36328dbe4212..1ba403b83cb1 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi
@@ -26,7 +26,7 @@ psci {
};
&CPU_SLEEP_0 {
- compatible = "qcom,idle-state-spc";
+ compatible = "qcom,idle-state-spc", "arm,idle-state";
};
&cpu0_acc {
--
2.42.0
On 3.12.2023 00:47, David Heidelberg wrote:
> Required for dt-schema validation.
>
> Signed-off-by: David Heidelberg <[email protected]>
> ---
Only patches 2 and 3 made it to my inbox and linux-arm-msm
Konrad
Hello Konrad,
v4 should be outside,
https://patchwork.kernel.org/project/linux-hwmon/patch/[email protected]/
Sadly, v3 probably got filtered by SPAM filter :(
David
On 04/12/2023 12:12, Konrad Dybcio wrote:
> On 3.12.2023 00:47, David Heidelberg wrote:
>> Required for dt-schema validation.
>>
>> Signed-off-by: David Heidelberg <[email protected]>
>> ---
> Only patches 2 and 3 made it to my inbox and linux-arm-msm
>
> Konrad
--
David Heidelberg
Ignore the link and v4, wrong patchset. At least linux-riscv accepted
the patch:
https://patchwork.kernel.org/project/linux-riscv/list/?series=806279&state=*&archive=both
David
On 09/12/2023 18:31, David Heidelberg wrote:
> Hello Konrad,
>
> v4 should be outside,
> https://patchwork.kernel.org/project/linux-hwmon/patch/[email protected]/
>
> Sadly, v3 probably got filtered by SPAM filter :(
>
> David
>
> On 04/12/2023 12:12, Konrad Dybcio wrote:
>> On 3.12.2023 00:47, David Heidelberg wrote:
>>> Required for dt-schema validation.
>>>
>>> Signed-off-by: David Heidelberg <[email protected]>
>>> ---
>> Only patches 2 and 3 made it to my inbox and linux-arm-msm
>>
>> Konrad
>
--
David Heidelberg
On Sun, 03 Dec 2023 00:47:17 +0100, David Heidelberg wrote:
> Merge Qualcomm-specific idle-state binding with generic one.
>
> Signed-off-by: David Heidelberg <[email protected]>
>
> ---
> v4:
> - drop Linux-specific details
> - integrate compatible into existing block
> - added surrounding patches fixing node names
> v3:
> - integrate into idle-state.yml
> - original patch name was:
> "[v2] dt-bindings: arm/msm/qcom,idle-state convert to YAML"
>
> .../bindings/arm/msm/qcom,idle-state.txt | 84 -------------------
> .../devicetree/bindings/cpu/idle-states.yaml | 80 +++++++++++++++++-
> 2 files changed, 76 insertions(+), 88 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
>
I kept the single entry compatibles as 1 enum and applied, thanks!
On Sun, 03 Dec 2023 00:47:17 +0100, David Heidelberg wrote:
> Merge Qualcomm-specific idle-state binding with generic one.
>
>
Applied, thanks!
[2/3] ARM: dts: qcom: include cpu in idle-state node names
commit: e48919dc1ed568f895eca090dc6c5dc56b12480c
[3/3] ARM: dts: qcom: msm8916: idle-state compatible require the generic idle-state
commit: 8f2cc88cd4a35e33931ca1375ea508c8c9267b57
Best regards,
--
Bjorn Andersson <[email protected]>