While trying to deal with errata i856 on the dra7xx I encountered some
obvious typos in the frequencies checked in timer.c, so those are being
fixed in case anyone ever tries to use one of them.
Also implement a fix for errata i856. Without the fix the time on the
system will get ahead by 43 seconds per day if SYSCLK1 is 20MHz, which it
is on the EVM boards as well as the other boards I am currently aware of.
ntp declares that the system time drifts by over 500ppm (the maximum
ntp will tolerate).
To fix it, check the status register to determine if the 32.768KHz clock
source is real (driven by an external crystal) or emulated (SYSCLK1 /
610), and if it is emulated use the appropriate numerator and divisor
to make the fine master counter match the coarse master counter (which
is driven directly from the 32KHz clock (real or emulated) with a fixed
multiplier of 375 / 2). Making the fine counter run at a frequency
different from the coarse counter is not an option, as the value in the
fine counter is updated to match the coarse counter if they ever get
out of sync.
With 19.2MHz installed on the board, the clock runs almost 5% slow.
With the change in place, ntp runs with a drift of around 3ppm on all
boards I have tried which is well within the spec of the crystals used
for SYSCLK1.
Even if the errata is fixed in future revisions of the chip, there is
still the option of someone purposely not connecting a 32.768KHz crystal
to save cost or board space, and relying on the emulated clock instead,
in which case this correction will still be necessary.
Len Sorensen (2):
ARM: omap5/dra7xx: Fix frequency typos.
ARM: dra7xx: Fix counter frequency drift for AM572x errata i856.
arch/arm/mach-omap2/control.h | 4 ++++
arch/arm/mach-omap2/timer.c | 44 +++++++++++++++++++++++++++++++++++------
2 files changed, 42 insertions(+), 6 deletions(-)
--
1.7.10.4
The switch statement of the possible list of SYSCLK1 frequencies is
missing a 0 in 4 out of the 7 frequencies.
Fixes: fa6d79d27614 ("ARM: OMAP: Add initialisation for the real-time
counter")
Signed-off-by: Len Sorensen <[email protected]>
Reviewed-by: Lokesh Vutla <[email protected]>
Acked-by: Nishanth Menon <[email protected]>
---
arch/arm/mach-omap2/timer.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 4f61148..fb0cb2b 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -513,11 +513,11 @@ static void __init realtime_counter_init(void)
rate = clk_get_rate(sys_clk);
/* Numerator/denumerator values refer TRM Realtime Counter section */
switch (rate) {
- case 1200000:
+ case 12000000:
num = 64;
den = 125;
break;
- case 1300000:
+ case 13000000:
num = 768;
den = 1625;
break;
@@ -529,11 +529,11 @@ static void __init realtime_counter_init(void)
num = 192;
den = 625;
break;
- case 2600000:
+ case 26000000:
num = 384;
den = 1625;
break;
- case 2700000:
+ case 27000000:
num = 256;
den = 1125;
break;
--
1.7.10.4
Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
crystal is not enabled at power up. Instead the CPU falls back to using
an emulation for the 32KHz clock which is SYSCLK1/610. SYSCLK1 is usually
20MHz on boards so far (which gives an emulated frequency of 32.786KHz),
but can also be 19.2 or 27MHz which result in much larger drift.
Since this is used to drive the master counter at 32.768KHz * 375 /
2 = 6.144MHz, the emulated speed for 20MHz is of by 570ppm, or about 43
seconds per day, and more than the 500ppm NTP is able to tolerate.
Checking the CTRL_CORE_BOOTSTRAP register can determine if the CPU
is using the real 32.768KHz crystal or the emulated SYSCLK1/610, and
by known that the real counter frequency can be determined and used.
The real speed is then SYSCLK1 / 610 * 375 / 2 or SYSCLK1 * 75 / 244.
Signed-off-by: Len Sorensen <[email protected]>
---
arch/arm/mach-omap2/control.h | 4 ++++
arch/arm/mach-omap2/timer.c | 36 ++++++++++++++++++++++++++++++++++--
2 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index a3c0133..a80ac2d 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -286,6 +286,10 @@
#define OMAP5XXX_CONTROL_STATUS 0x134
#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
+/* DRA7XX CONTROL CORE BOOTSTRAP */
+#define DRA7_CTRL_CORE_BOOTSTRAP 0x6c4
+#define DRA7_SPEEDSELECT_MASK (0x3 << 8)
+
/*
* REVISIT: This list of registers is not comprehensive - there are more
* that should be added.
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index fb0cb2b..7d45c84 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -54,6 +54,7 @@
#include "soc.h"
#include "common.h"
+#include "control.h"
#include "powerdomain.h"
#include "omap-secure.h"
@@ -496,7 +497,8 @@ static void __init realtime_counter_init(void)
void __iomem *base;
static struct clk *sys_clk;
unsigned long rate;
- unsigned int reg, num, den;
+ unsigned int reg;
+ unsigned long long num, den;
base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
if (!base) {
@@ -511,6 +513,35 @@ static void __init realtime_counter_init(void)
}
rate = clk_get_rate(sys_clk);
+
+ if (soc_is_dra7xx()) {
+ /*
+ * Errata i856 says the 32.768KHz crystal does not start at
+ * power on, so the CPU falls back to an emulated 32KHz clock
+ * based on sysclk / 610 instead. This causes the master counter
+ * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
+ * (OR sysclk * 75 / 244)
+ *
+ * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
+ * Of course any board built without a populated 32.768KHz
+ * crystal would also need this fix even if the CPU is fixed
+ * later.
+ *
+ * Either case can be detected by using the two speedselect bits
+ * If they are not 0, then the 32.768KHz clock driving the
+ * coarse counter that corrects the fine counter every time it
+ * ticks is actually rate/610 rather than 32.768KHz and we
+ * should compensate to avoid the 570ppm (at 20MHz, much worse
+ * at other rates) too fast system time.
+ */
+ reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
+ if (reg & DRA7_SPEEDSELECT_MASK) {
+ num = 75;
+ den = 244;
+ goto sysclk1_based;
+ }
+ }
+
/* Numerator/denumerator values refer TRM Realtime Counter section */
switch (rate) {
case 12000000:
@@ -545,6 +576,7 @@ static void __init realtime_counter_init(void)
break;
}
+sysclk1_based:
/* Program numerator and denumerator registers */
reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
NUMERATOR_DENUMERATOR_MASK;
@@ -556,7 +588,7 @@ static void __init realtime_counter_init(void)
reg |= den;
writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
- arch_timer_freq = (rate / den) * num;
+ arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
set_cntfreq();
iounmap(base);
--
1.7.10.4
Hi Len,
On Wednesday 17 December 2014 02:38 AM, Lennart Sorensen wrote:
> Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
> crystal is not enabled at power up. Instead the CPU falls back to using
> an emulation for the 32KHz clock which is SYSCLK1/610. SYSCLK1 is usually
> 20MHz on boards so far (which gives an emulated frequency of 32.786KHz),
> but can also be 19.2 or 27MHz which result in much larger drift.
>
> Since this is used to drive the master counter at 32.768KHz * 375 /
> 2 = 6.144MHz, the emulated speed for 20MHz is of by 570ppm, or about 43
> seconds per day, and more than the 500ppm NTP is able to tolerate.
>
> Checking the CTRL_CORE_BOOTSTRAP register can determine if the CPU
> is using the real 32.768KHz crystal or the emulated SYSCLK1/610, and
> by known that the real counter frequency can be determined and used.
> The real speed is then SYSCLK1 / 610 * 375 / 2 or SYSCLK1 * 75 / 244.
Looks good to me.
Tested this on DRA7 evm.
Tested-by: Lokesh Vutla <[email protected]>
Thanks and regards,
Lokesh
>
> Signed-off-by: Len Sorensen <[email protected]>
> ---
> arch/arm/mach-omap2/control.h | 4 ++++
> arch/arm/mach-omap2/timer.c | 36 ++++++++++++++++++++++++++++++++++--
> 2 files changed, 38 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
> index a3c0133..a80ac2d 100644
> --- a/arch/arm/mach-omap2/control.h
> +++ b/arch/arm/mach-omap2/control.h
> @@ -286,6 +286,10 @@
> #define OMAP5XXX_CONTROL_STATUS 0x134
> #define OMAP5_DEVICETYPE_MASK (0x7 << 6)
>
> +/* DRA7XX CONTROL CORE BOOTSTRAP */
> +#define DRA7_CTRL_CORE_BOOTSTRAP 0x6c4
> +#define DRA7_SPEEDSELECT_MASK (0x3 << 8)
> +
> /*
> * REVISIT: This list of registers is not comprehensive - there are more
> * that should be added.
> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> index fb0cb2b..7d45c84 100644
> --- a/arch/arm/mach-omap2/timer.c
> +++ b/arch/arm/mach-omap2/timer.c
> @@ -54,6 +54,7 @@
>
> #include "soc.h"
> #include "common.h"
> +#include "control.h"
> #include "powerdomain.h"
> #include "omap-secure.h"
>
> @@ -496,7 +497,8 @@ static void __init realtime_counter_init(void)
> void __iomem *base;
> static struct clk *sys_clk;
> unsigned long rate;
> - unsigned int reg, num, den;
> + unsigned int reg;
> + unsigned long long num, den;
>
> base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
> if (!base) {
> @@ -511,6 +513,35 @@ static void __init realtime_counter_init(void)
> }
>
> rate = clk_get_rate(sys_clk);
> +
> + if (soc_is_dra7xx()) {
> + /*
> + * Errata i856 says the 32.768KHz crystal does not start at
> + * power on, so the CPU falls back to an emulated 32KHz clock
> + * based on sysclk / 610 instead. This causes the master counter
> + * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
> + * (OR sysclk * 75 / 244)
> + *
> + * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
> + * Of course any board built without a populated 32.768KHz
> + * crystal would also need this fix even if the CPU is fixed
> + * later.
> + *
> + * Either case can be detected by using the two speedselect bits
> + * If they are not 0, then the 32.768KHz clock driving the
> + * coarse counter that corrects the fine counter every time it
> + * ticks is actually rate/610 rather than 32.768KHz and we
> + * should compensate to avoid the 570ppm (at 20MHz, much worse
> + * at other rates) too fast system time.
> + */
> + reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
> + if (reg & DRA7_SPEEDSELECT_MASK) {
> + num = 75;
> + den = 244;
> + goto sysclk1_based;
> + }
> + }
> +
> /* Numerator/denumerator values refer TRM Realtime Counter section */
> switch (rate) {
> case 12000000:
> @@ -545,6 +576,7 @@ static void __init realtime_counter_init(void)
> break;
> }
>
> +sysclk1_based:
> /* Program numerator and denumerator registers */
> reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
> NUMERATOR_DENUMERATOR_MASK;
> @@ -556,7 +588,7 @@ static void __init realtime_counter_init(void)
> reg |= den;
> writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
>
> - arch_timer_freq = (rate / den) * num;
> + arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
> set_cntfreq();
>
> iounmap(base);
>
On 14:06-20141217, Lokesh Vutla wrote:
> Hi Len,
> On Wednesday 17 December 2014 02:38 AM, Lennart Sorensen wrote:
> > Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
> > crystal is not enabled at power up. Instead the CPU falls back to using
> > an emulation for the 32KHz clock which is SYSCLK1/610. SYSCLK1 is usually
> > 20MHz on boards so far (which gives an emulated frequency of 32.786KHz),
> > but can also be 19.2 or 27MHz which result in much larger drift.
> >
> > Since this is used to drive the master counter at 32.768KHz * 375 /
> > 2 = 6.144MHz, the emulated speed for 20MHz is of by 570ppm, or about 43
> > seconds per day, and more than the 500ppm NTP is able to tolerate.
> >
> > Checking the CTRL_CORE_BOOTSTRAP register can determine if the CPU
> > is using the real 32.768KHz crystal or the emulated SYSCLK1/610, and
> > by known that the real counter frequency can be determined and used.
> > The real speed is then SYSCLK1 / 610 * 375 / 2 or SYSCLK1 * 75 / 244.
> Looks good to me.
> Tested this on DRA7 evm.
>
> Tested-by: Lokesh Vutla <[email protected]>
>
> Thanks and regards,
> Lokesh
>
> >
> > Signed-off-by: Len Sorensen <[email protected]>
> > ---
> > arch/arm/mach-omap2/control.h | 4 ++++
> > arch/arm/mach-omap2/timer.c | 36 ++++++++++++++++++++++++++++++++++--
> > 2 files changed, 38 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
> > index a3c0133..a80ac2d 100644
> > --- a/arch/arm/mach-omap2/control.h
> > +++ b/arch/arm/mach-omap2/control.h
> > @@ -286,6 +286,10 @@
> > #define OMAP5XXX_CONTROL_STATUS 0x134
> > #define OMAP5_DEVICETYPE_MASK (0x7 << 6)
> >
> > +/* DRA7XX CONTROL CORE BOOTSTRAP */
> > +#define DRA7_CTRL_CORE_BOOTSTRAP 0x6c4
> > +#define DRA7_SPEEDSELECT_MASK (0x3 << 8)
> > +
> > /*
> > * REVISIT: This list of registers is not comprehensive - there are more
> > * that should be added.
> > diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> > index fb0cb2b..7d45c84 100644
> > --- a/arch/arm/mach-omap2/timer.c
> > +++ b/arch/arm/mach-omap2/timer.c
> > @@ -54,6 +54,7 @@
> >
> > #include "soc.h"
> > #include "common.h"
> > +#include "control.h"
> > #include "powerdomain.h"
> > #include "omap-secure.h"
> >
> > @@ -496,7 +497,8 @@ static void __init realtime_counter_init(void)
> > void __iomem *base;
> > static struct clk *sys_clk;
> > unsigned long rate;
> > - unsigned int reg, num, den;
> > + unsigned int reg;
> > + unsigned long long num, den;
> >
> > base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
> > if (!base) {
> > @@ -511,6 +513,35 @@ static void __init realtime_counter_init(void)
> > }
> >
> > rate = clk_get_rate(sys_clk);
> > +
> > + if (soc_is_dra7xx()) {
> > + /*
> > + * Errata i856 says the 32.768KHz crystal does not start at
> > + * power on, so the CPU falls back to an emulated 32KHz clock
> > + * based on sysclk / 610 instead. This causes the master counter
> > + * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
> > + * (OR sysclk * 75 / 244)
> > + *
> > + * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
> > + * Of course any board built without a populated 32.768KHz
> > + * crystal would also need this fix even if the CPU is fixed
> > + * later.
> > + *
> > + * Either case can be detected by using the two speedselect bits
> > + * If they are not 0, then the 32.768KHz clock driving the
> > + * coarse counter that corrects the fine counter every time it
> > + * ticks is actually rate/610 rather than 32.768KHz and we
> > + * should compensate to avoid the 570ppm (at 20MHz, much worse
> > + * at other rates) too fast system time.
> > + */
> > + reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
> > + if (reg & DRA7_SPEEDSELECT_MASK) {
> > + num = 75;
> > + den = 244;
> > + goto sysclk1_based;
> > + }
> > + }
> > +
> > /* Numerator/denumerator values refer TRM Realtime Counter section */
> > switch (rate) {
> > case 12000000:
> > @@ -545,6 +576,7 @@ static void __init realtime_counter_init(void)
> > break;
> > }
> >
> > +sysclk1_based:
> > /* Program numerator and denumerator registers */
> > reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
> > NUMERATOR_DENUMERATOR_MASK;
> > @@ -556,7 +588,7 @@ static void __init realtime_counter_init(void)
> > reg |= den;
> > writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
> >
> > - arch_timer_freq = (rate / den) * num;
> > + arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
> > set_cntfreq();
> >
> > iounmap(base);
> >
>
If tony is ok with the arch_timer_freq change in this patch, I am ok
with it as well.
--
Regards,
Nishanth Menon