2023-08-07 19:43:27

by Bartosz Golaszewski

Subject: [PATCH 4/9] arm64: dts: qcom: sa8775p-ride: add pin functions for ethernet1

From: Bartosz Golaszewski <[email protected]>

Add the MDC and MDIO pin functions for ethernet1 on sa8775p-ride.

Signed-off-by: Bartosz Golaszewski <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
index 09ae6e153282..38327aff18b0 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
@@ -480,6 +480,22 @@ ethernet0_mdio: ethernet0-mdio-pins {
};
};

+ ethernet1_default: ethernet1-default-state {
+ ethernet1_mdc: ethernet1-mdc-pins {
+ pins = "gpio20";
+ function = "emac1_mdc";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ ethernet1_mdio: ethernet1-mdio-pins {
+ pins = "gpio21";
+ function = "emac1_mdio";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
qup_uart10_default: qup-uart10-state {
pins = "gpio46", "gpio47";
function = "qup1_se3";
--
2.39.2

2023-08-07 21:59:56

by Andrew Lunn

Subject: Re: [PATCH 4/9] arm64: dts: qcom: sa8775p-ride: add pin functions for ethernet1

On Mon, Aug 07, 2023 at 04:18:21PM -0500, Andrew Halaney wrote:
> On Mon, Aug 07, 2023 at 09:35:02PM +0200, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski <[email protected]>
> >
> > Add the MDC and MDIO pin functions for ethernet1 on sa8775p-ride.
> >
> > Signed-off-by: Bartosz Golaszewski <[email protected]>
> > ---
> > arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> > index 09ae6e153282..38327aff18b0 100644
> > --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> > +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> > @@ -480,6 +480,22 @@ ethernet0_mdio: ethernet0-mdio-pins {
> > };
> > };
> >
> > + ethernet1_default: ethernet1-default-state {
> > + ethernet1_mdc: ethernet1-mdc-pins {
> > + pins = "gpio20";
> > + function = "emac1_mdc";
> > + drive-strength = <16>;
> > + bias-pull-up;
> > + };
> > +
> > + ethernet1_mdio: ethernet1-mdio-pins {
> > + pins = "gpio21";
> > + function = "emac1_mdio";
> > + drive-strength = <16>;
> > + bias-pull-up;
> > + };
> > + };
> > +
>
> With the whole "EMAC0 MDIO handles the ethernet phy for EMAC1", this
> doesn't seem to make sense.
>
> I don't have all the schematics, but these pins are not connected from
> what I see.

I kind of agree. I've seen different ways of describing pinmux. What
i've done for Kirkwood was to put all the common pinmux configurations
into the SoC .dtsi file. The .dts file can then reference it if
needed.

In this case, since the bus is unused, it seems odd to mux it. And
later versions of the board could actually use the pins for something
else, GPIOs etc.

Andrew

2023-08-07 23:33:06

by Andrew Halaney

Subject: Re: [PATCH 4/9] arm64: dts: qcom: sa8775p-ride: add pin functions for ethernet1

On Mon, Aug 07, 2023 at 09:35:02PM +0200, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Add the MDC and MDIO pin functions for ethernet1 on sa8775p-ride.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> index 09ae6e153282..38327aff18b0 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> @@ -480,6 +480,22 @@ ethernet0_mdio: ethernet0-mdio-pins {
> };
> };
>
> + ethernet1_default: ethernet1-default-state {
> + ethernet1_mdc: ethernet1-mdc-pins {
> + pins = "gpio20";
> + function = "emac1_mdc";
> + drive-strength = <16>;
> + bias-pull-up;
> + };
> +
> + ethernet1_mdio: ethernet1-mdio-pins {
> + pins = "gpio21";
> + function = "emac1_mdio";
> + drive-strength = <16>;
> + bias-pull-up;
> + };
> + };
> +

With the whole "EMAC0 MDIO handles the ethernet phy for EMAC1", this
doesn't seem to make sense.

I don't have all the schematics, but these pins are not connected from
what I see.