2003-03-23 11:42:57
by Margit Schubert-While
According to the Intel docs, the cacheline for a P4 is 64 bytes. The P4 does, on read, 2 sectors of 64 bytes. But, on write, 64 bytes. So, is the cache line size wrong ? (7 in 2.4 and 2.5) Margit