The Pentium4 models 0&1 have a longer MSR_EBC_FREQUENCY_ID register as
the models 2&3, so the bit shift must be bigger.
Signed-off-by: Matthias-Christian Ott <[email protected]>
--- linux-bk/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c.orig
2005-01-21 13:55:37.000000000 +0100
+++ linux-bk/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c 2005-01-22
10:58:34.000000000 +0100
@@ -160,7 +160,14 @@
printk(KERN_DEBUG "speedstep-lib: couldn't detect FSB speed.
Please send an e-mail to <[email protected]>\n");
/* Multiplier. */
- mult = msr_lo >> 24;
+ if (c->x86_model < 2)
+ {
+ mult = msr_lo >> 27;
+ }
+ else
+ {
+ mult = msr_lo >> 24;
+ }
dprintk("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n", fsb,
mult, (fsb * mult));
On Sat, Jan 22, 2005 at 02:48:52PM +0100, Matthias-Christian Ott wrote:
> The Pentium4 models 0&1 have a longer MSR_EBC_FREQUENCY_ID register as
> the models 2&3, so the bit shift must be bigger.
I would feel safer if this checked that it was actually a p4 as well...
Arjan van de Ven wrote:
>On Sat, Jan 22, 2005 at 02:48:52PM +0100, Matthias-Christian Ott wrote:
>
>
>>The Pentium4 models 0&1 have a longer MSR_EBC_FREQUENCY_ID register as
>>the models 2&3, so the bit shift must be bigger.
>>
>>
>
>I would feel safer if this checked that it was actually a p4 as well...
>-
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Hi!
If mean my CPU, it's a pentium4 model 1 and the patch is checked with it.
All other tests which check if it's a pentium4 are performed by other
instances of the cpufreq driver.
Matthias-Christian Ott