in file: include/asm-arm/arch-ixp4x//system.h
function: arch_reset
code snap --
/* disable watchdog interrupt, enable reset, enable count */
*IXP4XX_OSWE = 0x3;
--
according to intel's documentation the appropriate bits are in the
following order:
bit 2: wdog_cnt_ena
bit 1: wdog_int_ena
bit 0: wdog_rst_ena
so the above assigned value should be 101b == 0x5.
I do not know why 0x3 works at all. Btw, u-boot assigns 0x5.
This is for all kernels I had a chance to look at (2.4.20-2.6.10).
__
Thanks,
Ara
On Thu, Jan 27, 2005 at 06:40:17PM +0400, Ara Avanesyan wrote:
> in file: include/asm-arm/arch-ixp4x//system.h
> function: arch_reset
>
> code snap --
> /* disable watchdog interrupt, enable reset, enable count */
> *IXP4XX_OSWE = 0x3;
> --
>
> according to intel's documentation the appropriate bits are in the
> following order:
> bit 2: wdog_cnt_ena
> bit 1: wdog_int_ena
> bit 0: wdog_rst_ena
>
> so the above assigned value should be 101b == 0x5.
> I do not know why 0x3 works at all. Btw, u-boot assigns 0x5.
>
> This is for all kernels I had a chance to look at (2.4.20-2.6.10).
Best place to air this is [email protected]
where all ARM kernel related discussions go on.
--
Ben ([email protected], http://www.fluff.org/)
'a smiley only costs 4 bytes'
Ara Avanesyan wrote:
> in file: include/asm-arm/arch-ixp4x//system.h
> function: arch_reset
>
> code snap --
> /* disable watchdog interrupt, enable reset, enable count */
> *IXP4XX_OSWE = 0x3;
> --
See:
http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=2437
> I do not know why 0x3 works at all. Btw, u-boot assigns 0x5.
The count enable bit is irrelevant as the counter is initialized to
zero.
David Vrabel
--
David Vrabel, Design Engineer
Arcom, Clifton Road Tel: +44 (0)1223 411200 ext. 3233
Cambridge CB1 7EA, UK Web: http://www.arcom.com/