Current KVM does not expect L1 hypervisor to allow L2 guest to access
APIC page directly when APICv is enabled. When this happens, KVM
emulates the access itself resulting in interrupt lost.
As this kind of hypervisor is rare, it is simpler to inhibit APICv upon
detecting direct APIC access from L2 to avoid unexpected interrupt lost.
Signed-off-by: Ake Koomsin <[email protected]>
---
arch/x86/include/asm/kvm_host.h | 6 ++++++
arch/x86/kvm/mmu/mmu.c | 33 ++++++++++++++++++++++++++-------
arch/x86/kvm/svm/svm.h | 3 ++-
arch/x86/kvm/vmx/vmx.c | 3 ++-
4 files changed, 36 insertions(+), 9 deletions(-)
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 3bc146dfd38d..8764b11922a0 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -1188,6 +1188,12 @@ enum kvm_apicv_inhibit {
APICV_INHIBIT_REASON_APIC_ID_MODIFIED,
APICV_INHIBIT_REASON_APIC_BASE_MODIFIED,
+ /*
+ * APICv is disabled because L1 hypervisor allows L2 guest to access
+ * APIC directly.
+ */
+ APICV_INHIBIT_REASON_L2_PASSTHROUGH_ACCESS,
+
/******************************************************/
/* INHIBITs that are relevant only to the AMD's AVIC. */
/******************************************************/
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index ec169f5c7dce..c1150ef9fce1 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -4293,6 +4293,30 @@ void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true, NULL);
}
+static int __kvm_faultin_pfn_guest_mode(struct kvm_vcpu *vcpu,
+ struct kvm_page_fault *fault)
+{
+ struct kvm_memory_slot *slot = fault->slot;
+
+ /* Don't expose private memslots to L2. */
+ fault->slot = NULL;
+ fault->pfn = KVM_PFN_NOSLOT;
+ fault->map_writable = false;
+
+ /*
+ * APICv does not work when L1 hypervisor allows L2 guest to access
+ * APIC directly. As this kind of L1 hypervisor is rare, it is simpler
+ * to inhibit APICv when we detect direct APIC access from L2, and
+ * fallback to emulation path to avoid interrupt lost.
+ */
+ if (unlikely(slot && slot->id == APIC_ACCESS_PAGE_PRIVATE_MEMSLOT &&
+ kvm_apicv_activated(vcpu->kvm)))
+ kvm_set_apicv_inhibit(vcpu->kvm,
+ APICV_INHIBIT_REASON_L2_PASSTHROUGH_ACCESS);
+
+ return RET_PF_CONTINUE;
+}
+
static int __kvm_faultin_pfn(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
{
struct kvm_memory_slot *slot = fault->slot;
@@ -4307,13 +4331,8 @@ static int __kvm_faultin_pfn(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault
return RET_PF_RETRY;
if (!kvm_is_visible_memslot(slot)) {
- /* Don't expose private memslots to L2. */
- if (is_guest_mode(vcpu)) {
- fault->slot = NULL;
- fault->pfn = KVM_PFN_NOSLOT;
- fault->map_writable = false;
- return RET_PF_CONTINUE;
- }
+ if (is_guest_mode(vcpu))
+ return __kvm_faultin_pfn_guest_mode(vcpu, fault);
/*
* If the APIC access page exists but is disabled, go directly
* to emulation without caching the MMIO access or creating a
diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h
index 18af7e712a5a..8d77932ee0fb 100644
--- a/arch/x86/kvm/svm/svm.h
+++ b/arch/x86/kvm/svm/svm.h
@@ -683,7 +683,8 @@ extern struct kvm_x86_nested_ops svm_nested_ops;
BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED) | \
BIT(APICV_INHIBIT_REASON_APIC_ID_MODIFIED) | \
BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED) | \
- BIT(APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED) \
+ BIT(APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED) | \
+ BIT(APICV_INHIBIT_REASON_L2_PASSTHROUGH_ACCESS) \
)
bool avic_hardware_setup(void);
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index df461f387e20..f652397c9765 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -8189,7 +8189,8 @@ static void vmx_hardware_unsetup(void)
BIT(APICV_INHIBIT_REASON_BLOCKIRQ) | \
BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED) | \
BIT(APICV_INHIBIT_REASON_APIC_ID_MODIFIED) | \
- BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED) \
+ BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED) | \
+ BIT(APICV_INHIBIT_REASON_L2_PASSTHROUGH_ACCESS) \
)
static void vmx_vm_destroy(struct kvm *kvm)
--
2.41.0
У пн, 2023-08-07 у 15:26 +0900, Ake Koomsin пише:
> Current KVM does not expect L1 hypervisor to allow L2 guest to access
> APIC page directly when APICv is enabled. When this happens, KVM
> emulates the access itself resulting in interrupt lost.
>
> As this kind of hypervisor is rare, it is simpler to inhibit APICv upon
> detecting direct APIC access from L2 to avoid unexpected interrupt lost.
>
> Signed-off-by: Ake Koomsin <[email protected]>
> ---
> arch/x86/include/asm/kvm_host.h | 6 ++++++
> arch/x86/kvm/mmu/mmu.c | 33 ++++++++++++++++++++++++++-------
> arch/x86/kvm/svm/svm.h | 3 ++-
> arch/x86/kvm/vmx/vmx.c | 3 ++-
> 4 files changed, 36 insertions(+), 9 deletions(-)
>
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index 3bc146dfd38d..8764b11922a0 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -1188,6 +1188,12 @@ enum kvm_apicv_inhibit {
> APICV_INHIBIT_REASON_APIC_ID_MODIFIED,
> APICV_INHIBIT_REASON_APIC_BASE_MODIFIED,
>
> + /*
> + * APICv is disabled because L1 hypervisor allows L2 guest to access
> + * APIC directly.
> + */
> + APICV_INHIBIT_REASON_L2_PASSTHROUGH_ACCESS,
> +
> /******************************************************/
> /* INHIBITs that are relevant only to the AMD's AVIC. */
> /******************************************************/
> diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
> index ec169f5c7dce..c1150ef9fce1 100644
> --- a/arch/x86/kvm/mmu/mmu.c
> +++ b/arch/x86/kvm/mmu/mmu.c
> @@ -4293,6 +4293,30 @@ void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
> kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true, NULL);
> }
>
> +static int __kvm_faultin_pfn_guest_mode(struct kvm_vcpu *vcpu,
> + struct kvm_page_fault *fault)
> +{
> + struct kvm_memory_slot *slot = fault->slot;
> +
> + /* Don't expose private memslots to L2. */
> + fault->slot = NULL;
> + fault->pfn = KVM_PFN_NOSLOT;
> + fault->map_writable = false;
> +
> + /*
> + * APICv does not work when L1 hypervisor allows L2 guest to access
> + * APIC directly. As this kind of L1 hypervisor is rare, it is simpler
> + * to inhibit APICv when we detect direct APIC access from L2, and
> + * fallback to emulation path to avoid interrupt lost.
> + */
> + if (unlikely(slot && slot->id == APIC_ACCESS_PAGE_PRIVATE_MEMSLOT &&
> + kvm_apicv_activated(vcpu->kvm)))
> + kvm_set_apicv_inhibit(vcpu->kvm,
> + APICV_INHIBIT_REASON_L2_PASSTHROUGH_ACCESS);
Is there a good reason why KVM doesn't expose APIC memslot to a nested guest?
While nested guest runs, the L1's APICv is "inhibited" effectively anyway, so writes to this memslot
should update APIC registers and be picked up by APICv hardware when L1 resumes execution.
Since APICv alows itself to be inhibited due to other reasons, it means that just like AVIC, it should be able
to pick up arbitrary changes to APIC registers which happened while it was inhibited,
just like AVIC does.
I'll take a look at the code to see if APICv does this (I know AVIC's code much better that APICv's)
Is there a reproducer for this bug?
Best regards,
Maxim Levitsky
> +
> + return RET_PF_CONTINUE;
> +}
> +
> static int __kvm_faultin_pfn(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
> {
> struct kvm_memory_slot *slot = fault->slot;
> @@ -4307,13 +4331,8 @@ static int __kvm_faultin_pfn(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault
> return RET_PF_RETRY;
>
> if (!kvm_is_visible_memslot(slot)) {
> - /* Don't expose private memslots to L2. */
> - if (is_guest_mode(vcpu)) {
> - fault->slot = NULL;
> - fault->pfn = KVM_PFN_NOSLOT;
> - fault->map_writable = false;
> - return RET_PF_CONTINUE;
> - }
> + if (is_guest_mode(vcpu))
> + return __kvm_faultin_pfn_guest_mode(vcpu, fault);
> /*
> * If the APIC access page exists but is disabled, go directly
> * to emulation without caching the MMIO access or creating a
> diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h
> index 18af7e712a5a..8d77932ee0fb 100644
> --- a/arch/x86/kvm/svm/svm.h
> +++ b/arch/x86/kvm/svm/svm.h
> @@ -683,7 +683,8 @@ extern struct kvm_x86_nested_ops svm_nested_ops;
> BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED) | \
> BIT(APICV_INHIBIT_REASON_APIC_ID_MODIFIED) | \
> BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED) | \
> - BIT(APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED) \
> + BIT(APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED) | \
> + BIT(APICV_INHIBIT_REASON_L2_PASSTHROUGH_ACCESS) \
> )
>
> bool avic_hardware_setup(void);
> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> index df461f387e20..f652397c9765 100644
> --- a/arch/x86/kvm/vmx/vmx.c
> +++ b/arch/x86/kvm/vmx/vmx.c
> @@ -8189,7 +8189,8 @@ static void vmx_hardware_unsetup(void)
> BIT(APICV_INHIBIT_REASON_BLOCKIRQ) | \
> BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED) | \
> BIT(APICV_INHIBIT_REASON_APIC_ID_MODIFIED) | \
> - BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED) \
> + BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED) | \
> + BIT(APICV_INHIBIT_REASON_L2_PASSTHROUGH_ACCESS) \
> )
>
> static void vmx_vm_destroy(struct kvm *kvm)
On Mon, Aug 07, 2023, Maxim Levitsky wrote:
> У пн, 2023-08-07 у 15:26 +0900, Ake Koomsin пише:
> > Current KVM does not expect L1 hypervisor to allow L2 guest to access
> > APIC page directly when APICv is enabled. When this happens, KVM
> > emulates the access itself resulting in interrupt lost.
Kinda stating the obvious, but as Maxim alluded to, emulating an APIC access while
APICv is active should not result in lost interrupts. I.e. suppressing APICv is
likely masking a bug that isn't unique to this specific scenario.
> Is there a good reason why KVM doesn't expose APIC memslot to a nested guest?
AFAIK, simply because no one has ever requested that KVM support such a use case.
> While nested guest runs, the L1's APICv is "inhibited" effectively anyway, so
> writes to this memslot should update APIC registers and be picked up by APICv
> hardware when L1 resumes execution.
>
> Since APICv alows itself to be inhibited due to other reasons, it means that
> just like AVIC, it should be able to pick up arbitrary changes to APIC
> registers which happened while it was inhibited, just like AVIC does.
>
> I'll take a look at the code to see if APICv does this (I know AVIC's code
> much better that APICv's)
>
> Is there a reproducer for this bug?
+1, this needs a reproducer, or at the very least a very detailed explanation
and analysis.
On Mon, 07 Aug 2023 17:00:58 +0300
Maxim Levitsky <[email protected]> wrote:
> Is there a good reason why KVM doesn't expose APIC memslot to a
> nested guest? While nested guest runs, the L1's APICv is "inhibited"
> effectively anyway, so writes to this memslot should update APIC
> registers and be picked up by APICv hardware when L1 resumes
> execution.
>
> Since APICv alows itself to be inhibited due to other reasons, it
> means that just like AVIC, it should be able to pick up arbitrary
> changes to APIC registers which happened while it was inhibited, just
> like AVIC does.
>
> I'll take a look at the code to see if APICv does this (I know AVIC's
> code much better that APICv's)
>
> Is there a reproducer for this bug?
>
> Best regards,
> Maxim Levitsky
From reading old commits (3a2936dedd20 and 1313cc2bd8f6), I interprete that
current KVM implementation does not expect direct APIC access from L2 guests.
I assume that there might be some challenging implementation issues.
To reproduce the problem, we need to run a micro hypervisor named BitVisor on
KVM. This hypervisor, when running on real machine, lets its guest access
physical APIC directly. As BitVisor intends to run on real machine, when running
under KVM, it conceals all KVM related features reported through CPUID. The L2
guest will initialize and run as if it runs on a physical machine. We also need
an Intel machine that support APICv. (I test on Intel 13th machine. The problem
should also be reproducible on Intel 12th machine). Current BitVisor's SVM
implementations always monitor MMIO access so we cannot reproduce the problem.
BitVisor VMX implementation under UEFI environment by default hooks the APIC
access during initialization. The purpose of this APIC access hook is to
bootstrap AP processors during UEFI ExitBootServices. When booting a guest OS,
the firmware sends INIT signal during ExitBootServices. BitVisor then bootstrap
AP processors, put them to guest mode, and unhook APIC access. After this,
the guest can now access APIC memory directly.
As far as I understand the KVM implemntation, when BitVisor still hooks APIC
access, EPT_VIOLATION occurs when L2 guest accesses APIC page. The EPT_VIOLATION
is then forwarded to BitVisor. BitVisor eventually accesses APIC on behalf of
the L2 guest. In this case, APICv works properly because the access is from L1.
After BitVisor unhooks the APIC page, the first access to APIC from the L2 guest
goes to EPT_VIOLATION handling path. This handling path marks the APIC page with
a reserved flag, and causes the access to retry eventually. Subsequent accesses
are then handled in EPT_MISCONFIG path, emulating the MMIO access. Interrupt
seems to disappear after this.
Here is the steps to reproduce the problem.
1) hg clone http://hg.code.sf.net/p/bitvisor/code bitvisor-code
2) Enter the cloned directory and type 'make' (No need to worry about warnings
at the moment. The default configuration is good enough to reproduce the
problem). We now have bitvisor.elf after the compilation.
3) Enter boot/uefi-boot, and type 'make' to compile the UEFI bootloader. We
need mingw for this. We now have loadvmm.efi after the compilation.
4) Put bitvisor.elf and loadvmm.efi to together in a folder. The folder
is going to look like the following:
~/x86_test
├── bitvisor.elf
└── loadvmm.efi
5) Run the following qemu command. Replace UEFI firmware path and other
parameters as you prefer. Make sure -smp 2 is there. Otherwise, there will be
no INIT signal during UEFI ExitBootServices. (I use QEMU 8.0.3)
qemu-system-x86_64 -cpu host -enable-kvm -bios /usr/share/edk2-ovmf/OVMF_CODE.fd \
-drive file=fat:rw:~/x86_test/,format=raw \
-cdrom ~/Downloads/Fedora-Workstation-Live-x86_64-38-1.6.iso \
-M q35 -m 8192 -smp 2 -serial stdio
6) During the launch, enter the bios config by hitting esc key repeatedly.
Then, select 'Boot Manager' and choose 'EFI Internel Shell' to enter the
UEFI shell.
7) The directory we specify in the command should be at fs0. Type 'fs0:' in
the shell.
8) Type 'loadvmm.efi' to load BitVisor. We should see the following message
Loading ...............................................................
Starting BitVisor...
Copyright (c) 2007, 2008 University of Tsukuba
All rights reserved.
ACPI DMAR not found.
FACS address 0x7FBDD000
Module not found.
Processor 0 (BSP)
ooooooooooooooooooooooooooooooooooooooooooooooooooo
...
MCFG [0] 0000:00-FF (B0000000,10000000)
Starting a virtual machine.
9) We should now return to the shell. Right now we are running as a L2 guest.
10) Next is to boot Linux from the live cd or your prefered method. We can see
the panic related to "panic - not syncing: IO-APIC + timer doesn't work!".
The panic can be reproduced quite easy. Even though, it happens to pass to
timer check, or you specify 'no_timer_check' boot parameter, it will stall
during SMP bringup.
The idea from step 6 to step 10 is to start BitVisor first, and start Linux on
top of it. You can adjust the step as you like. Feel free to ask me anything
regarding reproducing the problem with BitVisor if the giving steps are not
sufficient.
The problem does not happen when enable_apicv=N. Note that SMP bringup with
enable_apicv=N can fail. This is another problem. We don't have to worry about
this for now. Linux seems to have no delay between INIT DEASSERT and SIPI during
its SMP bringup. This can easily makes INIT and SIPI pending together resultling
in signal lost.
I admit that my knowledge on KVM and APICv is very limited. I may misunderstand
the problem. If you don't mind, would it be possible for you to guide me which
code path should I pay attention to? I would love to learn to find out the
actual cause of the problem.
Best Regards
Ake Koomsin
On Tue, Aug 08, 2023, Ake Koomsin wrote:
> On Mon, 07 Aug 2023 17:00:58 +0300
> Maxim Levitsky <[email protected]> wrote:
>
> > Is there a good reason why KVM doesn't expose APIC memslot to a
> > nested guest? While nested guest runs, the L1's APICv is "inhibited"
> > effectively anyway, so writes to this memslot should update APIC
> > registers and be picked up by APICv hardware when L1 resumes
> > execution.
> >
> > Since APICv alows itself to be inhibited due to other reasons, it
> > means that just like AVIC, it should be able to pick up arbitrary
> > changes to APIC registers which happened while it was inhibited, just
> > like AVIC does.
> >
> > I'll take a look at the code to see if APICv does this (I know AVIC's
> > code much better that APICv's)
> >
> > Is there a reproducer for this bug?
>
> The idea from step 6 to step 10 is to start BitVisor first, and start Linux on
> top of it. You can adjust the step as you like. Feel free to ask me anything
> regarding reproducing the problem with BitVisor if the giving steps are not
> sufficient.
Thank you for the detailed repro steps! However, it's likely going to be O(weeks)
before anyone is able to look at this in detail given the extensive repro steps.
If you have bandwidth, it's probably worth trying to reproduce the problem in a
KVM selftest (or a KVM-Unit-Test), e.g. create a nested VM, send an IPI from L2,
and see if it gets routed correctly. This purely a suggestion to try and get a
faster fix, it's by no means necessary.
Actually, typing that out raises a question (or two). What APICv VMCS control
settings does BitVisor use? E.g. is BitVisor enabling APICv for its VM (L2)?
If so, what values for the APIC access page and vAPIC page are shoved into
BitVisor's VMCS?
> The problem does not happen when enable_apicv=N. Note that SMP bringup with
> enable_apicv=N can fail. This is another problem. We don't have to worry about
> this for now. Linux seems to have no delay between INIT DEASSERT and SIPI during
> its SMP bringup. This can easily makes INIT and SIPI pending together resultling
> in signal lost.
>
> I admit that my knowledge on KVM and APICv is very limited. I may misunderstand
> the problem. If you don't mind, would it be possible for you to guide me which
> code path should I pay attention to? I would love to learn to find out the
> actual cause of the problem.
KVM *should* emulate the APIC MMIO access from L2. The call stack should reach
apic_mmio_write(), and assuming it's an ICR write, KVM should send an IPI.
On Tue, 8 Aug 2023 16:48:19 -0700
Sean Christopherson <[email protected]> wrote:
> > The idea from step 6 to step 10 is to start BitVisor first, and
> > start Linux on top of it. You can adjust the step as you like. Feel
> > free to ask me anything regarding reproducing the problem with
> > BitVisor if the giving steps are not sufficient.
>
> Thank you for the detailed repro steps! However, it's likely going
> to be O(weeks) before anyone is able to look at this in detail given
> the extensive repro steps. If you have bandwidth, it's probably worth
> trying to reproduce the problem in a KVM selftest (or a
> KVM-Unit-Test), e.g. create a nested VM, send an IPI from L2, and see
> if it gets routed correctly. This purely a suggestion to try and get
> a faster fix, it's by no means necessary.
>
> Actually, typing that out raises a question (or two). What APICv
> VMCS control settings does BitVisor use? E.g. is BitVisor enabling
> APICv for its VM (L2)? If so, what values for the APIC access page
> and vAPIC page are shoved into BitVisor's VMCS?
BitVisor does not set up APICv at all. It also does not setup APIC
access page at all. It does not try to emulate APIC at all. It only
monitors for APIC INIT event through EPT_VIOLATION mechanism only for
its AP bringup and stop monitoring after that. As I mentioned in the
previous mail, when BitVisor runs on real hardware, it lets the guest
control real APIC directly.
As it is a micro hypervisor, it runs only one guest OS. Its main focus
is on device access monitoring/manipulation depending on the
configuration. It tries to avoid anything to do with interrupts as
much as possible.
In mean time, I will try to get deeper into KVM internal. Thank you
very much suggesting on KVM-Unit-Test.
> > The problem does not happen when enable_apicv=N. Note that SMP
> > bringup with enable_apicv=N can fail. This is another problem. We
> > don't have to worry about this for now. Linux seems to have no
> > delay between INIT DEASSERT and SIPI during its SMP bringup. This
> > can easily makes INIT and SIPI pending together resultling in
> > signal lost.
> >
> > I admit that my knowledge on KVM and APICv is very limited. I may
> > misunderstand the problem. If you don't mind, would it be possible
> > for you to guide me which code path should I pay attention to? I
> > would love to learn to find out the actual cause of the problem.
>
> KVM *should* emulate the APIC MMIO access from L2. The call stack
> should reach apic_mmio_write(), and assuming it's an ICR write, KVM
> should send an IPI.
When enable_apicv=N, interrupts work properly. This is why I wrote this
RFC patch.
Regarding SMP bringup fail, The thing is when L2 Linux guest runs on top
of L1 BitVisor, it is not going to rely on KVM specific features at all.
In this case, it seems to me that vcpus possibly can not change their
state to wait-for-sipi in time once INIT is issued (might be due to
scheduling?). This does not happen when BitVisor runs on real hardware.
Once you have time to try BitVisor, please let me know if you can
reproduce the problem with the default configuration. Trying with
-smp 8+ on a machine with many cores might be easy to reproduce the
problem. I test mine on i5-13600K.