Hi!
Does anybody have a strong opinion against adding support for
i386 Page Attribute Tables?
The main benefit would be that one can have write-combining memory
regions without setting up MTRRs. This will come in handy for a
device we're working with where the device driver needs to allocate the
display memory directly from system memory, and it may be difficult to fit
the mtrr alignment constraints.
Outline:
The PAT may be set up at boot time with fixed backwards-compatible
memory types for the different PAT entries + defines like the following:
#define _PAGE_PAT_WB xxx
#define _PAGE_PAT_WT xxx
#define _PAGE_PAT_UC0 xxx
#define _PAGE_PAT_UC1 xxx
#define _PAGE_PAT_WC xxx
which can be used in parallel with the old _PAGE_PWT and _PAGE_PCD bits.
The idea is that new memory types, WC for example, will use the pat entries
7 downto 4, whereas 0-3 are left to boot setting to maintain backwards
compatibility.
Issues:
1) The _PAGE_BIT_PAT will be the same as _PAGE_PSE, and _PAGE_PROTNONE.
As I understand it, _PAGE_PROTNONE is not used when the page is present,
so this might not be an issue.
What about _PAGE_PSE?
2) The PATs need to be setup for each processor just after system boot.
Where is the best place to do this?
/Thomas Hellstr?m
Thomas Hellstr?m wrote:
> Hi!
>
> Does anybody have a strong opinion against adding support for
> i386 Page Attribute Tables?
>
> The main benefit would be that one can have write-combining memory
> regions without setting up MTRRs. This will come in handy for a
> device we're working with where the device driver needs to allocate the
> display memory directly from system memory, and it may be difficult to
> fit
> the mtrr alignment constraints.
An additional benefit if that you can easily run out of mtrrs. My home
machine boots with all 8 mtrrs used, leaving none for the G965
graphics. I have to compress two mtrrs into one in order to get decent
performance.
>
> Outline:
> The PAT may be set up at boot time with fixed backwards-compatible
> memory types for the different PAT entries + defines like the following:
>
> #define _PAGE_PAT_WB xxx
> #define _PAGE_PAT_WT xxx
> #define _PAGE_PAT_UC0 xxx
> #define _PAGE_PAT_UC1 xxx
> #define _PAGE_PAT_WC xxx
>
> which can be used in parallel with the old _PAGE_PWT and _PAGE_PCD bits.
>
> The idea is that new memory types, WC for example, will use the pat
> entries
> 7 downto 4, whereas 0-3 are left to boot setting to maintain backwards
> compatibility.
>
> Issues:
> 1) The _PAGE_BIT_PAT will be the same as _PAGE_PSE, and _PAGE_PROTNONE.
> As I understand it, _PAGE_PROTNONE is not used when the page is
> present, so this might not be an issue.
> What about _PAGE_PSE?
pse pages place the pat bit in bit 12, you will need to account for that.
--
Do not meddle in the internals of kernels, for they are subtle and quick to panic.
On Sat, 27 Jan 2007 10:20:18 +0100, Thomas Hellstr?m wrote:
> Does anybody have a strong opinion against adding support for
> i386 Page Attribute Tables?
...
> Issues:
> 1) The _PAGE_BIT_PAT will be the same as _PAGE_PSE, and _PAGE_PROTNONE.
> As I understand it, _PAGE_PROTNONE is not used when the page is present,
> so this might not be an issue.
> What about _PAGE_PSE?
>
> 2) The PATs need to be setup for each processor just after system boot.
> Where is the best place to do this?
3) Many Intel processors, including at least most P6s and probably
also some P4s, have an erratum which effectively halves the number
of available PAT entries, forcing an OS to make the low 4 and upper
4 PAT entries identical.
I don't know if 4 PAT types suffice for the kinds of uses people
have in mind. But support for PAT would either have to restrict
itself to only 4 PAT types, or ensure that it is only enabled on
new enough processors where it actually works.
You will need to read all available Intel errata sheets (spec updates)
to determine which processors are affected and which are OK.
/Mikael
Mikael Pettersson wrote:
>
> 3) Many Intel processors, including at least most P6s and probably
> also some P4s, have an erratum which effectively halves the number
> of available PAT entries, forcing an OS to make the low 4 and upper
> 4 PAT entries identical.
>
> I don't know if 4 PAT types suffice for the kinds of uses people
> have in mind. But support for PAT would either have to restrict
> itself to only 4 PAT types, or ensure that it is only enabled on
> new enough processors where it actually works.
>
> You will need to read all available Intel errata sheets (spec updates)
> to determine which processors are affected and which are OK.
>
There aren't really that many useful caching types, so it probably
doesn't matter all that much.
The types that matters most are WB, WC, and UC. The fourth one could be
WT, or it could be UC- (however, UC- can *always* be emulated by simply
having the kernel being aware of the MTRR settings.)
-hpa
On Sat, Jan 27, 2007 at 10:20:18AM +0100, Thomas Hellstr?m wrote:
> Hi!
>
> Does anybody have a strong opinion against adding support for
> i386 Page Attribute Tables?
It pops up about once a year, everyone agrees it'd be a good idea,
and then nothing happens. Last year, I started picking over
Terrence Ripperda's original implementation, but that needs a bit
of work. (http://lkml.org/lkml/2005/5/12/187)
Whoa, two years even. Time flies.
Dave
--
http://www.codemonkey.org.uk
Dave Jones wrote:
> On Sat, Jan 27, 2007 at 10:20:18AM +0100, Thomas Hellstr?m wrote:
> > Hi!
> >
> > Does anybody have a strong opinion against adding support for
> > i386 Page Attribute Tables?
>
> It pops up about once a year, everyone agrees it'd be a good idea,
> and then nothing happens. Last year, I started picking over
> Terrence Ripperda's original implementation, but that needs a bit
> of work. (http://lkml.org/lkml/2005/5/12/187)
> Whoa, two years even. Time flies.
>
> Dave
>
>
Ah.
This might explain why nothing happens :).
I had something much simpler in mind.
Just the basic PAT setup and some new pgprot_ types which affected
drivers could use directly.
Like in(drivers/char/drm/drm_vm.c) where ia64 has a
pgprot_writecombine() function.
/Thomas