Hi,
I've been googeling for about an hour now and can't find an answer to:
What type of CPU should I select when compiling a recent 2.6 kernel if I
have a VIA Esther CPU?
Please CC me, I'm not on the list.
Thanks & Regards,
Mark.
~$ cat /proc/cpuinfo
processor : 0
vendor_id : CentaurHauls
cpu family : 6
model : 10
model name : VIA Esther processor 1200MHz
stepping : 9
cpu MHz : 1200.189
cache size : 128 KB
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce apic sep mtrr pge cmov
pat clflush acpi mmx fxsr sse sse2 tm nx up pni est tm2 rng rng_en ace
ace_en
bogomips : 2407.15
On Mon, Feb 12, 2007 at 06:37:38PM +0100, Mark de Vries wrote:
> I've been googeling for about an hour now and can't find an answer to:
> What type of CPU should I select when compiling a recent 2.6 kernel if I
> have a VIA Esther CPU?
> stepping : 9
config MVIAC3_2
bool "VIA C3-2 (Nehemiah)"
help
Select this for a VIA C3 "Nehemiah". Selecting this enables usage
of SSE and tells gcc to treat the CPU as a 686.
Note, this kernel will not boot on older (pre model 9) C3s.
Is the one you want, I believe.
Cheers,
Kyle
On Mon, Feb 12, 2007 at 02:14:41PM -0500, Kyle McMartin wrote:
> On Mon, Feb 12, 2007 at 06:37:38PM +0100, Mark de Vries wrote:
> > I've been googeling for about an hour now and can't find an answer to:
> > What type of CPU should I select when compiling a recent 2.6 kernel if I
> > have a VIA Esther CPU?
>
> > stepping : 9
>
> config MVIAC3_2
> bool "VIA C3-2 (Nehemiah)"
> help
> Select this for a VIA C3 "Nehemiah". Selecting this enables usage
> of SSE and tells gcc to treat the CPU as a 686.
> Note, this kernel will not boot on older (pre model 9) C3s.
>
> Is the one you want, I believe.
The C7 doesn't seem to care much which you optimise it for.
Any of the 686 options should work just fine, but MVIAC3_2 is no
worse than any of the others.
Dave
--
http://www.codemonkey.org.uk
On 12/02/07 20:16, Dave Jones wrote:
> On Mon, Feb 12, 2007 at 02:14:41PM -0500, Kyle McMartin wrote:
> > On Mon, Feb 12, 2007 at 06:37:38PM +0100, Mark de Vries wrote:
> > > I've been googeling for about an hour now and can't find an answer to:
> > > What type of CPU should I select when compiling a recent 2.6 kernel if I
> > > have a VIA Esther CPU?
> >
> > > stepping : 9
> >
> > config MVIAC3_2
> > bool "VIA C3-2 (Nehemiah)"
> > help
> > Select this for a VIA C3 "Nehemiah". Selecting this enables usage
> > of SSE and tells gcc to treat the CPU as a 686.
> > Note, this kernel will not boot on older (pre model 9) C3s.
> >
> > Is the one you want, I believe.
>
> The C7 doesn't seem to care much which you optimise it for.
> Any of the 686 options should work just fine, but MVIAC3_2 is no
> worse than any of the others.
>
MVIAC3_2 doesn't enable X86_GOOD_APIC, try M686 (Pentium-Pro) - but that won't enable MMX and SSE (via -march=c3-2).
These CPUs support SSE2 too... there should probably be an option for C7 that passes 686/mmx/sse/sse2 to gcc. (The c3-2 option could even cause gcc to alter code for the C3-2 that's not necessary for the C7, but I've not checked what else gcc does with -march=c3-2).
Also, for the C7 you'll want CRYPTO_DEV_PADLOCK_* (Hardware Crypto Devices, Support for VIA PadLock ACE) and HW_RANDOM_VIA (VIA HW Random Number Generator support).
--
Simon Arlott
On Mon, Feb 12, 2007 at 11:46:46PM +0000, Simon Arlott wrote:
> MVIAC3_2 doesn't enable X86_GOOD_APIC
which is pretty irrelevant unless you have a dual C7.
> , try M686 (Pentium-Pro) - but that won't enable MMX and SSE (via -march=c3-2).
If gcc generated SSE/MMX instructions that would be a bug. (hint: it doesn't).
> These CPUs support SSE2 too...
The SSE/SSE2/SSE3 etc support for userspace is unconditional. The context switch paths will
save/restore the registers regardless of the CPU you've compiled your kernel for.
The only SSE code in the kernel is the memcpy code (which wasn't that big a win when
I last tried it on VIA due to their poor memory bandwidth), and the RAID code, which
gets tested at runtime rather than compile time.
> Also, for the C7 you'll want CRYPTO_DEV_PADLOCK_* (Hardware Crypto Devices, Support for VIA PadLock ACE) and HW_RANDOM_VIA (VIA HW Random Number Generator support).
Yes. But these aren't dependant on any CPU config options.
Dave
--
http://www.codemonkey.org.uk