This series adds various devices (NAND, USB, tsens, L2CC, RPM) which
have either recently gained mainline drivers, or just failed to be
previously added, to the DTS for the IPQ806x platform. It then enables
them for the MikroTik RB3011 platform, where they have all been tested.
I've done the additions to the main IPQ806x DTS as separate commits for
each logical set, and then a single wholesale set of changes for the
RB3011 to turn everything on. Happy to squash to 1/2 commits or split
out further if desired.
Jonathan McDowell (5):
ARM: dts: qcom: Add ADM DMA + NAND definitions to ipq806x
ARM: dts: qcom: Add tsens details to ipq806x
ARM: dts: qcom: Add USB port definitions to ipq806x
ARM: dts: qcom: add L2CC and RPM for IPQ8064
ARM: dts: qcom: Enable NAND + USB for RB3011
arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 58 +++
arch/arm/boot/dts/qcom-ipq8064.dtsi | 427 +++++++++++++++++++++-
2 files changed, 484 insertions(+), 1 deletion(-)
--
2.20.1
This adds the L2CC IPC resource and RPM devices to the IPQ8064 device
tree.
Tested on a Mikrotik RB3011.
Signed-off-by: Jonathan McDowell <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index afa11acfb378..e4e3dc59c650 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -2,6 +2,8 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mfd/qcom-rpm.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
#include <dt-bindings/gpio/gpio.h>
@@ -753,11 +755,38 @@
};
};
+ rpm: rpm@108000 {
+ compatible = "qcom,rpm-ipq8064";
+ reg = <0x108000 0x1000>;
+ qcom,ipc = <&l2cc 0x8 2>;
+
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ack", "err", "wakeup";
+
+ clocks = <&gcc RPM_MSG_RAM_H_CLK>;
+ clock-names = "ram";
+
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
+ #clock-cells = <1>;
+ };
+ };
+
tcsr: syscon@1a400000 {
compatible = "qcom,tcsr-ipq8064", "syscon";
reg = <0x1a400000 0x100>;
};
+ l2cc: clock-controller@2011000 {
+ compatible = "qcom,kpss-gcc", "syscon";
+ reg = <0x2011000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu_l2_aux";
+ };
+
lcc: clock-controller@28000000 {
compatible = "qcom,lcc-ipq8064";
reg = <0x28000000 0x1000>;
--
2.20.1
Enable the NAND + USB devices for the MikroTik RB3011 platform now
they're in the main IPQ806x DT.
Signed-off-by: Jonathan McDowell <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 58 +++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
index 282b89ce3d45..f7ea2e5dd191 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
@@ -216,6 +216,10 @@
};
};
+&adm_dma {
+ status = "okay";
+};
+
&gmac0 {
status = "okay";
@@ -251,6 +255,39 @@
status = "okay";
};
+&hs_phy_1 {
+ status = "okay";
+};
+
+&nand {
+ status = "okay";
+
+ nandcs@0 {
+ compatible = "qcom,nandcs";
+ reg = <0>;
+
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot@0 {
+ label = "RouterBoard NAND 1 Boot";
+ reg = <0x0000000 0x0800000>;
+ };
+
+ main@800000 {
+ label = "RouterBoard NAND 1 Main";
+ reg = <0x0800000 0x7800000>;
+ };
+ };
+ };
+};
+
&qcom_pinmux {
buttons_pins: buttons_pins {
mux {
@@ -305,4 +342,25 @@
input-disable;
};
};
+
+ usb1_pwr_en_pins: usb1_pwr_en_pins {
+ mux {
+ pins = "gpio4";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&ss_phy_1 {
+ status = "okay";
+};
+
+&usb3_1 {
+ pinctrl-0 = <&usb1_pwr_en_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
};
--
2.20.1
This series adds various devices (NAND, USB, tsens, L2CC, RPM) which
have either recently gained mainline drivers, or just failed to be
previously added, to the DTS for the IPQ806x platform. It then enables
them for the MikroTik RB3011 platform, where they have all been tested.
I've done the additions to the main IPQ806x DTS as separate commits for
each logical set, and then a single wholesale set of changes for the
RB3011 to turn everything on. Happy to squash to 1/2 commits or split
out further if desired.
v2:
Fix ADM label to "dma-controller"
Drop spurious "syscon" on GCC for tsens changes
Jonathan McDowell (5):
ARM: dts: qcom: Add ADM DMA + NAND definitions to ipq806x
ARM: dts: qcom: Add tsens details to ipq806x
ARM: dts: qcom: Add USB port definitions to ipq806x
ARM: dts: qcom: add L2CC and RPM for IPQ8064
ARM: dts: qcom: Enable NAND + USB for RB3011
arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 58 +++
arch/arm/boot/dts/qcom-ipq8064.dtsi | 425 ++++++++++++++++++++++
2 files changed, 483 insertions(+)
--
2.20.1
Enable the NAND + USB devices for the MikroTik RB3011 platform now
they're in the main IPQ806x DT.
Signed-off-by: Jonathan McDowell <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 58 +++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
index 282b89ce3d45..f7ea2e5dd191 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
@@ -216,6 +216,10 @@
};
};
+&adm_dma {
+ status = "okay";
+};
+
&gmac0 {
status = "okay";
@@ -251,6 +255,39 @@
status = "okay";
};
+&hs_phy_1 {
+ status = "okay";
+};
+
+&nand {
+ status = "okay";
+
+ nandcs@0 {
+ compatible = "qcom,nandcs";
+ reg = <0>;
+
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot@0 {
+ label = "RouterBoard NAND 1 Boot";
+ reg = <0x0000000 0x0800000>;
+ };
+
+ main@800000 {
+ label = "RouterBoard NAND 1 Main";
+ reg = <0x0800000 0x7800000>;
+ };
+ };
+ };
+};
+
&qcom_pinmux {
buttons_pins: buttons_pins {
mux {
@@ -305,4 +342,25 @@
input-disable;
};
};
+
+ usb1_pwr_en_pins: usb1_pwr_en_pins {
+ mux {
+ pins = "gpio4";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&ss_phy_1 {
+ status = "okay";
+};
+
+&usb3_1 {
+ pinctrl-0 = <&usb1_pwr_en_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
};
--
2.20.1
Signed-off-by: Jonathan McDowell <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 88 +++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 9628092217cb..c66859abdfd5 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -1026,6 +1026,94 @@
status = "disabled";
};
+ hs_phy_0: hs_phy_0 {
+ compatible = "qcom,ipq806x-usb-phy-hs";
+ reg = <0x100f8800 0x30>;
+ clocks = <&gcc USB30_0_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ ss_phy_0: ss_phy_0 {
+ compatible = "qcom,ipq806x-usb-phy-ss";
+ reg = <0x100f8830 0x30>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb3_0: usb3@100f8800 {
+ compatible = "qcom,dwc3", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x100f8800 0x8000>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "core";
+
+ ranges;
+
+ resets = <&gcc USB30_0_MASTER_RESET>;
+ reset-names = "master";
+
+ status = "disabled";
+
+ dwc3_0: dwc3@10000000 {
+ compatible = "snps,dwc3";
+ reg = <0x10000000 0xcd00>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&hs_phy_0>, <&ss_phy_0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
+ hs_phy_1: hs_phy_1 {
+ compatible = "qcom,ipq806x-usb-phy-hs";
+ reg = <0x110f8800 0x30>;
+ clocks = <&gcc USB30_1_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+ };
+
+ ss_phy_1: ss_phy_1 {
+ compatible = "qcom,ipq806x-usb-phy-ss";
+ reg = <0x110f8830 0x30>;
+ clocks = <&gcc USB30_1_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+ };
+
+ usb3_1: usb3@110f8800 {
+ compatible = "qcom,dwc3", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x110f8800 0x8000>;
+ clocks = <&gcc USB30_1_MASTER_CLK>;
+ clock-names = "core";
+
+ ranges;
+
+ resets = <&gcc USB30_1_MASTER_RESET>;
+ reset-names = "master";
+
+ status = "disabled";
+
+ dwc3_1: dwc3@11000000 {
+ compatible = "snps,dwc3";
+ reg = <0x11000000 0xcd00>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&hs_phy_1>, <&ss_phy_1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
--
2.20.1
This adds the L2CC IPC resource and RPM devices to the IPQ8064 device
tree.
Tested on a Mikrotik RB3011.
Signed-off-by: Jonathan McDowell <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index c66859abdfd5..1851a95f8663 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -2,6 +2,8 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mfd/qcom-rpm.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
#include <dt-bindings/gpio/gpio.h>
@@ -753,11 +755,38 @@
};
};
+ rpm: rpm@108000 {
+ compatible = "qcom,rpm-ipq8064";
+ reg = <0x108000 0x1000>;
+ qcom,ipc = <&l2cc 0x8 2>;
+
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ack", "err", "wakeup";
+
+ clocks = <&gcc RPM_MSG_RAM_H_CLK>;
+ clock-names = "ram";
+
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
+ #clock-cells = <1>;
+ };
+ };
+
tcsr: syscon@1a400000 {
compatible = "qcom,tcsr-ipq8064", "syscon";
reg = <0x1a400000 0x100>;
};
+ l2cc: clock-controller@2011000 {
+ compatible = "qcom,kpss-gcc", "syscon";
+ reg = <0x2011000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu_l2_aux";
+ };
+
lcc: clock-controller@28000000 {
compatible = "qcom,lcc-ipq8064";
reg = <0x28000000 0x1000>;
--
2.20.1
On Thu 20 May 12:30 CDT 2021, Jonathan McDowell wrote:
> Signed-off-by: Jonathan McDowell <[email protected]>
> ---
> arch/arm/boot/dts/qcom-ipq8064.dtsi | 88 +++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> index 9628092217cb..c66859abdfd5 100644
> --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> @@ -1026,6 +1026,94 @@
> status = "disabled";
> };
>
> + hs_phy_0: hs_phy_0 {
The node name should be some generic-thing@unit-address, so I fixed up
all your phys as "phy@100f8800" while applying your patches.
Thank you,
Bjorn
> + compatible = "qcom,ipq806x-usb-phy-hs";
> + reg = <0x100f8800 0x30>;
> + clocks = <&gcc USB30_0_UTMI_CLK>;
> + clock-names = "ref";
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + ss_phy_0: ss_phy_0 {
> + compatible = "qcom,ipq806x-usb-phy-ss";
> + reg = <0x100f8830 0x30>;
> + clocks = <&gcc USB30_0_MASTER_CLK>;
> + clock-names = "ref";
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + usb3_0: usb3@100f8800 {
> + compatible = "qcom,dwc3", "syscon";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x100f8800 0x8000>;
> + clocks = <&gcc USB30_0_MASTER_CLK>;
> + clock-names = "core";
> +
> + ranges;
> +
> + resets = <&gcc USB30_0_MASTER_RESET>;
> + reset-names = "master";
> +
> + status = "disabled";
> +
> + dwc3_0: dwc3@10000000 {
> + compatible = "snps,dwc3";
> + reg = <0x10000000 0xcd00>;
> + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&hs_phy_0>, <&ss_phy_0>;
> + phy-names = "usb2-phy", "usb3-phy";
> + dr_mode = "host";
> + snps,dis_u3_susphy_quirk;
> + };
> + };
> +
> + hs_phy_1: hs_phy_1 {
> + compatible = "qcom,ipq806x-usb-phy-hs";
> + reg = <0x110f8800 0x30>;
> + clocks = <&gcc USB30_1_UTMI_CLK>;
> + clock-names = "ref";
> + #phy-cells = <0>;
> + };
> +
> + ss_phy_1: ss_phy_1 {
> + compatible = "qcom,ipq806x-usb-phy-ss";
> + reg = <0x110f8830 0x30>;
> + clocks = <&gcc USB30_1_MASTER_CLK>;
> + clock-names = "ref";
> + #phy-cells = <0>;
> + };
> +
> + usb3_1: usb3@110f8800 {
> + compatible = "qcom,dwc3", "syscon";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x110f8800 0x8000>;
> + clocks = <&gcc USB30_1_MASTER_CLK>;
> + clock-names = "core";
> +
> + ranges;
> +
> + resets = <&gcc USB30_1_MASTER_RESET>;
> + reset-names = "master";
> +
> + status = "disabled";
> +
> + dwc3_1: dwc3@11000000 {
> + compatible = "snps,dwc3";
> + reg = <0x11000000 0xcd00>;
> + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&hs_phy_1>, <&ss_phy_1>;
> + phy-names = "usb2-phy", "usb3-phy";
> + dr_mode = "host";
> + snps,dis_u3_susphy_quirk;
> + };
> + };
> +
> vsdcc_fixed: vsdcc-regulator {
> compatible = "regulator-fixed";
> regulator-name = "SDCC Power";
> --
> 2.20.1
>