TI's J7200 SoC supports additional PHY modes like QSGMII and SGMII
that are not supported on earlier SoCs. Add a compatible for it.
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
.../mfd/ti,j721e-system-controller.yaml | 6 +++++
.../bindings/phy/ti,phy-gmii-sel.yaml | 25 +++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
index 1aeac43cad92..873ee0c0973f 100644
--- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
+++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
@@ -54,6 +54,12 @@ patternProperties:
description:
Clock provider for TI EHRPWM nodes.
+ "phy@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/phy/ti,phy-gmii-sel.yaml#
+ description:
+ The phy node corresponding to the ethernet MAC.
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
index 016a37db1ea1..da7cac537e15 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
@@ -53,12 +53,25 @@ properties:
- ti,am43xx-phy-gmii-sel
- ti,dm814-phy-gmii-sel
- ti,am654-phy-gmii-sel
+ - ti,j7200-cpsw5g-phy-gmii-sel
reg:
maxItems: 1
'#phy-cells': true
+ ti,qsgmii-main-ports:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Required only for QSGMII mode. Array to select the port for
+ QSGMII main mode. Rest of the ports are selected as QSGMII_SUB
+ ports automatically. Any one of the 4 CPSW5G ports can act as the
+ main port with the rest of them being the QSGMII_SUB ports.
+ maxItems: 1
+ items:
+ minimum: 1
+ maximum: 4
+
allOf:
- if:
properties:
@@ -73,6 +86,18 @@ allOf:
'#phy-cells':
const: 1
description: CPSW port number (starting from 1)
+
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,j7200-cpsw5g-phy-gmii-sel
+ then:
+ properties:
+ ti,qsgmii-main-ports: false
+
- if:
properties:
compatible:
--
2.25.1
On 12/09/2022 10:56, Siddharth Vadapalli wrote:
> required:
> - compatible
> - reg
> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
> index 016a37db1ea1..da7cac537e15 100644
> --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
> +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
> @@ -53,12 +53,25 @@ properties:
> - ti,am43xx-phy-gmii-sel
> - ti,dm814-phy-gmii-sel
> - ti,am654-phy-gmii-sel
> + - ti,j7200-cpsw5g-phy-gmii-sel
>
> reg:
> maxItems: 1
>
> '#phy-cells': true
>
> + ti,qsgmii-main-ports:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description: |
> + Required only for QSGMII mode. Array to select the port for
Not really an array...
> + QSGMII main mode. Rest of the ports are selected as QSGMII_SUB
> + ports automatically. Any one of the 4 CPSW5G ports can act as the
> + main port with the rest of them being the QSGMII_SUB ports.
> + maxItems: 1
You say it is an array, but you have here just one item, so it is just
uint32. Do you expect it to grow? If so, when? Why it cannot grow now?
Best regards,
Krzysztof
Hello Krzysztof,
On 13/09/22 14:57, Krzysztof Kozlowski wrote:
> On 12/09/2022 10:56, Siddharth Vadapalli wrote:
>
>> required:
>> - compatible
>> - reg
>> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
>> index 016a37db1ea1..da7cac537e15 100644
>> --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
>> +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
>> @@ -53,12 +53,25 @@ properties:
>> - ti,am43xx-phy-gmii-sel
>> - ti,dm814-phy-gmii-sel
>> - ti,am654-phy-gmii-sel
>> + - ti,j7200-cpsw5g-phy-gmii-sel
>>
>> reg:
>> maxItems: 1
>>
>> '#phy-cells': true
>>
>> + ti,qsgmii-main-ports:
>> + $ref: /schemas/types.yaml#/definitions/uint32-array
>> + description: |
>> + Required only for QSGMII mode. Array to select the port for
>
> Not really an array...
>
>> + QSGMII main mode. Rest of the ports are selected as QSGMII_SUB
>> + ports automatically. Any one of the 4 CPSW5G ports can act as the
>> + main port with the rest of them being the QSGMII_SUB ports.
>> + maxItems: 1
>
>
> You say it is an array, but you have here just one item, so it is just
> uint32. Do you expect it to grow? If so, when? Why it cannot grow now?
Thank you for reviewing the patch.
I have defined it as an array because I plan to reuse this property for
other TI devices like J721e which supports up to two QSGMII main ports.
J7200 on the other hand can have at most one QSGMII main port, which is
why I have restricted the array size to one element as of this series.
In the upcoming patches that I will be posting for J721e, I will be
changing the maxItems to 2 for J721e's compatible while it will continue
to remain 1 for J7200's compatible. This is the reason for defining the
property as an array.
Regards,
Siddharth.
On 13/09/2022 11:45, Siddharth Vadapalli wrote:
> Hello Krzysztof,
>
> On 13/09/22 14:57, Krzysztof Kozlowski wrote:
>> On 12/09/2022 10:56, Siddharth Vadapalli wrote:
>>
>>> required:
>>> - compatible
>>> - reg
>>> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
>>> index 016a37db1ea1..da7cac537e15 100644
>>> --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
>>> +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
>>> @@ -53,12 +53,25 @@ properties:
>>> - ti,am43xx-phy-gmii-sel
>>> - ti,dm814-phy-gmii-sel
>>> - ti,am654-phy-gmii-sel
>>> + - ti,j7200-cpsw5g-phy-gmii-sel
>>>
>>> reg:
>>> maxItems: 1
>>>
>>> '#phy-cells': true
>>>
>>> + ti,qsgmii-main-ports:
>>> + $ref: /schemas/types.yaml#/definitions/uint32-array
>>> + description: |
>>> + Required only for QSGMII mode. Array to select the port for
>>
>> Not really an array...
>>
>>> + QSGMII main mode. Rest of the ports are selected as QSGMII_SUB
>>> + ports automatically. Any one of the 4 CPSW5G ports can act as the
>>> + main port with the rest of them being the QSGMII_SUB ports.
>>> + maxItems: 1
>>
>>
>> You say it is an array, but you have here just one item, so it is just
>> uint32. Do you expect it to grow? If so, when? Why it cannot grow now?
>
> Thank you for reviewing the patch.
>
> I have defined it as an array because I plan to reuse this property for
> other TI devices like J721e which supports up to two QSGMII main ports.
> J7200 on the other hand can have at most one QSGMII main port, which is
> why I have restricted the array size to one element as of this series.
> In the upcoming patches that I will be posting for J721e, I will be
> changing the maxItems to 2 for J721e's compatible while it will continue
> to remain 1 for J7200's compatible. This is the reason for defining the
> property as an array.
I have an impression that I asked this and you already replied... so
apologies for asking again. :)
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof