This patch series add supporting qca8081 1G version chip, the 1G version
chip can be identified by the register mmd7.0x901d bit0.
In addition, qca8081 does not support 1000BaseX mode and the fifo reset
is added on the link changed, which assert the fifo on the link down,
deassert the fifo on the link up.
Luo Jie (3):
net: phy: at803x: support qca8081 1G chip type
net: phy: at803x: remove 1000BaseX mode of qca8081
net: phy: at803x: add qca8081 fifo reset on the link down
drivers/net/phy/at803x.c | 79 +++++++++++++++++++++++++++++-----------
1 file changed, 58 insertions(+), 21 deletions(-)
base-commit: ae230642190a51b85656d6da2df744d534d59544
--
2.17.1
The qca8081 1G chip version does not support 2.5 capability, which
is distinguished from qca8081 2.5G chip according to the bit0 of
register mmd7.0x901d.
The fast retrain and master slave seed configs are only needed when
the 2.5G capability is supported.
Signed-off-by: Luo Jie <[email protected]>
---
drivers/net/phy/at803x.c | 58 ++++++++++++++++++++++++++--------------
1 file changed, 38 insertions(+), 20 deletions(-)
diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index c1f307d90518..3339ca372b24 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -272,6 +272,10 @@
#define QCA808X_CDT_STATUS_STAT_OPEN 2
#define QCA808X_CDT_STATUS_STAT_SHORT 3
+/* QCA808X 1G chip type */
+#define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d
+#define QCA808X_PHY_CHIP_TYPE_1G BIT(0)
+
MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
MODULE_AUTHOR("Matus Ujhelyi");
MODULE_LICENSE("GPL");
@@ -898,12 +902,22 @@ static int at803x_get_features(struct phy_device *phydev)
return err;
if (phydev->drv->phy_id == QCA8081_PHY_ID) {
- err = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_NG_EXTABLE);
+ err = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
if (err < 0)
return err;
- linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported,
- err & MDIO_PMA_NG_EXTABLE_2_5GBT);
+ /* QCA808X does not support 2.5G capability if the chip type is 1G according
+ * to the register MMD7.QCA808X_PHY_MMD7_CHIP_TYPE.
+ */
+
+ if (!(QCA808X_PHY_CHIP_TYPE_1G & err)) {
+ err = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_NG_EXTABLE);
+ if (err < 0)
+ return err;
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported,
+ err & MDIO_PMA_NG_EXTABLE_2_5GBT);
+ }
}
if (phydev->drv->phy_id != ATH8031_PHY_ID)
@@ -1770,20 +1784,22 @@ static int qca808x_config_init(struct phy_device *phydev)
if (ret)
return ret;
- /* Config the fast retrain for the link 2500M */
- ret = qca808x_phy_fast_retrain_config(phydev);
- if (ret)
- return ret;
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) {
+ /* Config the fast retrain for the link 2500M */
+ ret = qca808x_phy_fast_retrain_config(phydev);
+ if (ret)
+ return ret;
- /* Configure lower ramdom seed to make phy linked as slave mode */
- ret = qca808x_phy_ms_random_seed_set(phydev);
- if (ret)
- return ret;
+ /* Configure lower ramdom seed to make phy linked as slave mode */
+ ret = qca808x_phy_ms_random_seed_set(phydev);
+ if (ret)
+ return ret;
- /* Enable seed */
- ret = qca808x_phy_ms_seed_enable(phydev, true);
- if (ret)
- return ret;
+ /* Enable seed */
+ ret = qca808x_phy_ms_seed_enable(phydev, true);
+ if (ret)
+ return ret;
+ }
/* Configure adc threshold as 100mv for the link 10M */
return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
@@ -1822,11 +1838,13 @@ static int qca808x_read_status(struct phy_device *phydev)
* value is configured as the same value, the link can't be up and no link change
* occurs.
*/
- if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR) {
- qca808x_phy_ms_seed_enable(phydev, false);
- } else {
- qca808x_phy_ms_random_seed_set(phydev);
- qca808x_phy_ms_seed_enable(phydev, true);
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) {
+ if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR) {
+ qca808x_phy_ms_seed_enable(phydev, false);
+ } else {
+ qca808x_phy_ms_random_seed_set(phydev);
+ qca808x_phy_ms_seed_enable(phydev, true);
+ }
}
}
--
2.17.1
On Thu, Jun 29, 2023 at 11:48:44AM +0800, Luo Jie wrote:
> The qca8081 1G chip version does not support 2.5 capability, which
> is distinguished from qca8081 2.5G chip according to the bit0 of
> register mmd7.0x901d.
>
> The fast retrain and master slave seed configs are only needed when
> the 2.5G capability is supported.
Does genphy_c45_pma_read_abilities() work on these devices?
Andrew
On 6/29/2023 9:14 PM, Andrew Lunn wrote:
> On Thu, Jun 29, 2023 at 11:48:44AM +0800, Luo Jie wrote:
>> The qca8081 1G chip version does not support 2.5 capability, which
>> is distinguished from qca8081 2.5G chip according to the bit0 of
>> register mmd7.0x901d.
>>
>> The fast retrain and master slave seed configs are only needed when
>> the 2.5G capability is supported.
>
> Does genphy_c45_pma_read_abilities() work on these devices?
>
> Andrew
Hi Andrew,
yes, genphy_c45_pma_read_abilities works on both normal qca8081 2.5G
chip and qca8081 1G version chip, even the PHY ID is same, the only
difference between qca8081 1G and 2.5G chip is the 2.5G capability
removed on 1G version chip.
On Fri, Jun 30, 2023 at 02:39:06PM +0800, Jie Luo wrote:
>
>
> On 6/29/2023 9:14 PM, Andrew Lunn wrote:
> > On Thu, Jun 29, 2023 at 11:48:44AM +0800, Luo Jie wrote:
> > > The qca8081 1G chip version does not support 2.5 capability, which
> > > is distinguished from qca8081 2.5G chip according to the bit0 of
> > > register mmd7.0x901d.
> > >
> > > The fast retrain and master slave seed configs are only needed when
> > > the 2.5G capability is supported.
> >
> > Does genphy_c45_pma_read_abilities() work on these devices?
> >
> > Andrew
>
> Hi Andrew,
> yes, genphy_c45_pma_read_abilities works on both normal qca8081 2.5G chip
> and qca8081 1G version chip, even the PHY ID is same, the only difference
> between qca8081 1G and 2.5G chip is the 2.5G capability removed on 1G
> version chip.
Great, then please use it to simply the driver.
Andrew
On 6/30/2023 9:16 PM, Andrew Lunn wrote:
> On Fri, Jun 30, 2023 at 02:39:06PM +0800, Jie Luo wrote:
>>
>>
>> On 6/29/2023 9:14 PM, Andrew Lunn wrote:
>>> On Thu, Jun 29, 2023 at 11:48:44AM +0800, Luo Jie wrote:
>>>> The qca8081 1G chip version does not support 2.5 capability, which
>>>> is distinguished from qca8081 2.5G chip according to the bit0 of
>>>> register mmd7.0x901d.
>>>>
>>>> The fast retrain and master slave seed configs are only needed when
>>>> the 2.5G capability is supported.
>>>
>>> Does genphy_c45_pma_read_abilities() work on these devices?
>>>
>>> Andrew
>>
>> Hi Andrew,
>> yes, genphy_c45_pma_read_abilities works on both normal qca8081 2.5G chip
>> and qca8081 1G version chip, even the PHY ID is same, the only difference
>> between qca8081 1G and 2.5G chip is the 2.5G capability removed on 1G
>> version chip.
>
> Great, then please use it to simply the driver.
>
> Andrew
Hi Andrew,
Per double check qca8081 PHY registers, the PHY ID only exists in the
MII register, which is not in the MMD device register.
There are MMD device 1, 3, 7 in qca8081 PHY, the PMA abilities
10/100/1000/2500 are compliant with genphy_c45_pma_read_abilities, but
the MDIO_AN_STAT1_ABLE does not exist in MMD7.1 register.
so the genphy_c45_pma_read_abilities can't be fully supported by qca8081
phy, sorry for this misunderstanding.
> There are MMD device 1, 3, 7 in qca8081 PHY, the PMA abilities
> 10/100/1000/2500 are compliant with genphy_c45_pma_read_abilities, but the
> MDIO_AN_STAT1_ABLE does not exist in MMD7.1 register.
>
> so the genphy_c45_pma_read_abilities can't be fully supported by qca8081
> phy, sorry for this misunderstanding.
If all you are missing is MDIO_AN_STAT1_ABLE, then i assume you are
missing Autoneg? So have your tried using
genphy_c45_pma_read_abilities() and then just doing:
linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
phydev->supported);
with a comment explaining why.
Andrew
On 7/1/2023 10:30 PM, Andrew Lunn wrote:
>> There are MMD device 1, 3, 7 in qca8081 PHY, the PMA abilities
>> 10/100/1000/2500 are compliant with genphy_c45_pma_read_abilities, but the
>> MDIO_AN_STAT1_ABLE does not exist in MMD7.1 register.
>>
>> so the genphy_c45_pma_read_abilities can't be fully supported by qca8081
>> phy, sorry for this misunderstanding.
>
> If all you are missing is MDIO_AN_STAT1_ABLE, then i assume you are
> missing Autoneg? So have your tried using
> genphy_c45_pma_read_abilities() and then just doing:
>
> linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
> phydev->supported);
>
> with a comment explaining why.
>
> Andrew
Thanks Andrew for this suggestion, i will verify this code and update
the patch series.