Add json file of T-HEAD C9xx events.
Signed-off-by: Inochi Amaoto <[email protected]>
---
tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
.../arch/riscv/t-head/c9xx/cache.json | 67 ++++++++++++++++++
.../arch/riscv/t-head/c9xx/firmware.json | 68 +++++++++++++++++++
.../arch/riscv/t-head/c9xx/instruction.json | 22 ++++++
.../arch/riscv/t-head/c9xx/microarch.json | 42 ++++++++++++
5 files changed, 200 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json
create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/firmware.json
create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/instruction.json
create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/microarch.json
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
index c61b3d6ef616..9fbdfcdc17ad 100644
--- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -15,3 +15,4 @@
#
#MVENDORID-MARCHID-MIMPID,Version,Filename,EventType
0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
+0x5b7-0x0000000000000000-0x[[:xdigit:]]+,v1,t-head/c9xx,core
diff --git a/tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json
new file mode 100644
index 000000000000..2c6e9a904a11
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json
@@ -0,0 +1,67 @@
+[
+ {
+ "EventName": "L1_ICACHE_ACCESS",
+ "EventCode": "0x000001",
+ "BriefDescription": "L1 instruction cache access"
+ },
+ {
+ "EventName": "L1_ICACHE_MISS",
+ "EventCode": "0x000002",
+ "BriefDescription": "L1 instruction cache miss"
+ },
+ {
+ "EventName": "INST_TLB_MISS",
+ "EventCode": "0x000003",
+ "BriefDescription": "Instruction TLB (I-UTLB) miss"
+ },
+ {
+ "EventName": "DATA_TLB_MISS",
+ "EventCode": "0x000004",
+ "BriefDescription": "Data TLB (D-UTLB) miss"
+ },
+ {
+ "EventName": "JTLB_MISS",
+ "EventCode": "0x000005",
+ "BriefDescription": "JTLB access miss"
+ },
+ {
+ "EventName": "L1_DCACHE_READ_ACCESS",
+ "EventCode": "0x00000c",
+ "BriefDescription": "L1 data cache read access"
+ },
+ {
+ "EventName": "L1_DCACHE_READ_MISS",
+ "EventCode": "0x00000d",
+ "BriefDescription": "L1 data cache read miss"
+ },
+ {
+ "EventName": "L1_DCACHE_WRITE_ACCESS",
+ "EventCode": "0x00000e",
+ "BriefDescription": "L1 data cache write access"
+ },
+ {
+ "EventName": "L1_DCACHE_WRITE_MISS",
+ "EventCode": "0x00000f",
+ "BriefDescription": "L1 data cache write miss"
+ },
+ {
+ "EventName": "L2_CACHE_READ_ACCESS",
+ "EventCode": "0x000010",
+ "BriefDescription": "L2 cache read access"
+ },
+ {
+ "EventName": "L2_CACHE_READ_MISS",
+ "EventCode": "0x000011",
+ "BriefDescription": "L2 cache read miss"
+ },
+ {
+ "EventName": "L2_CACHE_WRITE_ACCESS",
+ "EventCode": "0x000012",
+ "BriefDescription": "L2 cache write access"
+ },
+ {
+ "EventName": "L2_CACHE_WRITE_MISS",
+ "EventCode": "0x000013",
+ "BriefDescription": "L2 cache write miss"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/t-head/c9xx/firmware.json b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/firmware.json
new file mode 100644
index 000000000000..9b4a032186a7
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/firmware.json
@@ -0,0 +1,68 @@
+[
+ {
+ "ArchStdEvent": "FW_MISALIGNED_LOAD"
+ },
+ {
+ "ArchStdEvent": "FW_MISALIGNED_STORE"
+ },
+ {
+ "ArchStdEvent": "FW_ACCESS_LOAD"
+ },
+ {
+ "ArchStdEvent": "FW_ACCESS_STORE"
+ },
+ {
+ "ArchStdEvent": "FW_ILLEGAL_INSN"
+ },
+ {
+ "ArchStdEvent": "FW_SET_TIMER"
+ },
+ {
+ "ArchStdEvent": "FW_IPI_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_IPI_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_FENCE_I_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_FENCE_I_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_SFENCE_VMA_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_GVMA_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_VVMA_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/t-head/c9xx/instruction.json b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/instruction.json
new file mode 100644
index 000000000000..53c5a9838400
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/instruction.json
@@ -0,0 +1,22 @@
+[
+ {
+ "EventName": "BR_COND_MIS_PRED",
+ "EventCode": "0x000006",
+ "BriefDescription": "Conditional branch mispredict"
+ },
+ {
+ "EventName": "BR_INDIRECT_MIS_PRED",
+ "EventCode": "0x000008",
+ "BriefDescription": "Indirect branch mispredict"
+ },
+ {
+ "EventName": "BR_INDIRECT_INST",
+ "EventCode": "0x000009",
+ "BriefDescription": "Indirect branch instruction"
+ },
+ {
+ "EventName": "INST_STORE",
+ "EventCode": "0x00000b",
+ "BriefDescription": "Store instruction retired"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/t-head/c9xx/microarch.json b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/microarch.json
new file mode 100644
index 000000000000..47f94890d20f
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/microarch.json
@@ -0,0 +1,42 @@
+[
+ {
+ "EventName": "LSU_SPEC_FAIL",
+ "EventCode": "0x00000a",
+ "BriefDescription": "LSU Spec Fail"
+ },
+ {
+ "EventName": "RF_LAUNCH_FAIL",
+ "EventCode": "0x000014",
+ "BriefDescription": "Register file launch fail"
+ },
+ {
+ "EventName": "RF_REG_LAUNCH",
+ "EventCode": "0x000015",
+ "BriefDescription": "Register file reg launch"
+ },
+ {
+ "EventName": "RF_INSTRUCTION",
+ "EventCode": "0x000016",
+ "BriefDescription": "Register file instruction"
+ },
+ {
+ "EventName": "LSU_STALL_CROSS_4K",
+ "EventCode": "0x000017",
+ "BriefDescription": "LSU stall with cross 4K access"
+ },
+ {
+ "EventName": "LSU_STALL_OTHER",
+ "EventCode": "0x000018",
+ "BriefDescription": "LSU stall with other events"
+ },
+ {
+ "EventName": "LSU_SQ_DISCARD",
+ "EventCode": "0x000019",
+ "BriefDescription": "LSU SQ discard"
+ },
+ {
+ "EventName": "LSU_SQ_DISCARD_DATA",
+ "EventCode": "0x00001a",
+ "BriefDescription": "LSU SQ data discard"
+ }
+]
--
2.40.1
Hello Inochi Amaoto!
Do c906 and c910 have same HPM events ?
https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v
and
https://github.com/T-head-Semi/openc910/blob/main/C910_RTL_FACTORY/gen_rtl/pmu/rtl/ct_hpcp_top.v
Look different to me - am i missing something ?
On Tue, 2023-05-16 at 10:37 +0800, Inochi Amaoto wrote:
> Add json file of T-HEAD C9xx events.
>
> Signed-off-by: Inochi Amaoto <[email protected]>
> ---
> tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
> .../arch/riscv/t-head/c9xx/cache.json | 67
> ++++++++++++++++++
> .../arch/riscv/t-head/c9xx/firmware.json | 68
> +++++++++++++++++++
> .../arch/riscv/t-head/c9xx/instruction.json | 22 ++++++
> .../arch/riscv/t-head/c9xx/microarch.json | 42 ++++++++++++
> 5 files changed, 200 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/cache.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/firmware.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/microarch.json
>
> diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv
> b/tools/perf/pmu-events/arch/riscv/mapfile.csv
> index c61b3d6ef616..9fbdfcdc17ad 100644
> --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
> +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
> @@ -15,3 +15,4 @@
> #
> #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType
> 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
> +0x5b7-0x0000000000000000-0x[[:xdigit:]]+,v1,t-head/c9xx,core
> diff --git a/tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json
> b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json
> new file mode 100644
> index 000000000000..2c6e9a904a11
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json
> @@ -0,0 +1,67 @@
> +[
> + {
> + "EventName": "L1_ICACHE_ACCESS",
> + "EventCode": "0x000001",
> + "BriefDescription": "L1 instruction cache access"
> + },
> + {
> + "EventName": "L1_ICACHE_MISS",
> + "EventCode": "0x000002",
> + "BriefDescription": "L1 instruction cache miss"
> + },
> + {
> + "EventName": "INST_TLB_MISS",
> + "EventCode": "0x000003",
> + "BriefDescription": "Instruction TLB (I-UTLB) miss"
> + },
> + {
> + "EventName": "DATA_TLB_MISS",
> + "EventCode": "0x000004",
> + "BriefDescription": "Data TLB (D-UTLB) miss"
> + },
> + {
> + "EventName": "JTLB_MISS",
> + "EventCode": "0x000005",
> + "BriefDescription": "JTLB access miss"
> + },
> + {
> + "EventName": "L1_DCACHE_READ_ACCESS",
> + "EventCode": "0x00000c",
> + "BriefDescription": "L1 data cache read access"
> + },
> + {
> + "EventName": "L1_DCACHE_READ_MISS",
> + "EventCode": "0x00000d",
> + "BriefDescription": "L1 data cache read miss"
> + },
> + {
> + "EventName": "L1_DCACHE_WRITE_ACCESS",
> + "EventCode": "0x00000e",
> + "BriefDescription": "L1 data cache write access"
> + },
> + {
> + "EventName": "L1_DCACHE_WRITE_MISS",
> + "EventCode": "0x00000f",
> + "BriefDescription": "L1 data cache write miss"
> + },
> + {
> + "EventName": "L2_CACHE_READ_ACCESS",
> + "EventCode": "0x000010",
> + "BriefDescription": "L2 cache read access"
> + },
> + {
> + "EventName": "L2_CACHE_READ_MISS",
> + "EventCode": "0x000011",
> + "BriefDescription": "L2 cache read miss"
> + },
> + {
> + "EventName": "L2_CACHE_WRITE_ACCESS",
> + "EventCode": "0x000012",
> + "BriefDescription": "L2 cache write access"
> + },
> + {
> + "EventName": "L2_CACHE_WRITE_MISS",
> + "EventCode": "0x000013",
> + "BriefDescription": "L2 cache write miss"
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/firmware.json b/tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/firmware.json
> new file mode 100644
> index 000000000000..9b4a032186a7
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/firmware.json
> @@ -0,0 +1,68 @@
> +[
> + {
> + "ArchStdEvent": "FW_MISALIGNED_LOAD"
> + },
> + {
> + "ArchStdEvent": "FW_MISALIGNED_STORE"
> + },
> + {
> + "ArchStdEvent": "FW_ACCESS_LOAD"
> + },
> + {
> + "ArchStdEvent": "FW_ACCESS_STORE"
> + },
> + {
> + "ArchStdEvent": "FW_ILLEGAL_INSN"
> + },
> + {
> + "ArchStdEvent": "FW_SET_TIMER"
> + },
> + {
> + "ArchStdEvent": "FW_IPI_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_IPI_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_FENCE_I_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_FENCE_I_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_SFENCE_VMA_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_GVMA_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_VVMA_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/instruction.json b/tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/instruction.json
> new file mode 100644
> index 000000000000..53c5a9838400
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/instruction.json
> @@ -0,0 +1,22 @@
> +[
> + {
> + "EventName": "BR_COND_MIS_PRED",
> + "EventCode": "0x000006",
> + "BriefDescription": "Conditional branch mispredict"
> + },
> + {
> + "EventName": "BR_INDIRECT_MIS_PRED",
> + "EventCode": "0x000008",
> + "BriefDescription": "Indirect branch mispredict"
> + },
> + {
> + "EventName": "BR_INDIRECT_INST",
> + "EventCode": "0x000009",
> + "BriefDescription": "Indirect branch instruction"
> + },
> + {
> + "EventName": "INST_STORE",
> + "EventCode": "0x00000b",
> + "BriefDescription": "Store instruction retired"
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/microarch.json b/tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/microarch.json
> new file mode 100644
> index 000000000000..47f94890d20f
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/microarch.json
> @@ -0,0 +1,42 @@
> +[
> + {
> + "EventName": "LSU_SPEC_FAIL",
> + "EventCode": "0x00000a",
> + "BriefDescription": "LSU Spec Fail"
> + },
> + {
> + "EventName": "RF_LAUNCH_FAIL",
> + "EventCode": "0x000014",
> + "BriefDescription": "Register file launch fail"
> + },
> + {
> + "EventName": "RF_REG_LAUNCH",
> + "EventCode": "0x000015",
> + "BriefDescription": "Register file reg launch"
> + },
> + {
> + "EventName": "RF_INSTRUCTION",
> + "EventCode": "0x000016",
> + "BriefDescription": "Register file instruction"
> + },
> + {
> + "EventName": "LSU_STALL_CROSS_4K",
> + "EventCode": "0x000017",
> + "BriefDescription": "LSU stall with cross 4K access"
> + },
> + {
> + "EventName": "LSU_STALL_OTHER",
> + "EventCode": "0x000018",
> + "BriefDescription": "LSU stall with other events"
> + },
> + {
> + "EventName": "LSU_SQ_DISCARD",
> + "EventCode": "0x000019",
> + "BriefDescription": "LSU SQ discard"
> + },
> + {
> + "EventName": "LSU_SQ_DISCARD_DATA",
> + "EventCode": "0x00001a",
> + "BriefDescription": "LSU SQ data discard"
> + }
> +]
> Do c906 and c910 have same HPM events ?
>
> https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v
>
> and
>
>
> https://github.com/T-head-Semi/openc910/blob/main/C910_RTL_FACTORY/gen_rtl/pmu/rtl/ct_hpcp_top.v
>
> Look different to me - am i missing something ?
Yes, they as different, but event ids are compatible. See [1] p.99 and [2] p.73.
It seems I forgot extra event index from C906. I will fix in the v2.
[1] https://github.com/T-head-Semi/openc910/blob/main/doc/%E7%8E%84%E9%93%81C910%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf
[2] https://github.com/T-head-Semi/openc906/blob/main/doc/%E7%8E%84%E9%93%81C906%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf
On Tue, 2023-05-16 at 17:45 +0800, Inochi Amaoto wrote:
> > Do c906 and c910 have same HPM events ?
> >
> > https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v
> >
> > and
> >
> >
> > https://github.com/T-head-Semi/openc910/blob/main/C910_RTL_FACTORY/gen_rtl/pmu/rtl/ct_hpcp_top.v
> >
> > Look different to me - am i missing something ?
>
> Yes, they as different, but event ids are compatible. See [1] p.99
> and [2] p.73.
>
> It seems I forgot extra event index from C906. I will fix in the v2.
>
> [1]
> https://github.com/T-head-Semi/openc910/blob/main/doc/%E7%8E%84%E9%93%81C910%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf
> [2]
> https://github.com/T-head-Semi/openc906/blob/main/doc/%E7%8E%84%E9%93%81C906%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf
They are not the same - they are different in many ways. And c906 list
seems more complete to me.
I think you should drop wildcard (it shouldn't be used anyway) then and
name it c906.
"0x5b7-0x0-0x0,v1,t-head/c906,core" would match both c906 and c910.
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
As my last email is correct, this is a resend.
>
> They are not the same - they are different in many ways. And c906 list
> seems more complete to me.
>
They are different, as this summary:
event id range | support cpu
0x01 - 0x06 | c906,c910,c920
0x07 | c906
0x08 - 0x0a | c910,c920
0x0b - 0x0f | c906,c910,c920
0x10 - 0x1a | c910,c920
0x1b - 0x1c | c910,c920 (software defined, >= 0x1b)
0x1d - 0x2a | c906
This table shows it is not very different. The events of c910 and c906
are complementary.
> I think you should drop wildcard (it shouldn't be used anyway) then and
> name it c906.
>
> "0x5b7-0x0-0x0,v1,t-head/c906,core" would match both c906 and c910.
>
Drop wildcard is a good idea. But I choose to preserve t-head c9xx id,
as it cover all events for c9xx series.
>
> They are not the same - they are different in many ways. And c906 list
> seems more complete to me.
>
They are different, as this summary:
event id range | support cpu
0x01 - 0x06 | c906,c910,c920
0x07 | c906
0x08 - 0x0a | c910,c920
0x0b - 0x0f | c906,c910,c920
0x10 - 0x1a | c910,c920
0x1b - 0x1c | c910,c920 (software defined, >= 0x1b)
0x1d - 0x2a | c906
> I think you should drop wildcard (it shouldn't be used anyway) then and
> name it c906.
>
> "0x5b7-0x0-0x0,v1,t-head/c906,core" would match both c906 and c910.
>
Drop wildcard is a good idea. But I choose to