2022-03-11 15:53:49

by Jim Liu

Subject: [PATCH v1 2/3] dt-bindings: support Nuvoton sgpio

Add nuvoton sgpio yaml in dt-bindings

Signed-off-by: jimliu2 <[email protected]>
---
.../bindings/gpio/nuvoton,sgpio.yaml | 78 +++++++++++++++++++
1 file changed, 78 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml

diff --git a/Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml b/Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml
new file mode 100644
index 000000000000..8766e1fa4528
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/nuvoton,sgpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton SGPIO controller
+
+maintainers:
+ - Jim LIU <[email protected]>
+
+description:
+ This SGPIO controller is for NUVOTON NPCM7xx and NPCM8xx SoC,
+ NPCM7xx/NPCM8xx have two sgpio module each module can support up
+ to 64 output pins,and up to 64 input pin.
+ GPIO pins can be programmed to support the following options
+ - Support interrupt option for each input port and various interrupt
+ sensitivity option (level-high, level-low, edge-high, edge-low)
+ - Directly connected to APB bus and its shift clock is from APB bus clock
+ divided by a programmable value.
+ - ngpios is number of nin_gpios GPIO lines and nout_gpios GPIO lines.
+
+properties:
+ compatible:
+ enum:
+ - nuvoton,npcm750-sgpio
+ - nuvoton,npcm845-sgpio
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ nin_gpios: true
+
+ nout_gpios: true
+
+ bus-frequency: true
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - '#gpio-cells'
+ - interrupts
+ - nin_gpios
+ - nout_gpios
+ - clocks
+ - bus-frequency
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ sgpio1: sgpio@101000 {
+ compatible = "nuvoton,npcm750-sgpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x101000 0x200>;
+ clocks = <&clk NPCM7XX_CLK_APB3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&iox1_pins>;
+ nin_gpios = <64>;
+ nout_gpios = <64>;
+ bus-frequency = <16000000>;
+ };
--
2.17.1

2022-03-11 17:41:07

by Krzysztof Kozlowski

Subject: Re: [PATCH v1 2/3] dt-bindings: support Nuvoton sgpio

On 11/03/2022 07:09, jimliu2 wrote:
> Add nuvoton sgpio yaml in dt-bindings

Missing full stop.

Subject: missing prefix. Check git log history.

>
> Signed-off-by: jimliu2 <[email protected]>
> ---
> .../bindings/gpio/nuvoton,sgpio.yaml | 78 +++++++++++++++++++
> 1 file changed, 78 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml
>
> diff --git a/Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml b/Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml
> new file mode 100644
> index 000000000000..8766e1fa4528
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml
> @@ -0,0 +1,78 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpio/nuvoton,sgpio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Nuvoton SGPIO controller
> +
> +maintainers:
> + - Jim LIU <[email protected]>
> +
> +description:
> + This SGPIO controller is for NUVOTON NPCM7xx and NPCM8xx SoC,
> + NPCM7xx/NPCM8xx have two sgpio module each module can support up
> + to 64 output pins,and up to 64 input pin.
> + GPIO pins can be programmed to support the following options
> + - Support interrupt option for each input port and various interrupt
> + sensitivity option (level-high, level-low, edge-high, edge-low)
> + - Directly connected to APB bus and its shift clock is from APB bus clock
> + divided by a programmable value.
> + - ngpios is number of nin_gpios GPIO lines and nout_gpios GPIO lines.
> +
> +properties:
> + compatible:
> + enum:
> + - nuvoton,npcm750-sgpio
> + - nuvoton,npcm845-sgpio
> +
> + reg:
> + maxItems: 1
> +
> + gpio-controller: true
> +
> + '#gpio-cells':
> + const: 2
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + nin_gpios: true
> +
> + nout_gpios: true

Both do not look like proper property. No description, no vendor prefix,
no type, wrong value (true).

> +
> + bus-frequency: true

Why a GPIO controller needs this legacy bus-frequency property? Which
bus frequency is it? Internal? APB? If APB, use assigned-clocks.

> +
> +required:
> + - compatible
> + - reg
> + - gpio-controller
> + - '#gpio-cells'
> + - interrupts
> + - nin_gpios
> + - nout_gpios
> + - clocks
> + - bus-frequency
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + sgpio1: sgpio@101000 {

Generic node name, so "gpio".

> + compatible = "nuvoton,npcm750-sgpio";
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x101000 0x200>;

reg goes after compatible.

> + clocks = <&clk NPCM7XX_CLK_APB3>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&iox1_pins>;
> + nin_gpios = <64>;
> + nout_gpios = <64>;
> + bus-frequency = <16000000>;
> + };


Best regards,
Krzysztof