Hello All,
We're developing on a Freescale MPC8272 and are having some nasty
problems with PCI bus mastering and data corruption.
We have some custom hardware that is bus mastering, reading data from
the CPUs memory for it's own use. Most of the time, the data is correct,
however occasionally we are seeing data that appears to be from
somewhere else in memory (usually memory that has already been read by
the PCI device). The problem looks like stale data on the PCI bridge
prefetch buffers or a cache coherency problem, but we've been unable to
come up with a solution to our problem. It is my understanding that it
shouldn't be a cache coherency problem as the CPU cache should be
snooped as the data is read from memory. Even if it were an issue, the
pci_map_sg* functions should have sorted out any cache coherency issues
before the DMA operation started.
I've not been able to find anything on the Freescale data sheet that
provides any way of flushing the prefetch cache on the PCI bridge. We've
done a bit of experimenting, and found that turning off prefetch appears
to solve (or possibly mask?) the problem (at the expensive of massive
performance problems). I've also tried DMA'ing two adjacent userspace
buffers in memory (from the same page), and see corruption on the second
buffer. If I populate both buffers, then DMA them both, the data is
fine. If I populate the first, DMA the first, then populate the second
and DMA the second, corruption occurs at the start of the second buffer.
If I add 8-32 bytes of padding between the buffers, the problem goes away.
The PCI spec says that the PCI bridge is supposed to flush any data from
it's prefetch buffers that are not read by the bus master, so
technically, this isn't supposed to happen.
I've tried making sure that buffers are cache line (and page) aligned,
and are multiples of cache lines, but it's made no difference. PIO mode
works fine, and I've checked the data with the CPU just before, and
immediately after the DMA and the driver sees no data integrity issues.
There are memory write barriers just before the DMA start, so all the
registers should be correct before the DMA starts.
For background info, the device doing the bus mastering is a Xilinx
Virtex 5 FPGA. We've monitored the data as it comes off the PCI bus
using ChipScope - so the firmware should not be manipulating the data in
any way.
We have some hardware/firmware/drivers that has a lot of common code
that runs on an x86 platform (as opposed to powerpc), and that works
without any issues whatsoever.
Has anyone got any ideas what this might be? Does anyone of know issues
with PCI bridges on the PowerPC platform? Is there extra things that
need to be done from the driver when DMAing on PowerPC (I've looked at
other drivers and there's nothing obvious). The chip errata doesn't have
anything on it that looks like it could cause this.
I'm really hoping this is something that we're doing wrong in the driver
or the firmware, but we've been through both the firmware and drivers
countless times and are unable to see anything wrong.
Any thoughts/ideas would be much appreciated!
Regards,
Chris
--
______________________________
Chris Pringle
Software Engineer
Miranda Technologies Ltd.
Hithercroft Road
Wallingford
Oxfordshire OX10 9DG
UK
Tel. +44 1491 820206
Fax. +44 1491 820001
http://www.miranda.com
____________________________
Miranda Technologies Limited
Registered in England and Wales CN 02017053
Registered Office: James House, Mere Park, Dedmere Road, Marlow, Bucks, SL7 1FJ
On Tue June 16 2009, Chris Pringle wrote:
> Hello All,
>
> We're developing on a Freescale MPC8272 and are having some nasty
> problems with PCI bus mastering and data corruption.
>
> We have some custom hardware that is bus mastering, reading data from
> the CPUs memory for it's own use. Most of the time, the data is correct,
> however occasionally we are seeing data that appears to be from
> somewhere else in memory (usually memory that has already been read by
> the PCI device). The problem looks like stale data on the PCI bridge
> prefetch buffers or a cache coherency problem, but we've been unable to
> come up with a solution to our problem. It is my understanding that it
> shouldn't be a cache coherency problem as the CPU cache should be
> snooped as the data is read from memory. Even if it were an issue, the
> pci_map_sg* functions should have sorted out any cache coherency issues
> before the DMA operation started.
>
> I've not been able to find anything on the Freescale data sheet that
> provides any way of flushing the prefetch cache on the PCI bridge. We've
> done a bit of experimenting, and found that turning off prefetch appears
> to solve (or possibly mask?) the problem (at the expensive of massive
> performance problems). I've also tried DMA'ing two adjacent userspace
> buffers in memory (from the same page), and see corruption on the second
> buffer. If I populate both buffers, then DMA them both, the data is
> fine. If I populate the first, DMA the first, then populate the second
> and DMA the second, corruption occurs at the start of the second buffer.
> If I add 8-32 bytes of padding between the buffers, the problem goes away.
>
> The PCI spec says that the PCI bridge is supposed to flush any data from
> it's prefetch buffers that are not read by the bus master, so
> technically, this isn't supposed to happen.
>
> I've tried making sure that buffers are cache line (and page) aligned,
> and are multiples of cache lines, but it's made no difference. PIO mode
> works fine, and I've checked the data with the CPU just before, and
> immediately after the DMA and the driver sees no data integrity issues.
> There are memory write barriers just before the DMA start, so all the
> registers should be correct before the DMA starts.
>
> For background info, the device doing the bus mastering is a Xilinx
> Virtex 5 FPGA. We've monitored the data as it comes off the PCI bus
> using ChipScope - so the firmware should not be manipulating the data in
> any way.
>
> We have some hardware/firmware/drivers that has a lot of common code
> that runs on an x86 platform (as opposed to powerpc), and that works
> without any issues whatsoever.
>
> Has anyone got any ideas what this might be? Does anyone of know issues
> with PCI bridges on the PowerPC platform? Is there extra things that
> need to be done from the driver when DMAing on PowerPC (I've looked at
> other drivers and there's nothing obvious). The chip errata doesn't have
> anything on it that looks like it could cause this.
>
> I'm really hoping this is something that we're doing wrong in the driver
> or the firmware, but we've been through both the firmware and drivers
> countless times and are unable to see anything wrong.
>
> Any thoughts/ideas would be much appreciated!
>
Did you actually check the load image for proper alignment?
Like in:
gen2-32 compressed # objdump -x vmlinux.bin
- - - - -
Sections:
Idx Name Size VMA LMA File off Algn
- - - - -
21 .data.page_aligned 00001800 c068a000 0068a000 0058b000 2**12
CONTENTS, ALLOC, LOAD, DATA
22 .data.cacheline_aligned 000026c0 c068b800 0068b800 0058c800 2**6
CONTENTS, ALLOC, LOAD, DATA
23 .data.read_mostly 00001e98 c068dec0 0068dec0 0058eec0 2**6
CONTENTS, ALLOC, LOAD, DATA
= = = =
I had to make this change to the x86 loader script to get alignment for VIA:
diff --git a/arch/x86/kernel/vmlinux_32.lds.S b/arch/x86/kernel/vmlinux_32.lds.S
index 62ad500..26f68a5 100644
--- a/arch/x86/kernel/vmlinux_32.lds.S
+++ b/arch/x86/kernel/vmlinux_32.lds.S
@@ -82,7 +82,7 @@ SECTIONS
? ? ? ? *(.data.idt)
? ?}
- ?. = ALIGN(32);
+ ?. = ALIGN(L1_CACHE_BYTES);
? ?.data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - LOAD_OFFSET) {
? ? ? ? *(.data.cacheline_aligned)
? ?}
= = = =
Eyeball your loader script if you haven't already done so.
Mike
> Regards,
> Chris
>
On Tue, 16 Jun 2009 14:58:27 +0100
Chris Pringle <[email protected]> wrote:
> Hello All,
>
> We're developing on a Freescale MPC8272 and are having some nasty
> problems with PCI bus mastering and data corruption.
>
> We have some custom hardware that is bus mastering, reading data from
> the CPUs memory for it's own use. Most of the time, the data is correct,
> however occasionally we are seeing data that appears to be from
> somewhere else in memory (usually memory that has already been read by
> the PCI device). The problem looks like stale data on the PCI bridge
> prefetch buffers or a cache coherency problem, but we've been unable to
> come up with a solution to our problem. It is my understanding that it
> shouldn't be a cache coherency problem as the CPU cache should be
> snooped as the data is read from memory. Even if it were an issue, the
> pci_map_sg* functions should have sorted out any cache coherency issues
> before the DMA operation started.
>
> I've not been able to find anything on the Freescale data sheet that
> provides any way of flushing the prefetch cache on the PCI bridge. We've
> done a bit of experimenting, and found that turning off prefetch appears
> to solve (or possibly mask?) the problem (at the expensive of massive
> performance problems). I've also tried DMA'ing two adjacent userspace
> buffers in memory (from the same page), and see corruption on the second
> buffer. If I populate both buffers, then DMA them both, the data is
> fine. If I populate the first, DMA the first, then populate the second
> and DMA the second, corruption occurs at the start of the second buffer.
> If I add 8-32 bytes of padding between the buffers, the problem goes away.
>
> The PCI spec says that the PCI bridge is supposed to flush any data from
> it's prefetch buffers that are not read by the bus master, so
> technically, this isn't supposed to happen.
>
> I've tried making sure that buffers are cache line (and page) aligned,
> and are multiples of cache lines, but it's made no difference. PIO mode
> works fine, and I've checked the data with the CPU just before, and
> immediately after the DMA and the driver sees no data integrity issues.
> There are memory write barriers just before the DMA start, so all the
> registers should be correct before the DMA starts.
>
> For background info, the device doing the bus mastering is a Xilinx
> Virtex 5 FPGA. We've monitored the data as it comes off the PCI bus
> using ChipScope - so the firmware should not be manipulating the data in
> any way.
>
> We have some hardware/firmware/drivers that has a lot of common code
> that runs on an x86 platform (as opposed to powerpc), and that works
> without any issues whatsoever.
>
> Has anyone got any ideas what this might be? Does anyone of know issues
> with PCI bridges on the PowerPC platform? Is there extra things that
> need to be done from the driver when DMAing on PowerPC (I've looked at
> other drivers and there's nothing obvious). The chip errata doesn't have
> anything on it that looks like it could cause this.
>
> I'm really hoping this is something that we're doing wrong in the driver
> or the firmware, but we've been through both the firmware and drivers
> countless times and are unable to see anything wrong.
>
> Any thoughts/ideas would be much appreciated!
>
> Regards,
> Chris
Can you try allocate the data buffer using dma_alloc_coherent, that can making
the data coherency.
I got the similar issues in the arm cpu with a dma device base on spartan3, using
the dma_alloc_coherent making it works well.
hope this help.
thanks.
--
steve
On Tue, Jun 16, 2009 at 02:58:27PM +0100, Chris Pringle wrote:
> We're developing on a Freescale MPC8272 and are having some nasty
> problems with PCI bus mastering and data corruption.
What kernel version? What firmware? Custom board, or one in upstream
(which one)?
> We have some custom hardware that is bus mastering, reading data from
> the CPUs memory for it's own use. Most of the time, the data is correct,
> however occasionally we are seeing data that appears to be from
> somewhere else in memory (usually memory that has already been read by
> the PCI device). The problem looks like stale data on the PCI bridge
> prefetch buffers or a cache coherency problem, but we've been unable to
> come up with a solution to our problem. It is my understanding that it
> shouldn't be a cache coherency problem as the CPU cache should be
> snooped as the data is read from memory. Even if it were an issue, the
> pci_map_sg* functions should have sorted out any cache coherency issues
> before the DMA operation started.
Cache coherency on PCI DMA requires that the memory be mapped with the M
attribute on this chip, but that should be happening based on detection of
the core.
Also make sure that you park the bus on PCI and raise its arbitration
priority, as done at the end of fixup_pci in arch/powerpc/boot/cuboot-pq2.c.
BTW, you may want to post to [email protected] for
powerpc-specific issues, especially this kind of hardware issue.
-Scott
Scott Wood wrote:
> On Tue, Jun 16, 2009 at 02:58:27PM +0100, Chris Pringle wrote:
>
>> We're developing on a Freescale MPC8272 and are having some nasty
>> problems with PCI bus mastering and data corruption.
>>
>
> What kernel version? What firmware? Custom board, or one in upstream
> (which one)?
>
The kernel version is 2.6.26. Firmware is custom on a custom board.
> Cache coherency on PCI DMA requires that the memory be mapped with the M
> attribute on this chip, but that should be happening based on detection of
> the core.
>
I'm not sure where to look to verify this?
> Also make sure that you park the bus on PCI and raise its arbitration
> priority, as done at the end of fixup_pci in arch/powerpc/boot/cuboot-pq2.c.
>
Since this is a reasonably recent kernel, I'd guess that both of these
things are correct. I've had a quick look in that file and there is code
in there raising arbitartion priority and parking the bus.
> BTW, you may want to post to [email protected] for
> powerpc-specific issues, especially this kind of hardware issue.
>
>
I've just posted there :-)
Interestingly, I've just turned off cache snooping and the problem has
got much worse. This has surprised me as I thought that part of the job
done by pci_map_sg was to flush the CPU cache - so I wasn't expecting
this to make any difference. The memory corruption with the cache
snooping turned off is almost identical to that which I'm seeing with it
turned on, only much, much worse.
--
______________________________
Chris Pringle
Software Engineer
Miranda Technologies Ltd.
Hithercroft Road
Wallingford
Oxfordshire OX10 9DG
UK
Tel. +44 1491 820206
Fax. +44 1491 820001
http://www.miranda.com
____________________________
Miranda Technologies Limited
Registered in England and Wales CN 02017053
Registered Office: James House, Mere Park, Dedmere Road, Marlow, Bucks, SL7 1FJ
Chris Pringle wrote:
> The kernel version is 2.6.26. Firmware is custom on a custom board.
>> Cache coherency on PCI DMA requires that the memory be mapped with the M
>> attribute on this chip, but that should be happening based on
>> detection of
>> the core.
>>
> I'm not sure where to look to verify this?
Check asm/cputable.h for CPU_FTR_NEED_COHERENT. Make sure that
CONFIG_8260 is one of the #ifdefs that turns that on. It looks like
that was in place by 2.6.26 in arch/powerpc. I'm not sure what to look
for in arch/ppc.
>> Also make sure that you park the bus on PCI and raise its arbitration
>> priority, as done at the end of fixup_pci in
>> arch/powerpc/boot/cuboot-pq2.c.
>>
> Since this is a reasonably recent kernel,
Not really, there was a fair amount of 82xx work in the mid-2.6.20s.
The addition of CPU_FTR_NEED_COHERENT to 82xx was somewhere in that time.
Can you try 2.6.30?
> I'd guess that both of these
> things are correct. I've had a quick look in that file and there is code
> in there raising arbitartion priority and parking the bus.
Just because the code is there doesn't mean you're using it -- are you
using cuImage? Are you using arch/ppc or arch/powerpc?
Typically this would be done by firmware; it's only in cuboot because
u-boot wasn't doing it.
>> BTW, you may want to post to [email protected] for
>> powerpc-specific issues, especially this kind of hardware issue.
>>
>>
> I've just posted there :-)
Doh, sorry. :-)
> Interestingly, I've just turned off cache snooping and the problem has
> got much worse. This has surprised me as I thought that part of the job
> done by pci_map_sg was to flush the CPU cache
It only flushes the cache on hardware that doesn't do coherent DMA.
-Scott
Scott Wood wrote:
>
> Check asm/cputable.h for CPU_FTR_NEED_COHERENT. Make sure that
> CONFIG_8260 is one of the #ifdefs that turns that on. It looks like
> that was in place by 2.6.26 in arch/powerpc. I'm not sure what to
> look for in arch/ppc.
I've just checked that and it's definitely switched on in CPU_FTR_COMMON
(CONFIG_8260 is also being used).
>
>>> Also make sure that you park the bus on PCI and raise its arbitration
>>> priority, as done at the end of fixup_pci in
>>> arch/powerpc/boot/cuboot-pq2.c.
>>>
>> Since this is a reasonably recent kernel,
>
> Not really, there was a fair amount of 82xx work in the mid-2.6.20s.
> The addition of CPU_FTR_NEED_COHERENT to 82xx was somewhere in that time.
>
> Can you try 2.6.30?
I'll give it a try, but that won't be a quick thing to do - will
hopefully manage to get that done tomorrow if it patches without too
many issues. I should point out that we've got the low latency patches
on this kernel too; I guess it'd be worth trying it without them before
I move kernels.
>
>> I'd guess that both of these things are correct. I've had a quick
>> look in that file and there is code in there raising arbitartion
>> priority and parking the bus.
>
> Just because the code is there doesn't mean you're using it -- are you
> using cuImage? Are you using arch/ppc or arch/powerpc?
>
> Typically this would be done by firmware; it's only in cuboot because
> u-boot wasn't doing it.
Just checked this is being called and it is. We're using arch/powerpc.
>
>
>> Interestingly, I've just turned off cache snooping and the problem
>> has got much worse. This has surprised me as I thought that part of
>> the job done by pci_map_sg was to flush the CPU cache
>
> It only flushes the cache on hardware that doesn't do coherent DMA.
>
Ah right - that would explain what we're seeing then... Doh. Thought I
might have been onto something then. Is there any way to force a cache
flush? That'd at least prove it was a caching issue if it resolved the
problem.
Thanks,
Chris
--
______________________________
Chris Pringle
Software Engineer
Miranda Technologies Ltd.
Hithercroft Road
Wallingford
Oxfordshire OX10 9DG
UK
Tel. +44 1491 820206
Fax. +44 1491 820001
http://www.miranda.com
____________________________
Miranda Technologies Limited
Registered in England and Wales CN 02017053
Registered Office: James House, Mere Park, Dedmere Road, Marlow, Bucks, SL7 1FJ
Chris Pringle wrote:
> Ah right - that would explain what we're seeing then... Doh. Thought I
> might have been onto something then. Is there any way to force a cache
> flush? That'd at least prove it was a caching issue if it resolved the
> problem.
You could enable CONFIG_NOT_COHERENT_CACHE.
-Scott
On Tuesday 16 June 2009, Scott Wood wrote:
> Chris Pringle wrote:
> > Ah right - that would explain what we're seeing then... Doh. Thought I
> > might have been onto something then. Is there any way to force a cache
> > flush? That'd at least prove it was a caching issue if it resolved the
> > problem.
>
> You could enable CONFIG_NOT_COHERENT_CACHE.
If the whole system is noncoherent, that is the right solution. If the
device is the only one, you can also use dma_alloc_noncoherent() and
flush explicitly with dma_cache_sync().
Arnd <><
Arnd Bergmann wrote:
> On Tuesday 16 June 2009, Scott Wood wrote:
>> Chris Pringle wrote:
>>> Ah right - that would explain what we're seeing then... Doh. Thought I
>>> might have been onto something then. Is there any way to force a cache
>>> flush? That'd at least prove it was a caching issue if it resolved the
>>> problem.
>> You could enable CONFIG_NOT_COHERENT_CACHE.
>
> If the whole system is noncoherent, that is the right solution.
I meant it more as a test than a permanent solution...
> If the
> device is the only one, you can also use dma_alloc_noncoherent() and
> flush explicitly with dma_cache_sync().
I don't see how that would help -- aren't those also controlled by
CONFIG_NOT_COHERENT_CACHE?
-Scott
On Tuesday 16 June 2009, Scott Wood wrote:
> > If the
> > device is the only one, you can also use dma_alloc_noncoherent() and
> > flush explicitly with dma_cache_sync().
>
> I don't see how that would help -- aren't those also controlled by
> CONFIG_NOT_COHERENT_CACHE?
Ah, yes you are right. PowerPC implements dma_alloc_noncoherent as
dma_alloc_coherent, so dma_cache_sync() is actually a NOP (or should be).
Actually there seems to be a bug in here: Since dma_alloc_noncoherent
gives you a coherent mapping (or NULL) on noncoherent machines,
dma_cache_sync() is redundant and should not actually flush the
cache, or we should change dma_alloc_noncoherent to do a simple
alloc_pages on CONFIG_NON_COHERENT_CACHE and leave dma_cache_sync()
as it is.
Arnd <><
On Tue, 2009-06-16 at 20:02 +0200, Arnd Bergmann wrote:
> On Tuesday 16 June 2009, Scott Wood wrote:
> > > If the
> > > device is the only one, you can also use dma_alloc_noncoherent() and
> > > flush explicitly with dma_cache_sync().
> >
> > I don't see how that would help -- aren't those also controlled by
> > CONFIG_NOT_COHERENT_CACHE?
>
> Ah, yes you are right. PowerPC implements dma_alloc_noncoherent as
> dma_alloc_coherent, so dma_cache_sync() is actually a NOP (or should be).
But we still need to sync the result of dma_map_* when used multiple
times for a single mapping.
Cheers,
Ben.
> Actually there seems to be a bug in here: Since dma_alloc_noncoherent
> gives you a coherent mapping (or NULL) on noncoherent machines,
> dma_cache_sync() is redundant and should not actually flush the
> cache, or we should change dma_alloc_noncoherent to do a simple
> alloc_pages on CONFIG_NON_COHERENT_CACHE and leave dma_cache_sync()
> as it is.
>
> Arnd <><
> _______________________________________________
> Linuxppc-dev mailing list
> [email protected]
> https://lists.ozlabs.org/listinfo/linuxppc-dev
On Wed, 17 Jun 2009 10:18:45 +1000
Benjamin Herrenschmidt <[email protected]> wrote:
> On Tue, 2009-06-16 at 20:02 +0200, Arnd Bergmann wrote:
> > On Tuesday 16 June 2009, Scott Wood wrote:
> > > > If the
> > > > device is the only one, you can also use dma_alloc_noncoherent() and
> > > > flush explicitly with dma_cache_sync().
> > >
> > > I don't see how that would help -- aren't those also controlled by
> > > CONFIG_NOT_COHERENT_CACHE?
> >
> > Ah, yes you are right. PowerPC implements dma_alloc_noncoherent as
> > dma_alloc_coherent, so dma_cache_sync() is actually a NOP (or should be).
>
> But we still need to sync the result of dma_map_* when used multiple
> times for a single mapping.
We have dma_sync_{single|sg}_for_{cpu|device} API for the above
purpose.
dma_cache_sync is supposed to be used only with the buffers that
dma_alloc_noncoherent() returns. On architecutures that maps
dma_alloc_noncoherent to dma_alloc_coherent, dma_cache_sync() is
supposed to be NOP.
Hello all,
On Wed, Jun 17, 2009 at 2:37 AM, FUJITA
Tomonori<[email protected]> wrote:
> On Wed, 17 Jun 2009 10:18:45 +1000
> Benjamin Herrenschmidt <[email protected]> wrote:
>
>> On Tue, 2009-06-16 at 20:02 +0200, Arnd Bergmann wrote:
>> > On Tuesday 16 June 2009, Scott Wood wrote:
>> > > > If the
>> > > > device is the only one, you can also use dma_alloc_noncoherent() and
>> > > > flush explicitly with dma_cache_sync().
>> > >
>> > > I don't see how that would help -- aren't those also controlled by
>> > > CONFIG_NOT_COHERENT_CACHE?
>> >
>> > Ah, yes you are right. PowerPC implements dma_alloc_noncoherent as
>> > dma_alloc_coherent, so dma_cache_sync() is actually a NOP (or should be).
>>
>> But we still need to sync the result of dma_map_* when used multiple
>> times for a single mapping.
>
> We have dma_sync_{single|sg}_for_{cpu|device} API for the above
> purpose.
>
> dma_cache_sync is supposed to be used only with the buffers that
> dma_alloc_noncoherent() returns. On architecutures that maps
> dma_alloc_noncoherent to dma_alloc_coherent, dma_cache_sync() is
> supposed to be NOP.
This discussion raised some doubt with me about my use case:
I my case (note I am not the poster) I am using (what LDD3 calls)
streaming mappings:
I use pci_map_sg(), have the device perform either DMA master reads or
writes to the bus address using PCIe.
After that, I use pci_unmap_sg().
My assumption is that pci_unmap_sg() either makes the cache coherent
or invalidated and thus I do not need to take further actions.
This is on a MPC83xx or 85xx system.
Is this assumption correct?
Regards,
Leon/
--
Leon
On Wed, 2009-06-17 at 09:37 +0900, FUJITA Tomonori wrote:
>
> dma_cache_sync is supposed to be used only with the buffers that
> dma_alloc_noncoherent() returns. On architecutures that maps
> dma_alloc_noncoherent to dma_alloc_coherent, dma_cache_sync() is
> supposed to be NOP.
>
Or at least a sync() on powerpc but yeah, I see. We should probably do
that.
Cheers,
Ben.
On Wed, 2009-06-17 at 02:56 +0200, Leon Woestenberg wrote:
> I use pci_map_sg(), have the device perform either DMA master reads or
> writes to the bus address using PCIe.
> After that, I use pci_unmap_sg().
>
> My assumption is that pci_unmap_sg() either makes the cache coherent
> or invalidated and thus I do not need to take further actions.
> This is on a MPC83xx or 85xx system.
>
> Is this assumption correct?
It is, as far as I understand things :-) Those APIs are fun.
You should only need the explicit sync calls if you are going to peek or
poke at the DMA mapped memory before you unmap it.
Cheers,
Ben.
Hello Benjamin,
On Wed, Jun 17, 2009 at 3:08 AM, Benjamin
Herrenschmidt<[email protected]> wrote:
> On Wed, 2009-06-17 at 02:56 +0200, Leon Woestenberg wrote:
>> I use pci_map_sg(), have the device perform either DMA master reads or
>> writes to the bus address using PCIe.
>> After that, I use pci_unmap_sg().
>>
>> My assumption is that pci_unmap_sg() either makes the cache coherent
>> or invalidated and thus I do not need to take further actions.
>> This is on a MPC83xx or 85xx system.
>>
>> Is this assumption correct?
>
> It is, as far as I understand things :-) Those APIs are fun.
>
> You should only need the explicit sync calls if you are going to peek or
> poke at the DMA mapped memory before you unmap it.
>
Thanks, then at least I understand things in the corr^H^H^H^Hsame way :-)
And btw, I hadn't seen any data mismatch yet.
Regards,
--
Leon 'likewise' Woestenberg
> You could enable CONFIG_NOT_COHERENT_CACHE.
>
I've just tried this (I had to edit Kconfig in power/platforms to make
the build system accept it), and interestingly it's making no
difference. I'm using streaming mappings, and are using the pci_map_sg
functions to ensure the memory is mapped/flushed correctly. I've also
explicitly put in a pci_dma_sync_sg_for_device, however that's also not
made any difference. Turning the cpu cache snoop off has the same affect
as it did without CONFIG_NOT_COHERENT_CACHE; it gets much worse. Any
other ideas?
Will back off the low latency patches next, and give 2.6.30 a try - see
if that makes any difference.
--
______________________________
Chris Pringle
Software Engineer
Miranda Technologies Ltd.
Hithercroft Road
Wallingford
Oxfordshire OX10 9DG
UK
Tel. +44 1491 820206
Fax. +44 1491 820001
http://www.miranda.com
____________________________
Miranda Technologies Limited
Registered in England and Wales CN 02017053
Registered Office: James House, Mere Park, Dedmere Road, Marlow, Bucks, SL7 1FJ
Chris Pringle wrote:
>> You could enable CONFIG_NOT_COHERENT_CACHE.
>>
> I've just tried this (I had to edit Kconfig in power/platforms to make
> the build system accept it), and interestingly it's making no
> difference. I'm using streaming mappings, and are using the pci_map_sg
> functions to ensure the memory is mapped/flushed correctly. I've also
> explicitly put in a pci_dma_sync_sg_for_device, however that's also
> not made any difference. Turning the cpu cache snoop off has the same
> affect as it did without CONFIG_NOT_COHERENT_CACHE; it gets much
> worse. Any other ideas?
>
> Will back off the low latency patches next, and give 2.6.30 a try -
> see if that makes any difference.
>
Low latency patches made no difference. Tried it with 2.6.30 and it now
works. There are a couple of commits contributing to the fix, including
one introduced between 2.6.29-rc8 and 2.6.29 proper in
powerpc/kernel/head_32.S (couple of commits with the name "Fix Respect
_PAGE_COHERENT on classic ppc32 SW TLB load machines"). I've tried
backporting this to 2.6.29-rc8 and it then worked. Backporting to 2.6.26
made no difference however, so I suspect there are other things fixed
which are also contributing.
I'm going to move to 2.6.29/2.6.30 which should resolve our issue.
Thanks to all who have contributed to this thread.
Chris
--
______________________________
Chris Pringle
Software Engineer
Miranda Technologies Ltd.
Hithercroft Road
Wallingford
Oxfordshire OX10 9DG
UK
Tel. +44 1491 820206
Fax. +44 1491 820001
http://www.miranda.com
____________________________
Miranda Technologies Limited
Registered in England and Wales CN 02017053
Registered Office: James House, Mere Park, Dedmere Road, Marlow, Bucks, SL7 1FJ
Chris Pringle wrote:
> Chris Pringle wrote:
>>> You could enable CONFIG_NOT_COHERENT_CACHE.
>>>
>> I've just tried this (I had to edit Kconfig in power/platforms to
>> make the build system accept it), and interestingly it's making no
>> difference. I'm using streaming mappings, and are using the
>> pci_map_sg functions to ensure the memory is mapped/flushed
>> correctly. I've also explicitly put in a pci_dma_sync_sg_for_device,
>> however that's also not made any difference. Turning the cpu cache
>> snoop off has the same affect as it did without
>> CONFIG_NOT_COHERENT_CACHE; it gets much worse. Any other ideas?
>>
>> Will back off the low latency patches next, and give 2.6.30 a try -
>> see if that makes any difference.
>>
> Low latency patches made no difference. Tried it with 2.6.30 and it
> now works. There are a couple of commits contributing to the fix,
> including one introduced between 2.6.29-rc8 and 2.6.29 proper in
> powerpc/kernel/head_32.S (couple of commits with the name "Fix Respect
> _PAGE_COHERENT on classic ppc32 SW TLB load machines"). I've tried
> backporting this to 2.6.29-rc8 and it then worked. Backporting to
> 2.6.26 made no difference however, so I suspect there are other things
> fixed which are also contributing.
>
> I'm going to move to 2.6.29/2.6.30 which should resolve our issue.
>
> Thanks to all who have contributed to this thread.
>
The other part of the fix is in asm-powerpc/pgtable32.h. _PAGE_BASE
needs _PAGE_COHERENT in order to work correctly, and in fact there is
now a comment in there to that affect in 2.6.29. Backporting that change
has made it work on 2.6.26. Both this patch, and the fix to head_32.S
are needed for it to work correctly on older kernels.
Chris
--
______________________________
Chris Pringle
Software Engineer
Miranda Technologies Ltd.
Hithercroft Road
Wallingford
Oxfordshire OX10 9DG
UK
Tel. +44 1491 820206
Fax. +44 1491 820001
http://www.miranda.com
____________________________
Miranda Technologies Limited
Registered in England and Wales CN 02017053
Registered Office: James House, Mere Park, Dedmere Road, Marlow, Bucks, SL7 1FJ
>The other part of the fix is in asm-powerpc/pgtable32.h. _PAGE_BASE
>needs _PAGE_COHERENT in order to work correctly, and in fact there is
>now a comment in there to that affect in 2.6.29. Backporting that change
>has made it work on 2.6.26. Both this patch, and the fix to head_32.S
>are needed for it to work correctly on older kernels.
>
>Chris
Hello Chris,
sorry for dummy, but if it possible, could you, please, send a corresponding summary patch of backporting you've done for older kernels?
or just summary of that changes once again?
Many thanks
Sergej.-
Hi Sergej,
I've attached the patch used to fix this issue. Both the patch to
pgtable32.h and head_32.S are required in order to make it work. The
change to pgtable32.h ensures that all pages are marked cache coherent
(results in setting the M bit). The change to head_32.S ensures that the
M bit is not unconditionally masked out - it should only be masked out
if CPU_FTR_NEED_COHERENT is not set.
Hope this helps.
Cheers,
Chris
[email protected] wrote:
>> The other part of the fix is in asm-powerpc/pgtable32.h. _PAGE_BASE
>> needs _PAGE_COHERENT in order to work correctly, and in fact there is
>> now a comment in there to that affect in 2.6.29. Backporting that change
>> has made it work on 2.6.26. Both this patch, and the fix to head_32.S
>> are needed for it to work correctly on older kernels.
>>
>> Chris
>>
>
> Hello Chris,
>
> sorry for dummy, but if it possible, could you, please, send a corresponding summary patch of backporting you've done for older kernels?
> or just summary of that changes once again?
>
> Many thanks
>
> Sergej.
--
______________________________
Chris Pringle
Software Engineer
Miranda Technologies Ltd.
Hithercroft Road
Wallingford
Oxfordshire OX10 9DG
UK
Tel. +44 1491 820206
Fax. +44 1491 820001
http://www.miranda.com
____________________________
Miranda Technologies Limited
Registered in England and Wales CN 02017053
Registered Office: James House, Mere Park, Dedmere Road, Marlow, Bucks, SL7 1FJ