From: John(Jung-Ik) Lee <[email protected]>
Fix udma timings of pdc202xx_old controllers.
MB=1, MC=1 (0x20, 0x01) for all UDMA modes of pdc2026{57}.
Signed-off-by: John(Jung-Ik) Lee <[email protected]>
---
drivers/ata/pata_pdc202xx_old.c | 15 +++------------
drivers/ide/pdc202xx_old.c | 8 +++++---
2 files changed, 8 insertions(+), 15 deletions(-)
diff --git a/drivers/ata/pata_pdc202xx_old.c b/drivers/ata/pata_pdc202xx_old.c
index 2f3c9be..ae76a9e 100644
--- a/drivers/ata/pata_pdc202xx_old.c
+++ b/drivers/ata/pata_pdc202xx_old.c
@@ -97,14 +97,6 @@ static void pdc202xx_set_dmamode(struct ata_port
*ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
- static u8 udma_timing[6][2] = {
- { 0x60, 0x03 }, /* 33 Mhz Clock */
- { 0x40, 0x02 },
- { 0x20, 0x01 },
- { 0x40, 0x02 }, /* 66 Mhz Clock */
- { 0x20, 0x01 },
- { 0x20, 0x01 }
- };
static u8 mdma_timing[3][2] = {
{ 0xe0, 0x0f },
{ 0x60, 0x04 },
@@ -119,10 +111,9 @@ static void pdc202xx_set_dmamode(struct ata_port
*ap, struct ata_device *adev)
r_cp &= ~0x0F;
if (adev->dma_mode >= XFER_UDMA_0) {
- int speed = adev->dma_mode - XFER_UDMA_0;
- r_bp |= udma_timing[speed][0];
- r_cp |= udma_timing[speed][1];
-
+ /* MB=1, MC=1 for all UDMA modes of pdc2026{57} */
+ r_bp |= 0x20;
+ r_cp |= 0x01;
} else {
int speed = adev->dma_mode - XFER_MW_DMA_0;
r_bp |= mdma_timing[speed][0];
diff --git a/drivers/ide/pdc202xx_old.c b/drivers/ide/pdc202xx_old.c
index cb812f3..95c58dd 100644
--- a/drivers/ide/pdc202xx_old.c
+++ b/drivers/ide/pdc202xx_old.c
@@ -51,11 +51,13 @@ static void pdc202xx_set_mode(ide_drive_t *drive,
const u8 speed)
switch(speed) {
case XFER_UDMA_5:
- case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
- case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
+ case XFER_UDMA_4:
case XFER_UDMA_3:
- case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
+ case XFER_UDMA_2:
+ case XFER_UDMA_1:
case XFER_UDMA_0:
+ /* MB=1, MC=1 for all UDMA modes of pdc2026{57} */
+ TB = 0x20; TC = 0x01; break;
case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
On Thu, 17 Sep 2009 16:02:31 -0700
"Jung-Ik (John) Lee" <[email protected]> wrote:
> From: John(Jung-Ik) Lee <[email protected]>
>
> Fix udma timings of pdc202xx_old controllers.
> MB=1, MC=1 (0x20, 0x01) for all UDMA modes of pdc2026{57}.
On what documentation is this based ?
Alan
On Thu, Sep 17, 2009 at 4:23 PM, Alan Cox <[email protected]> wrote:
> On Thu, 17 Sep 2009 16:02:31 -0700
> "Jung-Ik (John) Lee" <[email protected]> wrote:
>
>> From: John(Jung-Ik) Lee <[email protected]>
>>
>> Fix udma timings of pdc202xx_old controllers.
>> MB=1, MC=1 (0x20, 0x01) for all UDMA modes of pdc2026{57}.
>
> On what documentation is this based ?
I have two documents, 20265, and 20267, and both need to set to the
same single value for all UDMA modes.
Doc 1:
PDC20265 Bus Mastering Ultra DMA PCI ?ATA/ATAPI Controller
Specification Rev 2.0
#7.17.2, Ultra DMA Data Transfer Speed list
For all Ultra DMA mode, MB, MC = 01h, 01h
Doc 2:
PDC20267 Bus Mastering Ultra DMA PCI ?ATA/ATAPI Controller
Specification Rev 2.0
#7.17.2, Ultra DMA Data Transfer Speed list
For all Ultra DMA mode, MB, MC = 01h, 01h
Are there other pdc202xx old controllers that are different?
-John
>
> Alan
>
Hello.
Jung-Ik (John) Lee wrote:
>>>From: John(Jung-Ik) Lee <[email protected]>
>>>Fix udma timings of pdc202xx_old controllers.
>>>MB=1, MC=1 (0x20, 0x01) for all UDMA modes of pdc2026{57}.
The patch should be broken in two as it's for 2 different subsystems.
>>On what documentation is this based ?
> I have two documents, 20265, and 20267, and both need to set to the
> same single value for all UDMA modes.
> Doc 1:
> PDC20265 Bus Mastering Ultra DMA PCI ?ATA/ATAPI Controller
> Specification Rev 2.0
> #7.17.2, Ultra DMA Data Transfer Speed list
> For all Ultra DMA mode, MB, MC = 01h, 01h
> Doc 2:
> PDC20267 Bus Mastering Ultra DMA PCI ?ATA/ATAPI Controller
> Specification Rev 2.0
> #7.17.2, Ultra DMA Data Transfer Speed list
> For all Ultra DMA mode, MB, MC = 01h, 01h
> Are there other pdc202xx old controllers that are different?
There are PDC20262 and PDC20246. We should ask Bart -- he probably has
the documatation for them...
> -John
>>Alan
WBR, Sergei
On Friday 18 September 2009 13:52:50 Sergei Shtylyov wrote:
> Hello.
>
> Jung-Ik (John) Lee wrote:
>
> >>>From: John(Jung-Ik) Lee <[email protected]>
>
> >>>Fix udma timings of pdc202xx_old controllers.
> >>>MB=1, MC=1 (0x20, 0x01) for all UDMA modes of pdc2026{57}.
>
> The patch should be broken in two as it's for 2 different subsystems.
>
> >>On what documentation is this based ?
>
> > I have two documents, 20265, and 20267, and both need to set to the
> > same single value for all UDMA modes.
>
> > Doc 1:
> > PDC20265 Bus Mastering Ultra DMA PCI ?ATA/ATAPI Controller
> > Specification Rev 2.0
> > #7.17.2, Ultra DMA Data Transfer Speed list
> > For all Ultra DMA mode, MB, MC = 01h, 01h
>
> > Doc 2:
> > PDC20267 Bus Mastering Ultra DMA PCI ?ATA/ATAPI Controller
> > Specification Rev 2.0
> > #7.17.2, Ultra DMA Data Transfer Speed list
> > For all Ultra DMA mode, MB, MC = 01h, 01h
I think that this patch is going in the right direction but it needs to also
take care of 66MHz internal clock setting:
* Please note that the same docs say that "For all Ultra DMA modes, 66MHz
internal clock will be used instead of 33MHz internal clock." and that this
is not true in case of Linux drivers.
* PDC20246 has no 66MHz internal clock AFAIK so those changes should not be
applied for this controller.
> > Are there other pdc202xx old controllers that are different?
>
> There are PDC20262 and PDC20246. We should ask Bart -- he probably has
> the documatation for them...
He doesn't, unfortunately..