2010-04-13 12:22:05

by Michal Simek

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Subject: Microblaze - The fist year

Dear Linux community,

The MicroBlaze Linux Kernel has been in mainline for exactly one year.
It is time to look back and celebrate this year.

First of all I would like to thank Xilinx and PetaLogix for their
committed support and everybody who has helped to improve the MicroBlaze
Linux kernel namely to Andrew Morton, Arnd Bergmann, Edgar E. Iglesias,
Grant Likely, Ingo Molnar, John Linn, John Williams, Linus Torvalds, Sam
Ravnborg, Stephen Neuendorffer and Steve Magnani. Goran Bilski and
Stefan Asserhall (from Xilinx Processing Solutions group) have provided
valuable assistance too.

Thank you for your work.

MicroBlaze is the first soft-cpu to be merged to the mainline Linux
kernel and I believe it has proved to be an effective decision to do so.
With the support of Xilinx and PetaLogix we have dedicated a lot of time
to improve the MicroBlaze Linux port, adding new features and
stabilizing the whole kernel. There are still areas for improvement but
we have set a good direction and we hope with continued support from
Xilinx and PetaLogix to achieve much more in the future


I would like to ask the whole community if you can point us to new
features (or weak places) which should be implemented on MicroBlaze.
Thank you for your continued input.


Let me summarize some MicroBlaze Linux highlights over the last 12 months.

MicroBlaze noMMU - added on April 13, 2009
MicroBlaze QEMU support - April, 2009
MicroBlaze MMU - added on June 12, 2009
First youtube movie with MicroBlaze QEMU by PetaLogix - October 28, 2009
Ftrace support - November 2009
Everyday testing framework - December 2009
and many others

Latest code is available on PetaLogix GIT server.
http://developer.petalogix.com/git/gitweb.cgi (or
http://git.monstr.eu/git/gitweb.cgi)

Output log from everyday testing
http://www.monstr.eu/wiki/doku.php?id=log:log

I also created a new facebook fan page for MicroBlaze where you can join
us. http://www.facebook.com/pages/Microblaze-linux/111131818899940

As I announced on Facebook, I decided to open monstr.eu wiki which is
becoming the microblaze linux wiki.
You can register on
http://www.monstr.eu/wiki/doku.php?id=user:user&do=register

Thank you.

Best regards,
Michal

--
Michal Simek, Ing. (M.Eng)
w: http://www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian


2010-04-13 13:15:20

by Michael Schnell

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Subject: Re: Microblaze - The fist year

Does Microblaze MMU Linux support Futex ?
Does Microblaze MMU Linux support SMP ?

Thanks
-Michael

2010-04-13 13:27:39

by Michal Simek

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Subject: Re: Microblaze - The fist year

Michael Schnell wrote:
> Does Microblaze MMU Linux support Futex ?

yes, futex is there. You can check it in
arch/microblaze/include/asm/futex.h

> Does Microblaze MMU Linux support SMP ?

It is possible to connect several MicroBlazes but the problem is missing
cache coherency modul. I hope that Xilinx will release any version which
will support it.
We haven't done any significant work to support it but it is expected
solution which will happen.

Thanks for input,
Michal

--
Michal Simek, Ing. (M.Eng)
w: http://www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

2010-04-14 07:55:14

by Michael Schnell

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Subject: Re: Microblaze - The fist year

On 04/13/2010 03:27 PM, Michal Simek wrote:
>
> yes, futex is there. You can check it in
> arch/microblaze/include/asm/futex.h
Great ! I'll check how this is done.
>
>> Does Microblaze MMU Linux support SMP ?
>
> It is possible to connect several MicroBlazes but the problem is
> missing cache coherency modul. I hope that Xilinx will release any
> version which will support it.
> We haven't done any significant work to support it but it is expected
> solution which will happen.

Besides cache coherency, another problem might be doing FUTEX. here (I
suppose) SMP safe atomic user space operations are necessary. many
simple RISK (load/store-) CPUs don't provide these (new ARMs provide
"load-locked / store-conditional" on that behalf as an extension to the
load/store paradigm. I suppose these can be done in an SMP-safe way,
supposedly using the hardware that provides cache coherency).

-Michael