From: Abhijeet Dharmapurikar <[email protected]>
This patch series adds support for pmic 8921 chip and its subdevices.
The pmic 8921 chip is used as a power management ic for 8960 based boards. It
communicates over the ssbi bus, ssbi bus can be found here
https://patchwork.kernel.org/patch/601771/
The patch set contains support for interrupt, gpio and mpp (multi purpose pin)
subdevices.
Note that gpio and mpp subdevices need the interrupt subdevice to
be operational, this is becuase the reading the the value of gpio/mpp lines
happens by doing a transaction over registers managed by the interrupt subdev.
The code invokes a call on interrupt subdevice, rather than writing to those
registers directly, avoiding race conditions.
Abhijeet Dharmapurikar (5):
mfd: pm8921: Add PMIC 8921 core driver
mfd: pm8xxx: Add irq support
gpio: pm8xxx-gpio: Add pm8xxx gpio driver
MAINTAINERS: Add pmic8921, pmic8xxx subdevices maintainers
msm: board-8960: Add support for pm8921
David Collins (1):
mfd: pm8xxx-mpp: Add pm8xxx MPP driver
MAINTAINERS | 6 +
arch/arm/mach-msm/board-msm8960.c | 47 ++-
arch/arm/mach-msm/include/mach/irqs-8960.h | 9 +-
drivers/gpio/Kconfig | 10 +
drivers/gpio/Makefile | 1 +
drivers/gpio/pm8xxx-gpio.c | 452 +++++++++++++++++++++
drivers/mfd/Kconfig | 41 ++
drivers/mfd/Makefile | 3 +
drivers/mfd/pm8921-core.c | 288 +++++++++++++
drivers/mfd/pm8xxx-irq.c | 599 ++++++++++++++++++++++++++++
drivers/mfd/pm8xxx-mpp.c | 319 +++++++++++++++
include/linux/mfd/pm8921.h | 48 +++
include/linux/mfd/pm8xxx/core.h | 75 ++++
include/linux/mfd/pm8xxx/gpio.h | 132 ++++++
include/linux/mfd/pm8xxx/irq.h | 62 +++
include/linux/mfd/pm8xxx/mpp.h | 233 +++++++++++
16 files changed, 2310 insertions(+), 15 deletions(-)
create mode 100644 drivers/gpio/pm8xxx-gpio.c
create mode 100644 drivers/mfd/pm8921-core.c
create mode 100644 drivers/mfd/pm8xxx-irq.c
create mode 100644 drivers/mfd/pm8xxx-mpp.c
create mode 100644 include/linux/mfd/pm8921.h
create mode 100644 include/linux/mfd/pm8xxx/core.h
create mode 100644 include/linux/mfd/pm8xxx/gpio.h
create mode 100644 include/linux/mfd/pm8xxx/irq.h
create mode 100644 include/linux/mfd/pm8xxx/mpp.h
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum
From: Abhijeet Dharmapurikar <[email protected]>
Add support for the Qualcomm PM8921 PMIC chip. The core driver
will communicate with the PMIC chip via the MSM SSBI bus.
Change-Id: I4b73e54916406fccc5286634bc0c024f0585c414
Signed-off-by: Abhijeet Dharmapurikar <[email protected]>
---
drivers/mfd/Kconfig | 23 +++++
drivers/mfd/Makefile | 1 +
drivers/mfd/pm8921-core.c | 172 +++++++++++++++++++++++++++++++++++++++
include/linux/mfd/pm8921.h | 26 ++++++
include/linux/mfd/pm8xxx/core.h | 66 +++++++++++++++
5 files changed, 288 insertions(+), 0 deletions(-)
create mode 100644 drivers/mfd/pm8921-core.c
create mode 100644 include/linux/mfd/pm8921.h
create mode 100644 include/linux/mfd/pm8xxx/core.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index fd01836..0a1bc22 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -624,6 +624,29 @@ config MFD_WL1273_CORE
driver connects the radio-wl1273 V4L2 module and the wl1273
audio codec.
+config MFD_PM8XXX
+ tristate "Support for Qualcomm PM8xxx subdevices"
+ help
+ This option enables the usage of various Qualcomm PMIC 8xxx subdevice
+ drivers. This is required in order to use generic PM8xxx subdevice
+ drivers. Selecting with option will result in PM8xxx subdevice
+ drivers being compiled by default.
+
+config MFD_PM8921_CORE
+ tristate "Qualcomm PM8921 PMIC chip"
+ depends on MSM_SSBI
+ select MFD_CORE
+ select MFD_PM8XXX
+ help
+ If you say yes to this option, support will be included for the
+ built-in PM8921 PMIC chip
+
+ This is required if your board has a PM8921 and uses its features,
+ such as: MPPs, GPIOs, regulators, interrupts, and PWM.
+
+ Say M here if you want to include support for PM8921 chip as a module.
+ This will build a module called "pm8921-core.ko".
+
endif # MFD_SUPPORT
menu "Multimedia Capabilities Port drivers"
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index a54e2c7..ec158da 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -83,3 +83,4 @@ obj-$(CONFIG_MFD_TPS6586X) += tps6586x.o
obj-$(CONFIG_MFD_VX855) += vx855.o
obj-$(CONFIG_MFD_WL1273_CORE) += wl1273-core.o
obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o
+obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o
diff --git a/drivers/mfd/pm8921-core.c b/drivers/mfd/pm8921-core.c
new file mode 100644
index 0000000..46ab2fc
--- /dev/null
+++ b/drivers/mfd/pm8921-core.c
@@ -0,0 +1,172 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/msm_ssbi.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/pm8921.h>
+#include <linux/mfd/pm8xxx/core.h>
+
+#define REG_HWREV 0x002 /* PMIC4 revision */
+#define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */
+
+struct pm8921 {
+ struct device *dev;
+};
+
+static int pm8921_readb(const struct device *dev, u16 addr, u8 *val)
+{
+ const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
+ const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
+
+ return msm_ssbi_read(pmic->dev->parent, addr, val, 1);
+}
+
+static int pm8921_writeb(const struct device *dev, u16 addr, u8 val)
+{
+ const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
+ const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
+
+ return msm_ssbi_write(pmic->dev->parent, addr, &val, 1);
+}
+
+static int pm8921_read_buf(const struct device *dev, u16 addr, u8 *buf,
+ int cnt)
+{
+ const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
+ const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
+
+ return msm_ssbi_read(pmic->dev->parent, addr, buf, cnt);
+}
+
+static int pm8921_write_buf(const struct device *dev, u16 addr, u8 *buf,
+ int cnt)
+{
+ const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
+ const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
+
+ return msm_ssbi_write(pmic->dev->parent, addr, buf, cnt);
+}
+
+static struct pm8xxx_drvdata pm8921_drvdata = {
+ .pmic_readb = pm8921_readb,
+ .pmic_writeb = pm8921_writeb,
+ .pmic_read_buf = pm8921_read_buf,
+ .pmic_write_buf = pm8921_write_buf,
+};
+
+static int __devinit pm8921_add_subdevices(const struct pm8921_platform_data
+ *pdata,
+ struct pm8921 *pmic)
+{
+ return 0;
+}
+
+static int __devinit pm8921_probe(struct platform_device *pdev)
+{
+ const struct pm8921_platform_data *pdata = pdev->dev.platform_data;
+ struct pm8921 *pmic;
+ int rc;
+ u8 val;
+
+ if (!pdata) {
+ pr_err("missing platform data\n");
+ return -EINVAL;
+ }
+
+ pmic = kzalloc(sizeof(struct pm8921), GFP_KERNEL);
+ if (!pmic) {
+ pr_err("Cannot alloc pm8921 struct\n");
+ return -ENOMEM;
+ }
+
+ /* Read PMIC chip revision */
+ rc = msm_ssbi_read(pdev->dev.parent, REG_HWREV, &val, sizeof(val));
+ if (rc) {
+ pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
+ goto err_read_rev;
+ }
+ pr_info("PMIC revision: %02X\n", val);
+
+ /* Read PMIC chip revision 2 */
+ rc = msm_ssbi_read(pdev->dev.parent, REG_HWREV_2, &val, sizeof(val));
+ if (rc) {
+ pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
+ REG_HWREV_2, rc);
+ goto err_read_rev;
+ }
+ pr_info("PMIC revision 2: %02X\n", val);
+
+ pmic->dev = &pdev->dev;
+ pm8921_drvdata.pm_chip_data = pmic;
+ platform_set_drvdata(pdev, &pm8921_drvdata);
+
+ rc = pm8921_add_subdevices(pdata, pmic);
+ if (rc) {
+ pr_err("Cannot add subdevices rc=%d\n", rc);
+ goto err;
+ }
+
+ return 0;
+
+err:
+ platform_set_drvdata(pdev, NULL);
+err_read_rev:
+ kfree(pmic);
+ return rc;
+}
+
+static int __devexit pm8921_remove(struct platform_device *pdev)
+{
+ struct pm8xxx_drvdata *drvdata;
+ struct pm8921 *pmic = NULL;
+
+ drvdata = platform_get_drvdata(pdev);
+ if (drvdata)
+ pmic = drvdata->pm_chip_data;
+ if (pmic)
+ mfd_remove_devices(pmic->dev);
+ platform_set_drvdata(pdev, NULL);
+ kfree(pmic);
+
+ return 0;
+}
+
+static struct platform_driver pm8921_driver = {
+ .probe = pm8921_probe,
+ .remove = __devexit_p(pm8921_remove),
+ .driver = {
+ .name = "pm8921-core",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init pm8921_init(void)
+{
+ return platform_driver_register(&pm8921_driver);
+}
+postcore_initcall(pm8921_init);
+
+static void __exit pm8921_exit(void)
+{
+ platform_driver_unregister(&pm8921_driver);
+}
+module_exit(pm8921_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PMIC 8921 core driver");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("platform:pm8921-core");
diff --git a/include/linux/mfd/pm8921.h b/include/linux/mfd/pm8921.h
new file mode 100644
index 0000000..17fc37b
--- /dev/null
+++ b/include/linux/mfd/pm8921.h
@@ -0,0 +1,26 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PMIC 8921 driver header file
+ *
+ */
+
+#ifndef __MFD_PM8921_H
+#define __MFD_PM8921_H
+
+#include <linux/device.h>
+
+struct pm8921_platform_data {
+ int irq_base;
+};
+
+#endif
diff --git a/include/linux/mfd/pm8xxx/core.h b/include/linux/mfd/pm8xxx/core.h
new file mode 100644
index 0000000..61f1c01
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/core.h
@@ -0,0 +1,66 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PMIC 8xxx driver header file
+ *
+ */
+
+#ifndef __MFD_PM8XXX_CORE_H
+#define __MFD_PM8XXX_CORE_H
+
+#include <linux/mfd/core.h>
+
+struct pm8xxx_drvdata {
+ int (*pmic_readb) (const struct device *dev, u16 addr, u8 *val);
+ int (*pmic_writeb) (const struct device *dev, u16 addr, u8 val);
+ int (*pmic_read_buf) (const struct device *dev, u16 addr, u8 *buf,
+ int n);
+ int (*pmic_write_buf) (const struct device *dev, u16 addr, u8 *buf,
+ int n);
+ void *pm_chip_data;
+};
+
+static inline int pm8xxx_readb(const struct device *dev, u16 addr, u8 *val)
+{
+ struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+ BUG_ON(!dd);
+ return dd->pmic_readb(dev, addr, val);
+}
+
+static inline int pm8xxx_writeb(const struct device *dev, u16 addr, u8 val)
+{
+ struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+ BUG_ON(!dd);
+ return dd->pmic_writeb(dev, addr, val);
+}
+
+static inline int pm8xxx_read_buf(const struct device *dev, u16 addr, u8 *buf,
+ int n)
+{
+ struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+ BUG_ON(!dd);
+ return dd->pmic_read_buf(dev, addr, buf, n);
+}
+
+static inline int pm8xxx_write_buf(const struct device *dev, u16 addr, u8 *buf,
+ int n)
+{
+ struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+ BUG_ON(!dd);
+ return dd->pmic_write_buf(dev, addr, buf, n);
+}
+
+#endif
--
1.7.1
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum
From: Abhijeet Dharmapurikar <[email protected]>
Change-Id: I253231c9410930a221351a3d69da95e0014f4786
Signed-off-by: Abhijeet Dharmapurikar <[email protected]>
---
MAINTAINERS | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 696cb18..97107fd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -905,6 +905,12 @@ F: drivers/mmc/host/msm_sdcc.h
F: drivers/tty/serial/msm_serial.h
F: drivers/tty/serial/msm_serial.c
F: drivers/platform/msm/
+F: drivers/mfd/pm8921-core.c
+F: drivers/mfd/pm8xxx-mpp.c
+F: include/linux/mfd/pm8921.h
+F: include/linux/mfd/pm8xxx/
+F: drivers/gpio/pm8xxx-gpio.c
+F: drivers/mfd/pm8xxx-irq.c
T: git git://codeaurora.org/quic/kernel/davidb/linux-msm.git
S: Maintained
--
1.7.1
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum
From: Abhijeet Dharmapurikar <[email protected]>
Add device structure declarations to the msm8960 board file
for PMIC 8921 chip and its subdevices.
Change-Id: I93a2c929a98e93a3b7a4e6e6e05381b519516d1f
Signed-off-by: Abhijeet Dharmapurikar <[email protected]>
Signed-off-by: David Collins <[email protected]>
---
arch/arm/mach-msm/board-msm8960.c | 47 ++++++++++++++++++++++------
arch/arm/mach-msm/include/mach/irqs-8960.h | 9 ++---
2 files changed, 41 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index bf1a24b..8433938 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -8,19 +8,15 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- *
*/
+
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/clkdev.h>
#include <linux/msm_ssbi.h>
+#include <linux/mfd/pm8921.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -28,9 +24,18 @@
#include <mach/board.h>
#include <mach/msm_iomap.h>
+#include <mach/irqs.h>
#include "devices.h"
+/* Macros assume PMIC GPIOs and MPPs start at 1 */
+#define PM8921_GPIO_BASE NR_GPIO_IRQS
+#define PM8921_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio - 1 + PM8921_GPIO_BASE)
+#define PM8921_MPP_BASE (PM8921_GPIO_BASE + NR_PM8921_GPIOS)
+#define PM8921_MPP_PM_TO_SYS(pm_gpio) (pm_gpio - 1 + PM8921_MPP_BASE)
+#define PM8921_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS)
+#define PM8921_MPP_IRQ_BASE (PM8921_IRQ_BASE + NR_GPIO_IRQS)
+
static void __init msm8960_map_io(void)
{
msm_map_msm8960_io();
@@ -65,12 +70,34 @@ static struct platform_device *sim_devices[] __initdata = {
static struct platform_device *rumi3_devices[] __initdata = {
&msm8960_device_uart_gsbi5,
+ &msm8960_device_ssbi_pm8921,
+};
+
+static struct pm8xxx_irq_platform_data pm8xxx_irq_pdata __devinitdata = {
+ .irq_base = PM8921_IRQ_BASE,
+ .devirq = MSM_GPIO_TO_INT(104),
+ .irq_trigger_flag = IRQF_TRIGGER_LOW,
+};
+
+static struct pm8xxx_gpio_platform_data pm8xxx_gpio_pdata __devinitdata = {
+ .gpio_base = PM8921_GPIO_PM_TO_SYS(1),
+};
+
+static struct pm8xxx_mpp_platform_data pm8xxx_mpp_pdata __devinitdata = {
+ .mpp_base = PM8921_MPP_PM_TO_SYS(1),
+};
+
+static struct pm8921_platform_data pm8921_platform_data __devinitdata = {
+ .irq_pdata = &pm8xxx_irq_pdata,
+ .gpio_pdata = &pm8xxx_gpio_pdata,
+ .mpp_pdata = &pm8xxx_mpp_pdata,
};
-static struct msm_ssbi_platform_data msm8960_ssbi_pm8921_pdata = {
- .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
- .slave = {
- .name = "pm8921-core",
+static struct msm_ssbi_platform_data msm8960_ssbi_pm8921_pdata __initdata = {
+ .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
+ .slave = {
+ .name = "pm8921-core",
+ .platform_data = &pm8921_platform_data,
},
};
diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h
index 81ab2a6..1bd0ee8 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8960.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8960.h
@@ -267,11 +267,10 @@
#define PM8921_SEC_IRQ_104 (GIC_SPI_START + 225)
#define PM8018_SEC_IRQ_107 (GIC_SPI_START + 226)
-/* For now, use the maximum number of interrupts until a pending GIC issue
- * is sorted out */
-#define NR_MSM_IRQS 1020
-#define NR_BOARD_IRQS 0
-#define NR_GPIO_IRQS 0
+#define NR_MSM_IRQS 256
+#define NR_GPIO_IRQS 151
+#define NR_PM8921_IRQS 256
+#define NR_BOARD_IRQS (NR_PM8921_IRQS)
#endif
--
1.7.1
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum
From: David Collins <[email protected]>
Add support for multi-purpose pins (MPPs) on Qualcomm PM8xxx
PMIC chips.
PM8xxx MPPs can be configured as digital or analog inputs or
outputs, current sinks, or buffers.
Change-Id: Iab39b2f7c2ba3f35ef6ac74d37ee7add8c70681f
Signed-off-by: David Collins <[email protected]>
---
drivers/mfd/Kconfig | 8 +
drivers/mfd/Makefile | 1 +
drivers/mfd/pm8921-core.c | 31 ++++
drivers/mfd/pm8xxx-mpp.c | 319 ++++++++++++++++++++++++++++++++++++++++
include/linux/mfd/pm8921.h | 4 +
include/linux/mfd/pm8xxx/mpp.h | 233 +++++++++++++++++++++++++++++
6 files changed, 596 insertions(+), 0 deletions(-)
create mode 100644 drivers/mfd/pm8xxx-mpp.c
create mode 100644 include/linux/mfd/pm8xxx/mpp.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 45fcc8a..33d119a 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -657,6 +657,14 @@ config MFD_PM8XXX_IRQ
This is required to use certain other PM 8xxx features, such as GPIO
and MPP.
+config MFD_PM8XXX_MPP
+ tristate "Support for Qualcomm PM8xxx MPP features"
+ depends on MFD_PM8XXX
+ default y if MFD_PM8XXX
+ help
+ This is the multi-purpose pin (MPP) driver for Qualcomm PM 8xxx PMIC
+ chips.
+
endif # MFD_SUPPORT
menu "Multimedia Capabilities Port drivers"
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 5fc9315..8891177 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -85,3 +85,4 @@ obj-$(CONFIG_MFD_WL1273_CORE) += wl1273-core.o
obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o
obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o
obj-$(CONFIG_MFD_PM8XXX_IRQ) += pm8xxx-irq.o
+obj-$(CONFIG_MFD_PM8XXX_MPP) += pm8xxx-mpp.o
diff --git a/drivers/mfd/pm8921-core.c b/drivers/mfd/pm8921-core.c
index 8d47626..b8e17eb 100644
--- a/drivers/mfd/pm8921-core.c
+++ b/drivers/mfd/pm8921-core.c
@@ -25,6 +25,8 @@
#define REG_HWREV 0x002 /* PMIC4 revision */
#define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */
+#define REG_MPP_BASE 0x050
+
struct pm8921 {
struct device *dev;
struct device *irq_dev;
@@ -101,6 +103,22 @@ static struct mfd_cell gpio_cell __devinitdata = {
.num_resources = ARRAY_SIZE(gpio_cell_resources),
};
+static const struct resource mpp_cell_resources[] __devinitconst = {
+ {
+ .start = PM8921_IRQ_BLOCK_BIT(PM8921_MPP_BLOCK_START, 0),
+ .end = PM8921_IRQ_BLOCK_BIT(PM8921_MPP_BLOCK_START, 0)
+ + NR_PM8921_MPPS - 1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct mfd_cell mpp_cell __devinitdata = {
+ .name = PM8XXX_MPP_DEV_NAME,
+ .id = -1,
+ .resources = mpp_cell_resources,
+ .num_resources = ARRAY_SIZE(mpp_cell_resources),
+};
+
static int __devinit pm8921_add_subdevices(const struct pm8921_platform_data
*pdata,
struct pm8921 *pmic,
@@ -136,6 +154,19 @@ static int __devinit pm8921_add_subdevices(const struct pm8921_platform_data
}
}
+ if (pdata->mpp_pdata) {
+ pdata->mpp_pdata->core_data.nmpps = NR_PM8921_MPPS;
+ pdata->mpp_pdata->core_data.base_addr = REG_MPP_BASE;
+ mpp_cell.platform_data = pdata->mpp_pdata;
+ mpp_cell.data_size = sizeof(struct pm8xxx_mpp_platform_data);
+ ret = mfd_add_devices(pmic->dev, 0, &mpp_cell, 1, NULL,
+ irq_base);
+ if (ret) {
+ pr_err("Failed to add mpp subdevice ret=%d\n", ret);
+ goto bail;
+ }
+ }
+
bail:
return ret;
}
diff --git a/drivers/mfd/pm8xxx-mpp.c b/drivers/mfd/pm8xxx-mpp.c
new file mode 100644
index 0000000..588ae5a
--- /dev/null
+++ b/drivers/mfd/pm8xxx-mpp.c
@@ -0,0 +1,319 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PM8XXX Multi-Purpose Pin (MPP) driver
+ *
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+#include <linux/mfd/pm8xxx/core.h>
+#include <linux/mfd/pm8xxx/mpp.h>
+
+/* MPP Type */
+#define PM8XXX_MPP_TYPE_MASK 0xE0
+#define PM8XXX_MPP_TYPE_SHIFT 5
+
+/* MPP Config Level */
+#define PM8XXX_MPP_CONFIG_LVL_MASK 0x1C
+#define PM8XXX_MPP_CONFIG_LVL_SHIFT 2
+
+/* MPP Config Control */
+#define PM8XXX_MPP_CONFIG_CTRL_MASK 0x03
+#define PM8XXX_MPP_CONFIG_CTRL_SHIFT 0
+
+struct pm8xxx_mpp_chip {
+ struct list_head link;
+ struct gpio_chip gpio_chip;
+ struct mutex pm_lock;
+ u8 *ctrl_reg;
+ int mpp_base;
+ int irq_base;
+ int nmpps;
+ u16 base_addr;
+};
+
+static LIST_HEAD(pm8xxx_mpp_chips);
+
+static int pm8xxx_mpp_write(struct pm8xxx_mpp_chip *mpp_chip, u16 offset,
+ u8 val, u8 mask)
+{
+ u8 reg;
+ int rc;
+
+ mutex_lock(&mpp_chip->pm_lock);
+
+ reg = (mpp_chip->ctrl_reg[offset] & ~mask) | (val & mask);
+ rc = pm8xxx_writeb(mpp_chip->gpio_chip.dev->parent,
+ mpp_chip->base_addr + offset, reg);
+ if (!rc)
+ mpp_chip->ctrl_reg[offset] = reg;
+
+ mutex_unlock(&mpp_chip->pm_lock);
+
+ return rc;
+}
+
+static int pm8xxx_mpp_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct pm8xxx_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+
+ return mpp_chip->irq_base + offset;
+}
+
+static int pm8xxx_mpp_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct pm8xxx_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ int rc;
+
+ if ((mpp_chip->ctrl_reg[offset] & PM8XXX_MPP_TYPE_MASK) >>
+ PM8XXX_MPP_TYPE_SHIFT == PM8XXX_MPP_TYPE_D_OUTPUT)
+ rc = mpp_chip->ctrl_reg[offset] & PM8XXX_MPP_CONFIG_CTRL_MASK;
+ else
+ rc = pm8xxx_read_irq_stat(mpp_chip->gpio_chip.dev->parent,
+ mpp_chip->irq_base + offset);
+
+ return rc;
+}
+
+static void pm8xxx_mpp_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+ struct pm8xxx_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ u8 reg = val ? PM8XXX_MPP_DOUT_CTRL_HIGH : PM8XXX_MPP_DOUT_CTRL_LOW;
+ int rc;
+
+ rc = pm8xxx_mpp_write(mpp_chip, offset, reg,
+ PM8XXX_MPP_CONFIG_CTRL_MASK);
+ if (rc)
+ pr_err("pm8xxx_mpp_write(): rc=%d\n", rc);
+}
+
+static int pm8xxx_mpp_dir_input(struct gpio_chip *chip, unsigned offset)
+{
+ struct pm8xxx_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ int rc = pm8xxx_mpp_write(mpp_chip, offset,
+ PM8XXX_MPP_TYPE_D_INPUT << PM8XXX_MPP_TYPE_SHIFT,
+ PM8XXX_MPP_TYPE_MASK);
+
+ if (rc)
+ pr_err("pm8xxx_mpp_write(): rc=%d\n", rc);
+ return rc;
+}
+
+static int pm8xxx_mpp_dir_output(struct gpio_chip *chip,
+ unsigned offset, int val)
+{
+ struct pm8xxx_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ u8 reg = (PM8XXX_MPP_TYPE_D_OUTPUT << PM8XXX_MPP_TYPE_SHIFT) |
+ (val & PM8XXX_MPP_CONFIG_CTRL_MASK);
+ u8 mask = PM8XXX_MPP_TYPE_MASK | PM8XXX_MPP_CONFIG_CTRL_MASK;
+ int rc = pm8xxx_mpp_write(mpp_chip, offset, reg, mask);
+
+ if (rc)
+ pr_err("pm8xxx_mpp_write(): rc=%d\n", rc);
+ return rc;
+}
+
+static void pm8xxx_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+{
+ static const char * const ctype[] = { "d_in", "d_out", "bi_dir", "a_in",
+ "a_out", "sink", "dtest_sink", "dtest_out" };
+ struct pm8xxx_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ u8 type, state;
+ const char *label;
+ int i;
+
+ for (i = 0; i < mpp_chip->nmpps; i++) {
+ label = gpiochip_is_requested(chip, i);
+ type = (mpp_chip->ctrl_reg[i] & PM8XXX_MPP_TYPE_MASK) >>
+ PM8XXX_MPP_TYPE_SHIFT;
+ state = pm8xxx_mpp_get(chip, i);
+ seq_printf(s, "gpio-%-3d (%-12.12s) %-10.10s"
+ " %s 0x%02x\n",
+ chip->base + i,
+ label ? label : "--",
+ ctype[type],
+ state ? "hi" : "lo",
+ mpp_chip->ctrl_reg[i]);
+ }
+}
+
+int pm8xxx_mpp_config(unsigned mpp, unsigned type, unsigned level,
+ unsigned control)
+{
+ struct pm8xxx_mpp_chip *mpp_chip;
+ int found = 0;
+ u8 config, mask;
+ int rc;
+
+ list_for_each_entry(mpp_chip, &pm8xxx_mpp_chips, link) {
+ if (mpp >= mpp_chip->mpp_base
+ && mpp < mpp_chip->mpp_base + mpp_chip->nmpps) {
+ found = 1;
+ break;
+ }
+ }
+ if (!found) {
+ pr_err("called on mpp %d not handled by any pmic\n", mpp);
+ return -EINVAL;
+ }
+
+ mask = PM8XXX_MPP_TYPE_MASK | PM8XXX_MPP_CONFIG_LVL_MASK |
+ PM8XXX_MPP_CONFIG_CTRL_MASK;
+ config = (type << PM8XXX_MPP_TYPE_SHIFT) & PM8XXX_MPP_TYPE_MASK;
+ config |= (level << PM8XXX_MPP_CONFIG_LVL_SHIFT) &
+ PM8XXX_MPP_CONFIG_LVL_MASK;
+ config |= control & PM8XXX_MPP_CONFIG_CTRL_MASK;
+
+ rc = pm8xxx_mpp_write(mpp_chip, mpp - mpp_chip->mpp_base, config, mask);
+
+ if (rc)
+ pr_err("pm8xxx_mpp_write(): rc=%d\n", rc);
+
+ return rc;
+}
+EXPORT_SYMBOL(pm8xxx_mpp_config);
+
+static int __devinit pm8xxx_mpp_reg_init(struct pm8xxx_mpp_chip *mpp_chip)
+{
+ int rc, i;
+
+ for (i = 0; i < mpp_chip->nmpps; i++) {
+ rc = pm8xxx_readb(mpp_chip->gpio_chip.dev->parent,
+ mpp_chip->base_addr + i,
+ &mpp_chip->ctrl_reg[i]);
+ if (rc)
+ goto bail;
+ }
+
+bail:
+ return rc;
+}
+
+static int __devinit pm8xxx_mpp_probe(struct platform_device *pdev)
+{
+ int rc;
+ const struct pm8xxx_mpp_platform_data *pdata = pdev->dev.platform_data;
+ struct pm8xxx_mpp_chip *mpp_chip;
+
+ if (!pdata) {
+ pr_err("missing platform data\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ mpp_chip = kzalloc(sizeof(struct pm8xxx_mpp_chip), GFP_KERNEL);
+ if (!mpp_chip) {
+ pr_err("Cannot allocate %d bytes\n",
+ sizeof(struct pm8xxx_mpp_chip));
+ rc = -ENOMEM;
+ goto out;
+ }
+
+ mpp_chip->ctrl_reg = kzalloc(pdata->core_data.nmpps, GFP_KERNEL);
+ if (!mpp_chip->ctrl_reg) {
+ pr_err("Cannot allocate %d bytes\n", pdata->core_data.nmpps);
+ rc = -ENOMEM;
+ goto free_mpp_chip;
+ }
+
+ mutex_init(&mpp_chip->pm_lock);
+
+ mpp_chip->gpio_chip.label = PM8XXX_MPP_DEV_NAME;
+ mpp_chip->gpio_chip.direction_input = pm8xxx_mpp_dir_input;
+ mpp_chip->gpio_chip.direction_output = pm8xxx_mpp_dir_output;
+ mpp_chip->gpio_chip.to_irq = pm8xxx_mpp_to_irq;
+ mpp_chip->gpio_chip.get = pm8xxx_mpp_get;
+ mpp_chip->gpio_chip.set = pm8xxx_mpp_set;
+ mpp_chip->gpio_chip.dbg_show = pm8xxx_mpp_dbg_show;
+ mpp_chip->gpio_chip.ngpio = pdata->core_data.nmpps;
+ mpp_chip->gpio_chip.can_sleep = 1;
+ mpp_chip->gpio_chip.dev = &pdev->dev;
+ mpp_chip->gpio_chip.base = pdata->mpp_base;
+ mpp_chip->irq_base = platform_get_irq(pdev, 0);
+ mpp_chip->mpp_base = pdata->mpp_base;
+ mpp_chip->base_addr = pdata->core_data.base_addr;
+ mpp_chip->nmpps = pdata->core_data.nmpps;
+
+ list_add(&mpp_chip->link, &pm8xxx_mpp_chips);
+ platform_set_drvdata(pdev, mpp_chip);
+
+ rc = gpiochip_add(&mpp_chip->gpio_chip);
+ if (rc) {
+ pr_err("gpiochip_add failed, rc=%d\n", rc);
+ goto reset_drvdata;
+ }
+
+ rc = pm8xxx_mpp_reg_init(mpp_chip);
+ if (rc) {
+ pr_err("failed to read MPP ctrl registers, rc=%d\n", rc);
+ goto remove_chip;
+ }
+
+ return 0;
+
+remove_chip:
+ if (gpiochip_remove(&mpp_chip->gpio_chip))
+ pr_err("failed to remove gpio chip\n");
+reset_drvdata:
+ platform_set_drvdata(pdev, NULL);
+ mutex_destroy(&mpp_chip->pm_lock);
+free_mpp_chip:
+ kfree(mpp_chip);
+out:
+ return rc;
+}
+
+static int __devexit pm8xxx_mpp_remove(struct platform_device *pdev)
+{
+ struct pm8xxx_mpp_chip *mpp_chip = platform_get_drvdata(pdev);
+
+ platform_set_drvdata(pdev, NULL);
+ if (gpiochip_remove(&mpp_chip->gpio_chip))
+ pr_err("failed to remove gpio chip\n");
+ mutex_destroy(&mpp_chip->pm_lock);
+ kfree(mpp_chip->ctrl_reg);
+ kfree(mpp_chip);
+
+ return 0;
+}
+
+static struct platform_driver pm8xxx_mpp_driver = {
+ .probe = pm8xxx_mpp_probe,
+ .remove = __devexit_p(pm8xxx_mpp_remove),
+ .driver = {
+ .name = PM8XXX_MPP_DEV_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init pm8xxx_mpp_init(void)
+{
+ return platform_driver_register(&pm8xxx_mpp_driver);
+}
+
+static void __exit pm8xxx_mpp_exit(void)
+{
+ platform_driver_unregister(&pm8xxx_mpp_driver);
+}
+
+subsys_initcall(pm8xxx_mpp_init);
+module_exit(pm8xxx_mpp_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PM8XXX MPP driver");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("platform:" PM8XXX_MPP_DEV_NAME);
diff --git a/include/linux/mfd/pm8921.h b/include/linux/mfd/pm8921.h
index 691b1d3..27fff3b 100644
--- a/include/linux/mfd/pm8921.h
+++ b/include/linux/mfd/pm8921.h
@@ -20,11 +20,14 @@
#include <linux/device.h>
#include <linux/mfd/pm8xxx/irq.h>
#include <linux/mfd/pm8xxx/gpio.h>
+#include <linux/mfd/pm8xxx/mpp.h>
#define NR_PM8921_IRQS 256
#define NR_PM8921_GPIOS 44
+#define NR_PM8921_MPPS 12
+
#define PM8921_GPIO_BLOCK_START 24
#define PM8921_MPP_BLOCK_START 16
#define PM8921_IRQ_BLOCK_BIT(block, bit) ((block) * 8 + (bit))
@@ -39,6 +42,7 @@ struct pm8921_platform_data {
int irq_base;
struct pm8xxx_irq_platform_data *irq_pdata;
struct pm8xxx_gpio_platform_data *gpio_pdata;
+ struct pm8xxx_mpp_platform_data *mpp_pdata;
};
#endif
diff --git a/include/linux/mfd/pm8xxx/mpp.h b/include/linux/mfd/pm8xxx/mpp.h
new file mode 100644
index 0000000..c779760
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/mpp.h
@@ -0,0 +1,233 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PM8XXX_MPP_H
+#define __PM8XXX_MPP_H
+
+#include <linux/errno.h>
+
+#define PM8XXX_MPP_DEV_NAME "pm8xxx-mpp"
+
+struct pm8xxx_mpp_core_data {
+ int base_addr;
+ int nmpps;
+};
+
+struct pm8xxx_mpp_platform_data {
+ struct pm8xxx_mpp_core_data core_data;
+ int mpp_base;
+};
+
+/* API */
+#if defined(CONFIG_MFD_PM8XXX_MPP) || defined(CONFIG_MFD_PM8XXX_MPP_MODULE)
+
+/**
+ * pm8xxx_mpp_config() - configure control options of a multi-purpose pin (MPP)
+ * @mpp: global GPIO number corresponding to the MPP
+ * @type: MPP type which determines the overall MPP function (i.e. digital
+ * in/out/bi, analog in/out, current sink, or test). It should be
+ * set to the value of one of PM8XXX_MPP_TYPE_D_*.
+ * @level: meaning depends upon MPP type specified
+ * @control: meaning depends upon MPP type specified
+ * Context: can sleep
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ *
+ * Usage of level argument:
+ * 1. type = PM8XXX_MPP_TYPE_D_INPUT, PM8XXX_MPP_TYPE_D_OUTPUT,
+ * PM8XXX_MPP_TYPE_D_BI_DIR, or PM8XXX_MPP_TYPE_DTEST_OUTPUT -
+ *
+ * level specifies that digital logic level to use for the MPP. It should
+ * be set to the value of one of PM8XXX_MPP_DIG_LEVEL_*. Actual regulator
+ * connections for these level choices are PMIC chip specific.
+ *
+ * 2. type = PM8XXX_MPP_TYPE_A_INPUT -
+ *
+ * level specifies where in the PMIC chip the analog input value should
+ * be routed to. It should be set to the value of one of
+ * PM8XXX_MPP_AIN_AMUX_*.
+ *
+ * 3. type = PM8XXX_MPP_TYPE_A_OUTPUT -
+ *
+ * level specifies the output analog voltage reference level. It should
+ * be set to the value of one of PM8XXX_MPP_AOUT_LVL_*.
+ *
+ * 4. type = PM8XXX_MPP_TYPE_SINK or PM8XXX_MPP_TYPE_DTEST_SINK -
+ *
+ * level specifies the output current level. It should be set to the value
+ * of one of PM8XXX_MPP_CS_OUT_*.
+ *
+ * Usage of control argument:
+ * 1. type = PM8XXX_MPP_TYPE_D_INPUT -
+ *
+ * control specifies how the digital input should be routed in the chip.
+ * It should be set to the value of one of PM8XXX_MPP_DIN_TO_*.
+ *
+ * 2. type = PM8XXX_MPP_TYPE_D_OUTPUT -
+ *
+ * control specifies the digital output value. It should be set to the
+ * value of one of PM8XXX_MPP_DOUT_CTRL_*.
+ *
+ * 3. type = PM8XXX_MPP_TYPE_D_BI_DIR -
+ *
+ * control specifies the pullup resistor value. It should be set to the
+ * value of one of PM8XXX_MPP_BI_PULLUP_*.
+ *
+ * 4. type = PM8XXX_MPP_TYPE_A_INPUT -
+ *
+ * control is unused; a value of 0 is sufficient.
+ *
+ * 5. type = PM8XXX_MPP_TYPE_A_OUTPUT -
+ *
+ * control specifies if analog output is enabled. It should be set to the
+ * value of one of PM8XXX_MPP_AOUT_CTRL_*.
+ *
+ * 6. type = PM8XXX_MPP_TYPE_SINK -
+ *
+ * control specifies if current sinking is enabled. It should be set to
+ * the value of one of PM8XXX_MPP_CS_CTRL_*.
+ *
+ * 7. type = PM8XXX_MPP_TYPE_DTEST_SINK -
+ *
+ * control specifies if current sinking is enabled. It should be set to
+ * the value of one of PM8XXX_MPP_DTEST_CS_CTRL_*.
+ *
+ * 8. type = PM8XXX_MPP_TYPE_DTEST_OUTPUT -
+ *
+ * control specifies which DTEST bus value to output. It should be set to
+ * the value of one of PM8XXX_MPP_DTEST_*.
+ */
+int pm8xxx_mpp_config(unsigned mpp, unsigned type, unsigned level,
+ unsigned control);
+
+#else
+
+static inline int pm8xxx_mpp_config(unsigned mpp, unsigned type, unsigned level,
+ unsigned control)
+{
+ return -ENXIO;
+}
+
+#endif
+
+/* MPP Type: type */
+#define PM8XXX_MPP_TYPE_D_INPUT 0
+#define PM8XXX_MPP_TYPE_D_OUTPUT 1
+#define PM8XXX_MPP_TYPE_D_BI_DIR 2
+#define PM8XXX_MPP_TYPE_A_INPUT 3
+#define PM8XXX_MPP_TYPE_A_OUTPUT 4
+#define PM8XXX_MPP_TYPE_SINK 5
+#define PM8XXX_MPP_TYPE_DTEST_SINK 6
+#define PM8XXX_MPP_TYPE_DTEST_OUTPUT 7
+
+/* Digital Input/Output: level */
+#define PM8XXX_MPP_DIG_LEVEL_VIO_0 0
+#define PM8XXX_MPP_DIG_LEVEL_VIO_1 1
+#define PM8XXX_MPP_DIG_LEVEL_VIO_2 2
+#define PM8XXX_MPP_DIG_LEVEL_VIO_3 3
+#define PM8XXX_MPP_DIG_LEVEL_VIO_4 4
+#define PM8XXX_MPP_DIG_LEVEL_VIO_5 5
+#define PM8XXX_MPP_DIG_LEVEL_VIO_6 6
+#define PM8XXX_MPP_DIG_LEVEL_VIO_7 7
+
+/* Digital Input/Output: level [PM8058] */
+#define PM8058_MPP_DIG_LEVEL_VPH 0
+#define PM8058_MPP_DIG_LEVEL_S3 1
+#define PM8058_MPP_DIG_LEVEL_L2 2
+#define PM8058_MPP_DIG_LEVEL_L3 3
+
+/* Digital Input/Output: level [PM8901] */
+#define PM8901_MPP_DIG_LEVEL_MSMIO 0
+#define PM8901_MPP_DIG_LEVEL_DIG 1
+#define PM8901_MPP_DIG_LEVEL_L5 2
+#define PM8901_MPP_DIG_LEVEL_S4 3
+#define PM8901_MPP_DIG_LEVEL_VPH 4
+
+/* Digital Input/Output: level [PM8921] */
+#define PM8921_MPP_DIG_LEVEL_S4 1
+#define PM8921_MPP_DIG_LEVEL_L15 3
+#define PM8921_MPP_DIG_LEVEL_L17 4
+#define PM8921_MPP_DIG_LEVEL_VPH 7
+
+/* Digital Input: control */
+#define PM8XXX_MPP_DIN_TO_INT 0
+#define PM8XXX_MPP_DIN_TO_DBUS1 1
+#define PM8XXX_MPP_DIN_TO_DBUS2 2
+#define PM8XXX_MPP_DIN_TO_DBUS3 3
+
+/* Digital Output: control */
+#define PM8XXX_MPP_DOUT_CTRL_LOW 0
+#define PM8XXX_MPP_DOUT_CTRL_HIGH 1
+#define PM8XXX_MPP_DOUT_CTRL_MPP 2
+#define PM8XXX_MPP_DOUT_CTRL_INV_MPP 3
+
+/* Bidirectional: control */
+#define PM8XXX_MPP_BI_PULLUP_1KOHM 0
+#define PM8XXX_MPP_BI_PULLUP_OPEN 1
+#define PM8XXX_MPP_BI_PULLUP_10KOHM 2
+#define PM8XXX_MPP_BI_PULLUP_30KOHM 3
+
+/* Analog Input: level */
+#define PM8XXX_MPP_AIN_AMUX_CH5 0
+#define PM8XXX_MPP_AIN_AMUX_CH6 1
+#define PM8XXX_MPP_AIN_AMUX_CH7 2
+#define PM8XXX_MPP_AIN_AMUX_CH8 3
+#define PM8XXX_MPP_AIN_AMUX_CH9 4
+#define PM8XXX_MPP_AIN_AMUX_ABUS1 5
+#define PM8XXX_MPP_AIN_AMUX_ABUS2 6
+#define PM8XXX_MPP_AIN_AMUX_ABUS3 7
+
+/* Analog Output: level */
+#define PM8XXX_MPP_AOUT_LVL_1V25 0
+#define PM8XXX_MPP_AOUT_LVL_1V25_2 1
+#define PM8XXX_MPP_AOUT_LVL_0V625 2
+#define PM8XXX_MPP_AOUT_LVL_0V3125 3
+#define PM8XXX_MPP_AOUT_LVL_MPP 4
+#define PM8XXX_MPP_AOUT_LVL_ABUS1 5
+#define PM8XXX_MPP_AOUT_LVL_ABUS2 6
+#define PM8XXX_MPP_AOUT_LVL_ABUS3 7
+
+/* Analog Output: control */
+#define PM8XXX_MPP_AOUT_CTRL_DISABLE 0
+#define PM8XXX_MPP_AOUT_CTRL_ENABLE 1
+#define PM8XXX_MPP_AOUT_CTRL_MPP_HIGH_EN 2
+#define PM8XXX_MPP_AOUT_CTRL_MPP_LOW_EN 3
+
+/* Current Sink: level */
+#define PM8XXX_MPP_CS_OUT_5MA 0
+#define PM8XXX_MPP_CS_OUT_10MA 1
+#define PM8XXX_MPP_CS_OUT_15MA 2
+#define PM8XXX_MPP_CS_OUT_20MA 3
+#define PM8XXX_MPP_CS_OUT_25MA 4
+#define PM8XXX_MPP_CS_OUT_30MA 5
+#define PM8XXX_MPP_CS_OUT_35MA 6
+#define PM8XXX_MPP_CS_OUT_40MA 7
+
+/* Current Sink: control */
+#define PM8XXX_MPP_CS_CTRL_DISABLE 0
+#define PM8XXX_MPP_CS_CTRL_ENABLE 1
+#define PM8XXX_MPP_CS_CTRL_MPP_HIGH_EN 2
+#define PM8XXX_MPP_CS_CTRL_MPP_LOW_EN 3
+
+/* DTEST Current Sink: control */
+#define PM8XXX_MPP_DTEST_CS_CTRL_EN1 0
+#define PM8XXX_MPP_DTEST_CS_CTRL_EN2 1
+#define PM8XXX_MPP_DTEST_CS_CTRL_EN3 2
+#define PM8XXX_MPP_DTEST_CS_CTRL_EN4 3
+
+/* DTEST Digital Output: control */
+#define PM8XXX_MPP_DTEST_DBUS1 0
+#define PM8XXX_MPP_DTEST_DBUS2 1
+#define PM8XXX_MPP_DTEST_DBUS3 2
+#define PM8XXX_MPP_DTEST_DBUS4 3
+
+#endif
--
1.7.1
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum
From: Abhijeet Dharmapurikar <[email protected]>
Add support for the irq controller in Qualcomm 8xxx pmic. The 8xxx
interrupt controller provides control for gpio and mpp configured as
interrupts in addition to other subdevice interrupts. The interrupt
controller also provides a way to read the real time status of an
interrupt. This real time status is the only way one can get the
input values of gpio and mpp lines.
Change-Id: Ibb23878cd382af9a750d62ab49482f5dc72e3714
Signed-off-by: Abhijeet Dharmapurikar <[email protected]>
---
drivers/mfd/Kconfig | 10 +
drivers/mfd/Makefile | 1 +
drivers/mfd/pm8921-core.c | 70 ++++-
drivers/mfd/pm8xxx-irq.c | 599 +++++++++++++++++++++++++++++++++++++++
include/linux/mfd/pm8921.h | 6 +-
include/linux/mfd/pm8xxx/core.h | 9 +
include/linux/mfd/pm8xxx/irq.h | 62 ++++
7 files changed, 748 insertions(+), 9 deletions(-)
create mode 100644 drivers/mfd/pm8xxx-irq.c
create mode 100644 include/linux/mfd/pm8xxx/irq.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 0a1bc22..45fcc8a 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -647,6 +647,16 @@ config MFD_PM8921_CORE
Say M here if you want to include support for PM8921 chip as a module.
This will build a module called "pm8921-core.ko".
+config MFD_PM8XXX_IRQ
+ bool "Support for Qualcomm PM8xxx IRQ features"
+ depends on MFD_PM8XXX
+ default y if MFD_PM8XXX
+ help
+ This is the IRQ driver for Qualcomm PM 8xxx PMIC chips.
+
+ This is required to use certain other PM 8xxx features, such as GPIO
+ and MPP.
+
endif # MFD_SUPPORT
menu "Multimedia Capabilities Port drivers"
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index ec158da..5fc9315 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -84,3 +84,4 @@ obj-$(CONFIG_MFD_VX855) += vx855.o
obj-$(CONFIG_MFD_WL1273_CORE) += wl1273-core.o
obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o
obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o
+obj-$(CONFIG_MFD_PM8XXX_IRQ) += pm8xxx-irq.o
diff --git a/drivers/mfd/pm8921-core.c b/drivers/mfd/pm8921-core.c
index 46ab2fc..2102e8b 100644
--- a/drivers/mfd/pm8921-core.c
+++ b/drivers/mfd/pm8921-core.c
@@ -19,12 +19,14 @@
#include <linux/mfd/core.h>
#include <linux/mfd/pm8921.h>
#include <linux/mfd/pm8xxx/core.h>
+#include <linux/mfd/pm8xxx/irq.h>
#define REG_HWREV 0x002 /* PMIC4 revision */
#define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */
struct pm8921 {
- struct device *dev;
+ struct device *dev;
+ struct device *irq_dev;
};
static int pm8921_readb(const struct device *dev, u16 addr, u8 *val)
@@ -61,26 +63,65 @@ static int pm8921_write_buf(const struct device *dev, u16 addr, u8 *buf,
return msm_ssbi_write(pmic->dev->parent, addr, buf, cnt);
}
+static int pm8921_read_irq_stat(const struct device *dev, int irq)
+{
+ const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
+ const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
+
+ return pm8xxx_get_irq_stat(pmic->irq_dev, irq);
+}
+
static struct pm8xxx_drvdata pm8921_drvdata = {
- .pmic_readb = pm8921_readb,
- .pmic_writeb = pm8921_writeb,
- .pmic_read_buf = pm8921_read_buf,
- .pmic_write_buf = pm8921_write_buf,
+ .pmic_readb = pm8921_readb,
+ .pmic_writeb = pm8921_writeb,
+ .pmic_read_buf = pm8921_read_buf,
+ .pmic_write_buf = pm8921_write_buf,
+ .pmic_read_irq_stat = pm8921_read_irq_stat,
+};
+
+static struct __devinitdata mfd_cell irq_cell = {
+ .name = PM8XXX_IRQ_DEV_NAME,
+ .id = -1,
};
static int __devinit pm8921_add_subdevices(const struct pm8921_platform_data
*pdata,
- struct pm8921 *pmic)
+ struct pm8921 *pmic,
+ u32 rev)
{
+ int ret = 0;
+ int irq_base = 0;
+
+ if (pdata->irq_pdata) {
+ pdata->irq_pdata->irq_cdata.nirqs = NR_PM8921_IRQS;
+ pdata->irq_pdata->irq_cdata.rev = rev;
+ irq_cell.platform_data = pdata->irq_pdata;
+ irq_cell.data_size = sizeof(struct pm8xxx_irq_platform_data);
+ irq_base = pdata->irq_pdata->irq_base;
+ ret = mfd_add_devices(pmic->dev, 0, &irq_cell, 1,
+ NULL, 0);
+ if (ret < 0) {
+ pr_err("Failed to add irq_subdevice ret=%d\n", ret);
+ return ret;
+ }
+ }
+
return 0;
}
+static int __devinit match_irq_dev(struct device *dev, void *data)
+{
+ return !strncmp(PM8XXX_IRQ_DEV_NAME, dev_name(dev),
+ PM8XXX_IRQ_DEV_NAME_LEN);
+}
+
static int __devinit pm8921_probe(struct platform_device *pdev)
{
const struct pm8921_platform_data *pdata = pdev->dev.platform_data;
struct pm8921 *pmic;
int rc;
u8 val;
+ u32 rev;
if (!pdata) {
pr_err("missing platform data\n");
@@ -99,7 +140,8 @@ static int __devinit pm8921_probe(struct platform_device *pdev)
pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
goto err_read_rev;
}
- pr_info("PMIC revision: %02X\n", val);
+ pr_info("PMIC revision 1: %02X\n", val);
+ rev = val;
/* Read PMIC chip revision 2 */
rc = msm_ssbi_read(pdev->dev.parent, REG_HWREV_2, &val, sizeof(val));
@@ -109,20 +151,32 @@ static int __devinit pm8921_probe(struct platform_device *pdev)
goto err_read_rev;
}
pr_info("PMIC revision 2: %02X\n", val);
+ rev |= val << BITS_PER_BYTE;
pmic->dev = &pdev->dev;
pm8921_drvdata.pm_chip_data = pmic;
platform_set_drvdata(pdev, &pm8921_drvdata);
- rc = pm8921_add_subdevices(pdata, pmic);
+ rc = pm8921_add_subdevices(pdata, pmic, rev);
if (rc) {
pr_err("Cannot add subdevices rc=%d\n", rc);
goto err;
}
+ /*
+ * Locate the irq device in the mfd subdevices and save a reference
+ * to it. This is becuase on pm8xxx gpio status is read through the
+ * interrupt blocks
+ */
+ pmic->irq_dev = device_find_child(pmic->dev, NULL,
+ match_irq_dev);
+ /* gpio might not work if no irq device is found */
+ WARN_ON(pmic->irq_dev == NULL);
+
return 0;
err:
+ mfd_remove_devices(pmic->dev);
platform_set_drvdata(pdev, NULL);
err_read_rev:
kfree(pmic);
diff --git a/drivers/mfd/pm8xxx-irq.c b/drivers/mfd/pm8xxx-irq.c
new file mode 100644
index 0000000..b555787
--- /dev/null
+++ b/drivers/mfd/pm8xxx-irq.c
@@ -0,0 +1,599 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/mfd/pm8xxx/core.h>
+#include <linux/mfd/pm8xxx/irq.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/ratelimit.h>
+
+/* PMIC8xxx IRQ */
+
+#define SSBI_REG_ADDR_IRQ_BASE 0x1BB
+
+#define SSBI_REG_ADDR_IRQ_ROOT (SSBI_REG_ADDR_IRQ_BASE + 0)
+#define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1)
+#define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2)
+#define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3)
+#define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4)
+#define SSBI_REG_ADDR_IRQ_BLK_SEL (SSBI_REG_ADDR_IRQ_BASE + 5)
+#define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6)
+#define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7)
+#define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8)
+
+#define PM_IRQF_LVL_SEL 0x01 /* level select */
+#define PM_IRQF_MASK_FE 0x02 /* mask falling edge */
+#define PM_IRQF_MASK_RE 0x04 /* mask rising edge */
+#define PM_IRQF_CLR 0x08 /* clear interrupt */
+#define PM_IRQF_BITS_MASK 0x70
+#define PM_IRQF_BITS_SHIFT 4
+#define PM_IRQF_WRITE 0x80
+
+#define PM_IRQF_MASK_ALL (PM_IRQF_MASK_FE | \
+ PM_IRQF_MASK_RE)
+#define PM_IRQF_W_C_M (PM_IRQF_WRITE | \
+ PM_IRQF_CLR | \
+ PM_IRQF_MASK_ALL)
+
+struct pm_irq_chip {
+ struct list_head link;
+ struct device *dev;
+ spinlock_t pm_irq_lock;
+ u8 *irqs_allowed;
+ u16 *irqs_to_handle;
+ u8 *config;
+ unsigned long *wake_enable;
+ unsigned int devirq;
+ unsigned int count_wakeable;
+ unsigned int irq_base;
+ unsigned int num_irqs;
+ unsigned int num_blocks;
+ unsigned int num_masters;
+};
+
+static LIST_HEAD(pm_irq_chips);
+
+/* Helper Functions */
+static DEFINE_RATELIMIT_STATE(pm8xxx_irq_ratelimit, 60 * HZ, 10);
+
+static inline int pm8xxx_can_print(void)
+{
+ return __ratelimit(&pm8xxx_irq_ratelimit);
+}
+
+static int
+pm8xxx_read_root(const struct pm_irq_chip *chip, u8 *rp)
+{
+ return pm8xxx_readb(chip->dev->parent, SSBI_REG_ADDR_IRQ_ROOT, rp);
+}
+
+static int
+pm8xxx_read_master(const struct pm_irq_chip *chip, u8 m, u8 *bp)
+{
+ return pm8xxx_readb(chip->dev->parent,
+ SSBI_REG_ADDR_IRQ_M_STATUS1 + m, bp);
+}
+
+static int
+pm8xxx_read_block(const struct pm_irq_chip *chip, u8 bp, u8 *ip)
+{
+ int rc;
+
+ rc = pm8xxx_writeb(chip->dev->parent,
+ SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
+ if (rc) {
+ pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
+ goto bail_out;
+ }
+
+ rc = pm8xxx_readb(chip->dev->parent,
+ SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
+ if (rc)
+ pr_err("Failed Reading Status rc=%d\n", rc);
+bail_out:
+ return rc;
+}
+
+static int
+pm8xxx_config_irq(const struct pm_irq_chip *chip, u8 bp, u8 cp)
+{
+ int rc;
+
+ rc = pm8xxx_writeb(chip->dev->parent,
+ SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
+ if (rc) {
+ pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
+ goto bail_out;
+ }
+
+ rc = pm8xxx_writeb(chip->dev->parent,
+ SSBI_REG_ADDR_IRQ_CONFIG, cp);
+ if (rc)
+ pr_err("Failed Configuring IRQ rc=%d\n", rc);
+bail_out:
+ return rc;
+}
+
+static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip,
+ int block, int *handled)
+{
+ int ret = 0;
+ u8 bits, config;
+ int pmirq, irq, k;
+
+ spin_lock(&chip->pm_irq_lock);
+ ret = pm8xxx_read_block(chip, block, &bits);
+ if (ret)
+ goto out;
+ if (!bits) {
+ if (pm8xxx_can_print())
+ pr_err("block bit set in master but no irqs: %d",
+ block);
+ goto out;
+ }
+
+ /* Check IRQ bits */
+ for (k = 0; k < 8; k++) {
+ if (bits & (1 << k)) {
+ pmirq = block * 8 + k;
+ irq = pmirq + chip->irq_base;
+ /* Check spurious interrupts */
+ if (((1 << k) & chip->irqs_allowed[block])) {
+ /* Found one */
+ chip->irqs_to_handle[*handled] = irq;
+ (*handled)++;
+ } else { /* Clear and mask wrong one */
+ config = PM_IRQF_W_C_M |
+ (k << PM_IRQF_BITS_SHIFT);
+
+ pm8xxx_config_irq(chip,
+ block, config);
+
+ if (pm8xxx_can_print())
+ pr_err("Spurious IRQ: %d "
+ "[block, bit]="
+ "[%d, %d]\n",
+ irq, block, k);
+ }
+ }
+ }
+out:
+ spin_unlock(&chip->pm_irq_lock);
+ return ret;
+}
+
+static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip,
+ int master, int *handled)
+{
+ int ret = 0;
+ u8 blockbits;
+ int block_number, j;
+
+ ret = pm8xxx_read_master(chip, master, &blockbits);
+ if (ret) {
+ pr_err("Failed to read master %d ret=%d\n", master, ret);
+ return ret;
+ }
+ if (!blockbits) {
+ if (pm8xxx_can_print())
+ pr_err("master bit set in root but no blocks: %d",
+ master);
+ return 0;
+ }
+
+ for (j = 0; j < 8; j++)
+ if (blockbits & (1 << j)) {
+ block_number = master * 8 + j; /* block # */
+ ret |= pm8xxx_irq_block_handler(chip, block_number,
+ handled);
+ }
+ return ret;
+}
+
+static void pm8xxx_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+ struct pm_irq_chip *chip = get_irq_data(irq);
+ int i, ret;
+ u8 root;
+ int masters = 0, handled = 0;
+
+ ret = pm8xxx_read_root(chip, &root);
+ if (ret) {
+ pr_err("Can't read root status ret=%d\n", ret);
+ return;
+ }
+
+ /* on pm8xxx series masters start from bit 1 of the root */
+ masters = root >> 1;
+
+ /* Read allowed masters for blocks. */
+ for (i = 0; i < chip->num_masters; i++)
+ if (masters & (1 << i))
+ pm8xxx_irq_master_handler(chip, i, &handled);
+
+ for (i = 0; i < handled; i++)
+ generic_handle_irq(chip->irqs_to_handle[i]);
+
+ desc->chip->ack(irq);
+
+}
+
+static void pm8xxx_irq_ack(unsigned int irq)
+{
+ const struct pm_irq_chip *chip = get_irq_chip_data(irq);
+ unsigned int pmirq = irq - chip->irq_base;
+ u8 block, config;
+
+ block = pmirq / 8;
+
+ config = PM_IRQF_WRITE | chip->config[pmirq] | PM_IRQF_CLR;
+ /* Keep the mask */
+ if (!(chip->irqs_allowed[block] & (1 << (pmirq % 8))))
+ config |= PM_IRQF_MASK_FE | PM_IRQF_MASK_RE;
+ pm8xxx_config_irq(chip, block, config);
+
+}
+
+static void pm8xxx_irq_mask(unsigned int irq)
+{
+ struct pm_irq_chip *chip = get_irq_chip_data(irq);
+ unsigned int pmirq = irq - chip->irq_base;
+ int master, irq_bit;
+ u8 block, config;
+
+ block = pmirq / 8;
+ master = block / 8;
+ irq_bit = pmirq % 8;
+
+ chip->irqs_allowed[block] &= ~(1 << irq_bit);
+
+ config = PM_IRQF_WRITE | chip->config[pmirq] |
+ PM_IRQF_MASK_FE | PM_IRQF_MASK_RE;
+ pm8xxx_config_irq(chip, block, config);
+}
+
+static void pm8xxx_irq_unmask(unsigned int irq)
+{
+ struct pm_irq_chip *chip = get_irq_chip_data(irq);
+ unsigned int pmirq = irq - chip->irq_base;
+ int master, irq_bit;
+ u8 block, config, old_irqs_allowed;
+
+ block = pmirq / 8;
+ master = block / 8;
+ irq_bit = pmirq % 8;
+
+ old_irqs_allowed = chip->irqs_allowed[block];
+ chip->irqs_allowed[block] |= 1 << irq_bit;
+
+ config = PM_IRQF_WRITE | chip->config[pmirq];
+ pm8xxx_config_irq(chip, block, config);
+}
+
+static int pm8xxx_irq_set_type(unsigned int irq, unsigned int flow_type)
+{
+ struct pm_irq_chip *chip = get_irq_chip_data(irq);
+ unsigned int pmirq = irq - chip->irq_base;
+ int master, irq_bit;
+ u8 block, config;
+
+ block = pmirq / 8;
+ master = block / 8;
+ irq_bit = pmirq % 8;
+
+ chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT) |
+ PM_IRQF_MASK_RE | PM_IRQF_MASK_FE;
+ if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
+ if (flow_type & IRQF_TRIGGER_RISING)
+ chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
+ if (flow_type & IRQF_TRIGGER_FALLING)
+ chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
+ } else {
+ chip->config[pmirq] |= PM_IRQF_LVL_SEL;
+
+ if (flow_type & IRQF_TRIGGER_HIGH)
+ chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
+ else
+ chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
+ }
+
+ config = PM_IRQF_WRITE
+ | chip->config[pmirq] | PM_IRQF_CLR;
+ return pm8xxx_config_irq(chip, block, config);
+}
+
+static int pm8xxx_irq_set_wake(unsigned int irq, unsigned int on)
+{
+ struct pm_irq_chip *chip = get_irq_chip_data(irq);
+ unsigned int pmirq = irq - chip->irq_base;
+
+ if (on) {
+ set_bit(pmirq, chip->wake_enable);
+ chip->count_wakeable++;
+ } else {
+ clear_bit(pmirq, chip->wake_enable);
+ chip->count_wakeable--;
+ }
+
+ return 0;
+}
+
+static struct irq_chip pm8xxx_irq_chip = {
+ .name = "pm8xxx",
+ .ack = pm8xxx_irq_ack,
+ .mask = pm8xxx_irq_mask,
+ .unmask = pm8xxx_irq_unmask,
+ .set_type = pm8xxx_irq_set_type,
+ .set_wake = pm8xxx_irq_set_wake,
+};
+
+int pm8xxx_get_irq_stat(const struct device *dev, int irq)
+{
+ struct pm_irq_chip *chip = dev_get_drvdata(dev);
+ int pmirq;
+ int rc;
+ u8 block, bits, bit;
+ unsigned long flags;
+
+ if (chip == NULL || irq < chip->irq_base ||
+ irq >= chip->irq_base + chip->num_irqs)
+ return -EINVAL;
+
+ pmirq = irq - chip->irq_base;
+
+ block = pmirq / 8;
+ bit = pmirq % 8;
+
+ spin_lock_irqsave(&chip->pm_irq_lock, flags);
+
+ rc = pm8xxx_writeb(chip->dev->parent,
+ SSBI_REG_ADDR_IRQ_BLK_SEL, block);
+ if (rc) {
+ pr_err("Failed Selecting block irq=%d pmirq=%d blk=%d rc=%d\n",
+ irq, pmirq, block, rc);
+ goto bail_out;
+ }
+
+ rc = pm8xxx_readb(chip->dev->parent,
+ SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
+ if (rc) {
+ pr_err("Failed Configuring irq=%d pmirq=%d blk=%d rc=%d\n",
+ irq, pmirq, block, rc);
+ goto bail_out;
+ }
+
+ rc = (bits & (1 << bit)) ? 1 : 0;
+
+bail_out:
+ spin_unlock_irqrestore(&chip->pm_irq_lock, flags);
+
+ return rc;
+}
+EXPORT_SYMBOL(pm8xxx_get_irq_stat);
+
+#ifdef CONFIG_PM
+static int pm8xxx_suspend(struct device *dev)
+{
+ const struct pm_irq_chip *chip = dev_get_drvdata(dev);
+ int pmirq;
+
+ for (pmirq = 0; pmirq < chip->num_irqs; pmirq++) {
+ if (chip->config[i] && !test_bit(i, chip->wake_enable)) {
+ if (!((chip->config[i] & PM_IRQF_MASK_ALL)
+ == PM_IRQF_MASK_ALL)) {
+ irq = i + chip->irq_base;
+ pm8xxx_irq_mask(irq);
+ }
+ }
+ }
+
+ if (!chip->count_wakeable)
+ disable_irq(chip->dev->irq);
+
+ return 0;
+}
+
+void pm8xxx_show_resume_irq(void)
+{
+ struct pm_irq_chip *chip;
+ u8 block, bits;
+ int pmirq;
+
+ list_for_each_entry(chip, &pm_irq_chips, link) {
+ for (pmirq = 0; pmirq < chip->num_irqs; pmirq++) {
+ if (test_bit(pmirq, chip->wake_enable)) {
+ block = pmirq / 8;
+ if (!pm8xxx_read_block(chip, &block, &bits)) {
+ if (bits & (1 << (pmirq & 0x7)))
+ pr_warning("%d triggered\n",
+ pmirq + chip->pdata.irq_base);
+ }
+ }
+ }
+ }
+}
+
+static int pm8xxx_resume(struct device *dev)
+{
+ const struct pm_irq_chip *chip = dev_get_drvdata(dev);
+ int pmirq;
+
+ for (pmirq = 0; pmirq < chip->num_irqs; pmirq++) {
+ if (chip->config[i] && !test_bit(i, chip->wake_enable)) {
+ if (!((chip->config[i] & PM_IRQF_MASK_ALL)
+ == PM_IRQF_MASK_ALL)) {
+ irq = i + chip->irq_base;
+ pm8xxx_irq_unmask(irq);
+ }
+ }
+ }
+
+ if (!chip->count_wakeable)
+ enable_irq(chip->dev->irq);
+
+ return 0;
+}
+#else
+#define pm8xxx_suspend NULL
+#define pm8xxx_resume NULL
+#endif
+
+static const struct dev_pm_ops pm8xxx_pm = {
+ .suspend = pm8xxx_suspend,
+ .resume = pm8xxx_resume,
+};
+
+static int __devinit pm8xxx_irq_probe(struct platform_device *pdev)
+{
+ const struct pm8xxx_irq_platform_data *pdata = pdev->dev.platform_data;
+ struct pm_irq_chip *chip;
+ int devirq;
+ int rc;
+ unsigned int pmirq;
+
+ if (!pdata) {
+ pr_err("No platform data\n");
+ return -EINVAL;
+ }
+
+ devirq = pdata->devirq;
+ if (devirq < 0) {
+ pr_err("missing devirq\n");
+ rc = devirq;
+ goto out;
+ }
+
+ chip = kzalloc(sizeof(struct pm_irq_chip), GFP_KERNEL);
+ if (!chip) {
+ pr_err("Cannot alloc pm_irq_chip struct\n");
+ rc = -ENOMEM;
+ goto out;
+ }
+
+ chip->dev = &pdev->dev;
+ chip->devirq = devirq;
+ chip->irq_base = pdata->irq_base;
+ chip->num_irqs = pdata->irq_cdata.nirqs;
+ chip->num_blocks = DIV_ROUND_UP(chip->num_irqs, 8);
+ chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
+ spin_lock_init(&chip->pm_irq_lock);
+
+ chip->irqs_allowed = kzalloc(sizeof(u8) * chip->num_blocks, GFP_KERNEL);
+ if (!chip->irqs_allowed) {
+ pr_err("Cannot alloc irqs_allowed array\n");
+ rc = -ENOMEM;
+ goto free_pm_irq_chip;
+ }
+
+ chip->irqs_to_handle = kzalloc(sizeof(u16) * chip->num_irqs,
+ GFP_KERNEL);
+ if (!chip->irqs_to_handle) {
+ pr_err("Cannot alloc irqs_to_handle array\n");
+ rc = -ENOMEM;
+ goto free_irqs_allowed;
+ }
+ chip->config = kzalloc(sizeof(u8) * chip->num_irqs, GFP_KERNEL);
+ if (!chip->config) {
+ pr_err("Cannot alloc config array\n");
+ rc = -ENOMEM;
+ goto free_irqs_to_handle;
+ }
+ chip->wake_enable = kzalloc(sizeof(unsigned long)
+ * DIV_ROUND_UP(chip->num_irqs, BITS_PER_LONG),
+ GFP_KERNEL);
+ if (!chip->wake_enable) {
+ pr_err("Cannot alloc wake_enable array\n");
+ rc = -ENOMEM;
+ goto free_config;
+ }
+
+ platform_set_drvdata(pdev, chip);
+ list_add(&chip->link, &pm_irq_chips);
+
+ for (pmirq = 0; pmirq < chip->num_irqs; pmirq++) {
+ set_irq_chip(chip->irq_base + pmirq, &pm8xxx_irq_chip);
+ set_irq_chip_data(chip->irq_base + pmirq, chip);
+ set_irq_handler(chip->irq_base + pmirq, handle_level_irq);
+#ifdef CONFIG_ARM
+ set_irq_flags(chip->irq_base + pmirq, IRQF_VALID);
+#else
+ set_irq_noprobe(chip->irq_base + pmirq);
+#endif
+ }
+
+ set_irq_type(devirq, pdata->irq_trigger_flag);
+ set_irq_data(devirq, chip);
+ set_irq_chained_handler(devirq, pm8xxx_irq_handler);
+ set_irq_wake(devirq, 1);
+
+ return 0;
+
+free_config:
+ kfree(chip->config);
+free_irqs_to_handle:
+ kfree(chip->irqs_to_handle);
+free_irqs_allowed:
+ kfree(chip->irqs_allowed);
+free_pm_irq_chip:
+ kfree(chip);
+out:
+ return rc;
+
+}
+
+static int __devexit pm_irq_remove(struct platform_device *pdev)
+{
+ struct pm_irq_chip *chip = platform_get_drvdata(pdev);
+
+ list_del(&chip->link);
+ platform_set_drvdata(pdev, NULL);
+ set_irq_chained_handler(chip->devirq, NULL);
+ kfree(chip->wake_enable);
+ kfree(chip->config);
+ kfree(chip->irqs_to_handle);
+ kfree(chip->irqs_allowed);
+ kfree(chip);
+ return 0;
+}
+
+static struct platform_driver pm8xxx_irq_driver = {
+ .probe = pm8xxx_irq_probe,
+ .remove = __devexit_p(pm_irq_remove),
+ .driver = {
+ .name = PM8XXX_IRQ_DEV_NAME,
+ .owner = THIS_MODULE,
+ .pm = &pm8xxx_pm,
+ },
+};
+
+static int __init pm_irq_init(void)
+{
+ return platform_driver_register(&pm8xxx_irq_driver);
+}
+postcore_initcall(pm_irq_init);
+
+static void __exit pm_irq_exit(void)
+{
+ platform_driver_unregister(&pm8xxx_irq_driver);
+}
+module_exit(pm_irq_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PMIC IRQ driver");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("platform:" PM8XXX_IRQ_DEV_NAME);
diff --git a/include/linux/mfd/pm8921.h b/include/linux/mfd/pm8921.h
index 17fc37b..92d21bd 100644
--- a/include/linux/mfd/pm8921.h
+++ b/include/linux/mfd/pm8921.h
@@ -18,9 +18,13 @@
#define __MFD_PM8921_H
#include <linux/device.h>
+#include <linux/mfd/pm8xxx/irq.h>
+
+#define NR_PM8921_IRQS 256
struct pm8921_platform_data {
- int irq_base;
+ int irq_base;
+ struct pm8xxx_irq_platform_data *irq_pdata;
};
#endif
diff --git a/include/linux/mfd/pm8xxx/core.h b/include/linux/mfd/pm8xxx/core.h
index 61f1c01..e5aeecf 100644
--- a/include/linux/mfd/pm8xxx/core.h
+++ b/include/linux/mfd/pm8xxx/core.h
@@ -26,6 +26,7 @@ struct pm8xxx_drvdata {
int n);
int (*pmic_write_buf) (const struct device *dev, u16 addr, u8 *buf,
int n);
+ int (*pmic_read_irq_stat) (const struct device *dev, int irq);
void *pm_chip_data;
};
@@ -63,4 +64,12 @@ static inline int pm8xxx_write_buf(const struct device *dev, u16 addr, u8 *buf,
return dd->pmic_write_buf(dev, addr, buf, n);
}
+static inline int pm8xxx_read_irq_stat(const struct device *dev, int irq)
+{
+ struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+ BUG_ON(!dd);
+ return dd->pmic_read_irq_stat(dev, irq);
+}
+
#endif
diff --git a/include/linux/mfd/pm8xxx/irq.h b/include/linux/mfd/pm8xxx/irq.h
new file mode 100644
index 0000000..5ea4294
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/irq.h
@@ -0,0 +1,62 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PMIC irq 8xxx driver header file
+ *
+ */
+
+#ifndef __MFD_PM8XXX_IRQ_H
+#define __MFD_PM8XXX_IRQ_H
+
+#include <linux/errno.h>
+
+#define PM8XXX_IRQ_DEV_NAME "pm8xxx-irq"
+#define PM8XXX_IRQ_DEV_NAME_LEN 10
+
+struct pm8xxx_irq_core_data {
+ u32 rev;
+ int nirqs;
+};
+
+struct pm8xxx_irq_platform_data {
+ int irq_base;
+ struct pm8xxx_irq_core_data irq_cdata;
+ int devirq;
+ int irq_trigger_flag;
+};
+
+#ifdef CONFIG_MFD_PM8XXX_IRQ
+/**
+ * pm8xxx_get_irq_stat - get the status of the irq line
+ * @dev: the interrupt device
+ * @irq: the irq number
+ *
+ * The pm8xxx gpio and mpp rely on the interrupt block to read
+ * the values on their pins. This function is to facilitate reading
+ * the status of a gpio or an mpp line. The caller has to convert the
+ * gpio number to irq number.
+ *
+ * RETURNS:
+ * an int indicating the value read on that line
+ */
+int pm8xxx_get_irq_stat(const struct device *dev, int irq);
+void pm8xxx_show_resume_irq(void);
+#else
+static inline int pm8xxx_get_irq_stat(const struct device *dev, int irq)
+{
+ return -ENXIO;
+}
+static inline void pm8xxx_show_resume_irq(void)
+{
+}
+#endif
+#endif
--
1.7.1
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum
From: Abhijeet Dharmapurikar <[email protected]>
Add support for GPIO on Qualcomm PM8xxx PMIC chips.
Change-Id: I5c00baeedc6c40ed40065d15c83577051e6ac9c6
Signed-off-by: Abhijeet Dharmapurikar <[email protected]>
---
drivers/gpio/Kconfig | 10 +
drivers/gpio/Makefile | 1 +
drivers/gpio/pm8xxx-gpio.c | 452 +++++++++++++++++++++++++++++++++++++++
drivers/mfd/pm8921-core.c | 35 +++-
include/linux/mfd/pm8921.h | 20 ++-
include/linux/mfd/pm8xxx/gpio.h | 132 ++++++++++++
6 files changed, 645 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpio/pm8xxx-gpio.c
create mode 100644 include/linux/mfd/pm8xxx/gpio.h
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 664660e..c5e6f51 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -411,4 +411,14 @@ config GPIO_JANZ_TTL
This driver provides support for driving the pins in output
mode only. Input mode is not supported.
+comment "SSBI GPIO expanders:"
+
+config GPIO_PM8XXX
+ tristate "Qualcomm PM8xxx GPIO support"
+ depends on MFD_PM8XXX
+ default y if MFD_PM8XXX
+ help
+ This option enables support for on-chip GPIO found on Qualcomm PM8xxx
+ PMICs.
+
endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 3351cf8..10efe6c 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -42,3 +42,4 @@ obj-$(CONFIG_GPIO_JANZ_TTL) += janz-ttl.o
obj-$(CONFIG_GPIO_SX150X) += sx150x.o
obj-$(CONFIG_GPIO_VX855) += vx855_gpio.o
obj-$(CONFIG_GPIO_ML_IOH) += ml_ioh_gpio.o
+obj-$(CONFIG_GPIO_PM8XXX) += pm8xxx-gpio.o
diff --git a/drivers/gpio/pm8xxx-gpio.c b/drivers/gpio/pm8xxx-gpio.c
new file mode 100644
index 0000000..621590d
--- /dev/null
+++ b/drivers/gpio/pm8xxx-gpio.c
@@ -0,0 +1,452 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Qualcomm PMIC8XXX GPIO driver
+ *
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/mfd/pm8xxx/core.h>
+#include <linux/mfd/pm8xxx/gpio.h>
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+#include <linux/fs.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+
+/* GPIO registers */
+#define SSBI_REG_ADDR_GPIO_BASE 0x150
+#define SSBI_REG_ADDR_GPIO(n) (SSBI_REG_ADDR_GPIO_BASE + n)
+
+/* GPIO */
+#define PM_GPIO_BANK_MASK 0x70
+#define PM_GPIO_BANK_SHIFT 4
+#define PM_GPIO_WRITE 0x80
+
+/* Bank 0 */
+#define PM_GPIO_VIN_MASK 0x0E
+#define PM_GPIO_VIN_SHIFT 1
+#define PM_GPIO_MODE_ENABLE 0x01
+
+/* Bank 1 */
+#define PM_GPIO_MODE_MASK 0x0C
+#define PM_GPIO_MODE_SHIFT 2
+#define PM_GPIO_OUT_BUFFER 0x02
+#define PM_GPIO_OUT_INVERT 0x01
+
+#define PM_GPIO_MODE_OFF 3
+#define PM_GPIO_MODE_OUTPUT 2
+#define PM_GPIO_MODE_INPUT 0
+#define PM_GPIO_MODE_BOTH 1
+
+/* Bank 2 */
+#define PM_GPIO_PULL_MASK 0x0E
+#define PM_GPIO_PULL_SHIFT 1
+
+/* Bank 3 */
+#define PM_GPIO_OUT_STRENGTH_MASK 0x0C
+#define PM_GPIO_OUT_STRENGTH_SHIFT 2
+
+/* Bank 4 */
+#define PM_GPIO_FUNC_MASK 0x0E
+#define PM_GPIO_FUNC_SHIFT 1
+
+/* Bank 5 */
+#define PM_GPIO_NON_INT_POL_INV 0x08
+#define PM_GPIO_BANKS 6
+
+struct pm_gpio_chip {
+ struct list_head link;
+ struct gpio_chip gpio_chip;
+ struct mutex pm_lock;
+ u8 *bank1;
+ int irq_base;
+};
+
+static LIST_HEAD(pm_gpio_chips);
+
+static int pm_gpio_get(struct pm_gpio_chip *pm_gpio_chip, unsigned gpio)
+{
+ int mode;
+
+ if (gpio >= pm_gpio_chip->gpio_chip.ngpio || pm_gpio_chip == NULL)
+ return -EINVAL;
+
+ /* Get gpio value from config bank 1 if output gpio.
+ Get gpio value from IRQ RT status register for all other gpio modes.
+ */
+ mode = (pm_gpio_chip->bank1[gpio] & PM_GPIO_MODE_MASK) >>
+ PM_GPIO_MODE_SHIFT;
+ if (mode == PM_GPIO_MODE_OUTPUT)
+ return pm_gpio_chip->bank1[gpio] & PM_GPIO_OUT_INVERT;
+ else
+ return pm8xxx_read_irq_stat(pm_gpio_chip->gpio_chip.dev->parent,
+ pm_gpio_chip->irq_base + gpio);
+}
+
+static int pm_gpio_set(struct pm_gpio_chip *pm_gpio_chip,
+ unsigned gpio, int value)
+{
+ int rc;
+ u8 bank1;
+
+ if (gpio >= pm_gpio_chip->gpio_chip.ngpio || pm_gpio_chip == NULL)
+ return -EINVAL;
+
+ mutex_lock(&pm_gpio_chip->pm_lock);
+ bank1 = PM_GPIO_WRITE
+ | (pm_gpio_chip->bank1[gpio] & ~PM_GPIO_OUT_INVERT);
+
+ if (value)
+ bank1 |= PM_GPIO_OUT_INVERT;
+
+ pm_gpio_chip->bank1[gpio] = bank1;
+ rc = pm8xxx_writeb(pm_gpio_chip->gpio_chip.dev->parent,
+ SSBI_REG_ADDR_GPIO(gpio), bank1);
+ mutex_unlock(&pm_gpio_chip->pm_lock);
+
+ if (rc)
+ pr_err("FAIL pm8xxx_writeb(): rc=%d. "
+ "(gpio=%d, value=%d)\n",
+ rc, gpio, value);
+
+ return rc;
+}
+
+static int dir_map[] = {
+ PM_GPIO_MODE_OFF,
+ PM_GPIO_MODE_OUTPUT,
+ PM_GPIO_MODE_INPUT,
+ PM_GPIO_MODE_BOTH,
+};
+
+static int pm_gpio_set_direction(struct pm_gpio_chip *pm_gpio_chip,
+ unsigned gpio, int direction)
+{
+ int rc;
+ u8 bank1;
+
+ if (!direction || pm_gpio_chip == NULL)
+ return -EINVAL;
+
+ mutex_lock(&pm_gpio_chip->pm_lock);
+ bank1 = PM_GPIO_WRITE
+ | (pm_gpio_chip->bank1[gpio] & ~PM_GPIO_MODE_MASK);
+
+ bank1 |= ((dir_map[direction] << PM_GPIO_MODE_SHIFT)
+ & PM_GPIO_MODE_MASK);
+
+ pm_gpio_chip->bank1[gpio] = bank1;
+ rc = pm8xxx_writeb(pm_gpio_chip->gpio_chip.dev->parent,
+ SSBI_REG_ADDR_GPIO(gpio), bank1);
+ mutex_unlock(&pm_gpio_chip->pm_lock);
+
+ if (rc)
+ pr_err("Failed on pm8xxx_writeb(): rc=%d (GPIO config)\n",
+ rc);
+
+ return rc;
+}
+
+static int pm_gpio_init_bank1(struct pm_gpio_chip *pm_gpio_chip)
+{
+ int i, rc;
+ u8 bank;
+
+ for (i = 0; i < pm_gpio_chip->gpio_chip.ngpio; i++) {
+ bank = 1 << PM_GPIO_BANK_SHIFT;
+ rc = pm8xxx_writeb(pm_gpio_chip->gpio_chip.dev->parent,
+ SSBI_REG_ADDR_GPIO(i),
+ bank);
+ if (rc) {
+ pr_err("error setting bank rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = pm8xxx_readb(pm_gpio_chip->gpio_chip.dev->parent,
+ SSBI_REG_ADDR_GPIO(i),
+ &pm_gpio_chip->bank1[i]);
+ if (rc) {
+ pr_err("error reading bank 1 rc=%d\n", rc);
+ return rc;
+ }
+ }
+ return 0;
+}
+
+static int pm_gpio_to_irq(struct gpio_chip *gpio_chip, unsigned offset)
+{
+ struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
+
+ return pm_gpio_chip->irq_base + offset;
+}
+
+static int pm_gpio_read(struct gpio_chip *gpio_chip, unsigned offset)
+{
+ struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
+
+ return pm_gpio_get(pm_gpio_chip, offset);
+}
+
+static void pm_gpio_write(struct gpio_chip *gpio_chip,
+ unsigned offset, int val)
+{
+ struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
+
+ pm_gpio_set(pm_gpio_chip, offset, val);
+}
+
+static int pm_gpio_direction_input(struct gpio_chip *gpio_chip,
+ unsigned offset)
+{
+ struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
+
+ return pm_gpio_set_direction(pm_gpio_chip, offset, PM_GPIO_DIR_IN);
+}
+
+static int pm_gpio_direction_output(struct gpio_chip *gpio_chip,
+ unsigned offset,
+ int val)
+{
+ int ret;
+ struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
+
+ ret = pm_gpio_set_direction(pm_gpio_chip, offset, PM_GPIO_DIR_OUT);
+ if (!ret)
+ ret = pm_gpio_set(pm_gpio_chip, offset, val);
+
+ return ret;
+}
+
+static void pm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gpio_chip)
+{
+ static const char * const cmode[] = { "in", "in/out", "out", "off" };
+ struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
+ u8 mode, state, bank;
+ const char *label;
+ int i, j;
+
+ for (i = 0; i < gpio_chip->ngpio; i++) {
+ label = gpiochip_is_requested(gpio_chip, i);
+ mode = (pm_gpio_chip->bank1[i] & PM_GPIO_MODE_MASK) >>
+ PM_GPIO_MODE_SHIFT;
+ state = pm_gpio_get(pm_gpio_chip, i);
+ seq_printf(s, "gpio-%-3d (%-12.12s) %-10.10s"
+ " %s",
+ gpio_chip->base + i,
+ label ? label : "--",
+ cmode[mode],
+ state ? "hi" : "lo");
+ for (j = 0; j < PM_GPIO_BANKS; j++) {
+ bank = j << PM_GPIO_BANK_SHIFT;
+ pm8xxx_writeb(gpio_chip->dev->parent,
+ SSBI_REG_ADDR_GPIO(i),
+ bank);
+ pm8xxx_readb(gpio_chip->dev->parent,
+ SSBI_REG_ADDR_GPIO(i),
+ &bank);
+ seq_printf(s, " 0x%02x", bank);
+ }
+ seq_printf(s, "\n");
+ }
+}
+
+static int __devinit pm_gpio_probe(struct platform_device *pdev)
+{
+ int ret;
+ const struct pm8xxx_gpio_platform_data *pdata = pdev->dev.platform_data;
+ struct pm_gpio_chip *pm_gpio_chip;
+
+ if (!pdata) {
+ pr_err("missing platform data\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ pm_gpio_chip = kzalloc(sizeof(struct pm_gpio_chip), GFP_KERNEL);
+ if (!pm_gpio_chip) {
+ pr_err("Cannot allocate pm_gpio_chip\n");
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ pm_gpio_chip->bank1 = kzalloc(sizeof(u8) * pdata->gpio_cdata.ngpios,
+ GFP_KERNEL);
+ if (!pm_gpio_chip->bank1) {
+ pr_err("Cannot allocate pm_gpio_chip->bank1\n");
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ mutex_init(&pm_gpio_chip->pm_lock);
+ pm_gpio_chip->gpio_chip.label = "pm-gpio";
+ pm_gpio_chip->gpio_chip.direction_input = pm_gpio_direction_input;
+ pm_gpio_chip->gpio_chip.direction_output = pm_gpio_direction_output;
+ pm_gpio_chip->gpio_chip.to_irq = pm_gpio_to_irq;
+ pm_gpio_chip->gpio_chip.get = pm_gpio_read;
+ pm_gpio_chip->gpio_chip.set = pm_gpio_write;
+ pm_gpio_chip->gpio_chip.dbg_show = pm_gpio_dbg_show;
+ pm_gpio_chip->gpio_chip.ngpio = pdata->gpio_cdata.ngpios;
+ pm_gpio_chip->gpio_chip.can_sleep = 1;
+ pm_gpio_chip->gpio_chip.dev = &pdev->dev;
+ pm_gpio_chip->gpio_chip.base = pdata->gpio_base;
+ pm_gpio_chip->irq_base = platform_get_irq(pdev, 0);
+ list_add(&pm_gpio_chip->link, &pm_gpio_chips);
+ platform_set_drvdata(pdev, pm_gpio_chip);
+
+ ret = gpiochip_add(&pm_gpio_chip->gpio_chip);
+ if (ret) {
+ pr_err("gpiochip_add failed ret = %d\n", ret);
+ goto reset_drvdata;
+ }
+
+ ret = pm_gpio_init_bank1(pm_gpio_chip);
+ if (ret) {
+ pr_err("gpio init bank failed ret = %d\n", ret);
+ goto remove_chip;
+ }
+
+ return 0;
+
+remove_chip:
+ if (gpiochip_remove(&pm_gpio_chip->gpio_chip))
+ pr_err("failed to remove gpio chip\n");
+reset_drvdata:
+ platform_set_drvdata(pdev, NULL);
+ mutex_destroy(&pm_gpio_chip->pm_lock);
+ kfree(pm_gpio_chip);
+out:
+ return ret;
+}
+
+static int __devexit pm_gpio_remove(struct platform_device *pdev)
+{
+ struct pm_gpio_chip *pm_gpio_chip
+ = platform_get_drvdata(pdev);
+
+ platform_set_drvdata(pdev, NULL);
+ if (gpiochip_remove(&pm_gpio_chip->gpio_chip))
+ pr_err("failed to remove gpio chip\n");
+ mutex_destroy(&pm_gpio_chip->pm_lock);
+ kfree(pm_gpio_chip->bank1);
+ kfree(pm_gpio_chip);
+ return 0;
+}
+
+int pm8xxx_gpio_config(int gpio, struct pm_gpio *param)
+{
+ int rc;
+ u8 bank[8];
+ struct pm_gpio_chip *pm_gpio_chip;
+ struct gpio_chip *gpio_chip;
+ int pm_gpio;
+ int found = 0;
+
+ if (param == NULL)
+ return -EINVAL;
+ list_for_each_entry(pm_gpio_chip, &pm_gpio_chips, link) {
+ gpio_chip = &pm_gpio_chip->gpio_chip;
+ if (gpio >= gpio_chip->base
+ && gpio < gpio_chip->base + gpio_chip->ngpio) {
+ found = 1;
+ pm_gpio = gpio - gpio_chip->base;
+ break;
+ }
+ }
+ if (!found) {
+ pr_err("called on gpio %d not handled by any pmic\n", gpio);
+ return -EINVAL;
+ }
+
+ /* Select banks and configure the gpio */
+ bank[0] = PM_GPIO_WRITE |
+ ((param->vin_sel << PM_GPIO_VIN_SHIFT) &
+ PM_GPIO_VIN_MASK) |
+ PM_GPIO_MODE_ENABLE;
+ bank[1] = PM_GPIO_WRITE |
+ ((1 << PM_GPIO_BANK_SHIFT) &
+ PM_GPIO_BANK_MASK) |
+ ((dir_map[param->direction] <<
+ PM_GPIO_MODE_SHIFT) &
+ PM_GPIO_MODE_MASK) |
+ ((param->direction & PM_GPIO_DIR_OUT) ?
+ ((param->output_buffer & 1) ?
+ PM_GPIO_OUT_BUFFER : 0) : 0) |
+ ((param->direction & PM_GPIO_DIR_OUT) ?
+ param->output_value & 0x01 : 0);
+ bank[2] = PM_GPIO_WRITE |
+ ((2 << PM_GPIO_BANK_SHIFT) &
+ PM_GPIO_BANK_MASK) |
+ ((param->pull << PM_GPIO_PULL_SHIFT) &
+ PM_GPIO_PULL_MASK);
+ bank[3] = PM_GPIO_WRITE |
+ ((3 << PM_GPIO_BANK_SHIFT) &
+ PM_GPIO_BANK_MASK) |
+ ((param->out_strength <<
+ PM_GPIO_OUT_STRENGTH_SHIFT) &
+ PM_GPIO_OUT_STRENGTH_MASK);
+ bank[4] = PM_GPIO_WRITE |
+ ((4 << PM_GPIO_BANK_SHIFT) &
+ PM_GPIO_BANK_MASK) |
+ ((param->function << PM_GPIO_FUNC_SHIFT) &
+ PM_GPIO_FUNC_MASK);
+ bank[5] = PM_GPIO_WRITE |
+ ((5 << PM_GPIO_BANK_SHIFT) & PM_GPIO_BANK_MASK) |
+ (param->inv_int_pol ? 0 : PM_GPIO_NON_INT_POL_INV);
+
+ mutex_lock(&pm_gpio_chip->pm_lock);
+ /* Remember bank1 for later use */
+ pm_gpio_chip->bank1[pm_gpio] = bank[1];
+ rc = pm8xxx_write_buf(pm_gpio_chip->gpio_chip.dev->parent,
+ SSBI_REG_ADDR_GPIO(pm_gpio), bank, 6);
+ mutex_unlock(&pm_gpio_chip->pm_lock);
+
+ if (rc)
+ pr_err("Failed on pm8xxx_write_buf() rc=%d (GPIO config)\n",
+ rc);
+
+ return rc;
+}
+EXPORT_SYMBOL(pm8xxx_gpio_config);
+
+static struct platform_driver pm_gpio_driver = {
+ .probe = pm_gpio_probe,
+ .remove = __devexit_p(pm_gpio_remove),
+ .driver = {
+ .name = PM8XXX_GPIO_DEV_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init pm_gpio_init(void)
+{
+ int rc = platform_driver_register(&pm_gpio_driver);
+
+ return rc;
+}
+
+static void __exit pm_gpio_exit(void)
+{
+ platform_driver_unregister(&pm_gpio_driver);
+}
+
+subsys_initcall(pm_gpio_init);
+module_exit(pm_gpio_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PMIC GPIO driver");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("platform:" PM8XXX_GPIO_DEV_NAME);
diff --git a/drivers/mfd/pm8921-core.c b/drivers/mfd/pm8921-core.c
index 2102e8b..8d47626 100644
--- a/drivers/mfd/pm8921-core.c
+++ b/drivers/mfd/pm8921-core.c
@@ -20,6 +20,7 @@
#include <linux/mfd/pm8921.h>
#include <linux/mfd/pm8xxx/core.h>
#include <linux/mfd/pm8xxx/irq.h>
+#include <linux/mfd/pm8xxx/gpio.h>
#define REG_HWREV 0x002 /* PMIC4 revision */
#define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */
@@ -84,6 +85,22 @@ static struct __devinitdata mfd_cell irq_cell = {
.id = -1,
};
+static const struct resource gpio_cell_resources[] __devinitconst = {
+ [0] = {
+ .start = PM8921_IRQ_BLOCK_BIT(PM8921_GPIO_BLOCK_START, 0),
+ .end = PM8921_IRQ_BLOCK_BIT(PM8921_GPIO_BLOCK_START, 0)
+ + NR_PM8921_IRQS - 1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct mfd_cell gpio_cell __devinitdata = {
+ .name = PM8XXX_GPIO_DEV_NAME,
+ .id = -1,
+ .resources = gpio_cell_resources,
+ .num_resources = ARRAY_SIZE(gpio_cell_resources),
+};
+
static int __devinit pm8921_add_subdevices(const struct pm8921_platform_data
*pdata,
struct pm8921 *pmic,
@@ -102,11 +119,25 @@ static int __devinit pm8921_add_subdevices(const struct pm8921_platform_data
NULL, 0);
if (ret < 0) {
pr_err("Failed to add irq_subdevice ret=%d\n", ret);
- return ret;
+ goto bail;
}
}
- return 0;
+ if (pdata->gpio_pdata) {
+ pdata->gpio_pdata->gpio_cdata.ngpios = NR_PM8921_GPIOS;
+ pdata->gpio_pdata->gpio_cdata.rev = rev;
+ gpio_cell.platform_data = pdata->gpio_pdata;
+ gpio_cell.data_size = sizeof(struct pm8xxx_gpio_platform_data);
+ ret = mfd_add_devices(pmic->dev, 0, &gpio_cell, 1,
+ NULL, irq_base);
+ if (ret) {
+ pr_err("Failed to add gpio subdevice ret=%d\n", ret);
+ goto bail;
+ }
+ }
+
+bail:
+ return ret;
}
static int __devinit match_irq_dev(struct device *dev, void *data)
diff --git a/include/linux/mfd/pm8921.h b/include/linux/mfd/pm8921.h
index 92d21bd..691b1d3 100644
--- a/include/linux/mfd/pm8921.h
+++ b/include/linux/mfd/pm8921.h
@@ -19,12 +19,26 @@
#include <linux/device.h>
#include <linux/mfd/pm8xxx/irq.h>
+#include <linux/mfd/pm8xxx/gpio.h>
-#define NR_PM8921_IRQS 256
+#define NR_PM8921_IRQS 256
+
+#define NR_PM8921_GPIOS 44
+
+#define PM8921_GPIO_BLOCK_START 24
+#define PM8921_MPP_BLOCK_START 16
+#define PM8921_IRQ_BLOCK_BIT(block, bit) ((block) * 8 + (bit))
+
+/* MPPs and GPIOs [1,N) */
+#define PM8921_MPP_IRQ(base, mpp) ((base) + \
+ PM8921_IRQ_BLOCK_BIT(PM8921_MPP_BLOCK_START, (mpp)-1))
+#define PM8921_GPIO_IRQ(base, gpio) ((base) + \
+ PM8921_IRQ_BLOCK_BIT(PM8921_GPIO_BLOCK_START, (gpio)-1))
struct pm8921_platform_data {
- int irq_base;
- struct pm8xxx_irq_platform_data *irq_pdata;
+ int irq_base;
+ struct pm8xxx_irq_platform_data *irq_pdata;
+ struct pm8xxx_gpio_platform_data *gpio_pdata;
};
#endif
diff --git a/include/linux/mfd/pm8xxx/gpio.h b/include/linux/mfd/pm8xxx/gpio.h
new file mode 100644
index 0000000..3ab08e0
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/gpio.h
@@ -0,0 +1,132 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Qualcomm PMIC8XXX gpio driver header file
+ *
+ */
+
+#ifndef __PM8XXX_GPIO_H
+#define __PM8XXX_GPIO_H
+
+#include <linux/errno.h>
+
+#define PM8XXX_GPIO_DEV_NAME "pm8xxx-gpio"
+
+struct pm8xxx_gpio_core_data {
+ u32 rev;
+ int ngpios;
+};
+
+struct pm8xxx_gpio_platform_data {
+ struct pm8xxx_gpio_core_data gpio_cdata;
+ int gpio_base;
+};
+
+/* GPIO parameters */
+/* direction */
+#define PM_GPIO_DIR_OUT 0x01
+#define PM_GPIO_DIR_IN 0x02
+#define PM_GPIO_DIR_BOTH (PM_GPIO_DIR_OUT | PM_GPIO_DIR_IN)
+
+/* output_buffer */
+#define PM_GPIO_OUT_BUF_OPEN_DRAIN 1
+#define PM_GPIO_OUT_BUF_CMOS 0
+
+/* pull */
+#define PM_GPIO_PULL_UP_30 0
+#define PM_GPIO_PULL_UP_1P5 1
+#define PM_GPIO_PULL_UP_31P5 2
+#define PM_GPIO_PULL_UP_1P5_30 3
+#define PM_GPIO_PULL_DN 4
+#define PM_GPIO_PULL_NO 5
+
+/* vin_sel: Voltage Input Select */
+#define PM_GPIO_VIN_VPH 0
+#define PM_GPIO_VIN_BB 1
+#define PM_GPIO_VIN_S3 2
+#define PM_GPIO_VIN_L3 3
+#define PM_GPIO_VIN_L7 4
+#define PM_GPIO_VIN_L6 5
+#define PM_GPIO_VIN_L5 6
+#define PM_GPIO_VIN_L2 7
+
+/* out_strength */
+#define PM_GPIO_STRENGTH_NO 0
+#define PM_GPIO_STRENGTH_HIGH 1
+#define PM_GPIO_STRENGTH_MED 2
+#define PM_GPIO_STRENGTH_LOW 3
+
+/* function */
+#define PM_GPIO_FUNC_NORMAL 0
+#define PM_GPIO_FUNC_PAIRED 1
+#define PM_GPIO_FUNC_1 2
+#define PM_GPIO_FUNC_2 3
+#define PM_GPIO_DTEST1 4
+#define PM_GPIO_DTEST2 5
+#define PM_GPIO_DTEST3 6
+#define PM_GPIO_DTEST4 7
+
+/**
+ * struct pm_gpio - structure to specify gpio configurtion values
+ * @direction: indicates whether the gpio should be input, output, or
+ * both. Should be of the type PM_GPIO_DIR_*
+ * @output_buffer: indicates gpio should be configured as CMOS or open
+ * drain. Should be of the type PM_GPIO_OUT_BUF_*
+ * @output_value: The gpio output value of the gpio line - 0 or 1
+ * @pull: Indicates whether a pull up or pull down should be
+ * applied. If a pullup is required the current strength
+ * needs to be specified. Current values of 30uA, 1.5uA,
+ * 31.5uA, 1.5uA with 30uA boost are supported. This value
+ * should be one of the PM_GPIO_PULL_*
+ * @vin_sel: specifies the voltage level when the output is set to 1.
+ * For an input gpio specifies the voltage level at which
+ * the input is interpreted as a logical 1.
+ * @out_strength: the amount of current supplied for an output gpio,
+ * should be of the type PM_GPIO_STRENGTH_*
+ * @function: choose alternate function for the gpio. Certain gpios
+ * can be paired (shorted) with each other. Some gpio pin
+ * can act as alternate functions. This parameter should
+ * be of type PM_GPIO_FUNC_*
+ * @inv_int_pol: Invert polarity before feeding the line to the interrupt
+ * module in pmic. This feature will almost be never used
+ * since the pm8xxx interrupt block can detect both edges
+ * and both levels.
+ */
+struct pm_gpio {
+ int direction;
+ int output_buffer;
+ int output_value;
+ int pull;
+ int vin_sel;
+ int out_strength;
+ int function;
+ int inv_int_pol;
+};
+
+#if defined(CONFIG_GPIO_PM8XXX) || defined(CONFIG_GPIO_PM8XXX_MODULE)
+/**
+ * pm8xxx_gpio_config - configure a gpio controlled by a pm8xxx chip
+ * @gpio: gpio number to configure
+ * @param: configuration values
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8xxx_gpio_config(int gpio, struct pm_gpio *param);
+#else
+static inline int pm8xxx_gpio_config(int gpio, struct pm_gpio *param)
+{
+ return -ENXIO;
+}
+#endif
+
+#endif
--
1.7.1
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum
On Wed, Mar 02, 2011 at 02:13:16PM -0800, [email protected] wrote:
> +config MFD_PM8XXX
> + tristate "Support for Qualcomm PM8xxx subdevices"
> + help
> + This option enables the usage of various Qualcomm PMIC 8xxx subdevice
> + drivers. This is required in order to use generic PM8xxx subdevice
> + drivers. Selecting with option will result in PM8xxx subdevice
> + drivers being compiled by default.
As this is selected by the driver it shouldn't have any help text -
there's no point in users seeing the option since it's useless by
itself. If we get enough to make an option useful either a menu or
dependencies from the individual MFDs would be a better option.
> +static int __devinit pm8921_add_subdevices(const struct pm8921_platform_data
> + *pdata,
> + struct pm8921 *pmic)
> +{
> + return 0;
> +}
This looks suspicious.
> +static int __init pm8921_init(void)
> +{
> + return platform_driver_register(&pm8921_driver);
> +}
> +postcore_initcall(pm8921_init);
Typically subsys_initcall() has been used.
On Wed, Mar 02, 2011 at 02:13:17PM -0800, [email protected] wrote:
>
> Change-Id: Ibb23878cd382af9a750d62ab49482f5dc72e3714
> Signed-off-by: Abhijeet Dharmapurikar <[email protected]>
Remove the change IDs from upstream submissions. The kernel doesn't use
gerritt.
> struct pm8921 {
> - struct device *dev;
> + struct device *dev;
> + struct device *irq_dev;
Is it really useful to register a struct device purely for the interrupt
controller? I'd have expected this to be core functionality of the
device. The fact that you need to store the device at all is a bit odd
too as you're using the MFD API.
> static struct pm8xxx_drvdata pm8921_drvdata = {
> - .pmic_readb = pm8921_readb,
> - .pmic_writeb = pm8921_writeb,
> - .pmic_read_buf = pm8921_read_buf,
> - .pmic_write_buf = pm8921_write_buf,
> + .pmic_readb = pm8921_readb,
> + .pmic_writeb = pm8921_writeb,
> + .pmic_read_buf = pm8921_read_buf,
> + .pmic_write_buf = pm8921_write_buf,
> + .pmic_read_irq_stat = pm8921_read_irq_stat,
> +};
It'd seem better to indent things as per the final driver in the first
patch - this reindentation creates a lot of noise in the diff.
> goto err_read_rev;
> }
> - pr_info("PMIC revision: %02X\n", val);
> + pr_info("PMIC revision 1: %02X\n", val);
> + rev = val;
>
Again, do this in the first patch.
> +static int
> +pm8xxx_read_block(const struct pm_irq_chip *chip, u8 bp, u8 *ip)
> +{
> + int rc;
> +
> + rc = pm8xxx_writeb(chip->dev->parent,
> + SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
> + if (rc) {
> + pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
> + goto bail_out;
> + }
> +
> + rc = pm8xxx_readb(chip->dev->parent,
> + SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
> + if (rc)
> + pr_err("Failed Reading Status rc=%d\n", rc);
> +bail_out:
> + return rc;
> +}
The namespacing here is odd, this looks like it should be a generic API
not a block specific one.
> + /* Check IRQ bits */
> + for (k = 0; k < 8; k++) {
> + if (bits & (1 << k)) {
> + pmirq = block * 8 + k;
> + irq = pmirq + chip->irq_base;
> + /* Check spurious interrupts */
> + if (((1 << k) & chip->irqs_allowed[block])) {
> + /* Found one */
> + chip->irqs_to_handle[*handled] = irq;
> + (*handled)++;
> + } else { /* Clear and mask wrong one */
> + config = PM_IRQF_W_C_M |
> + (k << PM_IRQF_BITS_SHIFT);
> +
> + pm8xxx_config_irq(chip,
> + block, config);
> +
> + if (pm8xxx_can_print())
> + pr_err("Spurious IRQ: %d "
> + "[block, bit]="
> + "[%d, %d]\n",
> + irq, block, k);
> + }
The generic IRQ code should be able to take care of spurious interrupts
for you? It's a bit surprising that there's all this logic - I'd expect
an IRQ chip to just defer logic about which interrupts are valid and so
on to the generic IRQ code.
> #include <linux/device.h>
> +#include <linux/mfd/pm8xxx/irq.h>
> +
> +#define NR_PM8921_IRQS 256
Traditionally this'd be namespaced like this:
+#define PM8921_NR_IRQS 256
On Wed, 2011-03-02 at 14:13 -0800, [email protected] wrote:
> diff --git a/MAINTAINERS b/MAINTAINERS
The patch subject is not quite correct.
You're adding patterns, not maintainers.
> index 696cb18..97107fd 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -905,6 +905,12 @@ F: drivers/mmc/host/msm_sdcc.h
> F: drivers/tty/serial/msm_serial.h
> F: drivers/tty/serial/msm_serial.c
> F: drivers/platform/msm/
> +F: drivers/mfd/pm8921-core.c
> +F: drivers/mfd/pm8xxx-mpp.c
> +F: include/linux/mfd/pm8921.h
> +F: include/linux/mfd/pm8xxx/
> +F: drivers/gpio/pm8xxx-gpio.c
> +F: drivers/mfd/pm8xxx-irq.c
My preference is to keep these in alphabetic order.
Another option is a wildcard pattern match like:
F: drivers/*/pm8???-*
instead of:
F: drivers/gpio/pm8xxx-gpio.c
F: drivers/mfd/pm8921-core.c
F: drivers/mfd/pm8xxx-irq.c
F: drivers/mfd/pm8xxx-mpp.c
Mark Brown wrote:
> On Wed, Mar 02, 2011 at 02:13:16PM -0800, [email protected] wrote:
>
>> +config MFD_PM8XXX
>> + tristate "Support for Qualcomm PM8xxx subdevices"
>> + help
>> + This option enables the usage of various Qualcomm PMIC 8xxx subdevice
>> + drivers. This is required in order to use generic PM8xxx subdevice
>> + drivers. Selecting with option will result in PM8xxx subdevice
>> + drivers being compiled by default.
>
> As this is selected by the driver it shouldn't have any help text -
> there's no point in users seeing the option since it's useless by
> itself. If we get enough to make an option useful either a menu or
> dependencies from the individual MFDs would be a better option.
Agree will fix this.
>
>> +static int __devinit pm8921_add_subdevices(const struct pm8921_platform_data
>> + *pdata,
>> + struct pm8921 *pmic)
>> +{
>> + return 0;
>> +}
>
> This looks suspicious.
True, the next patch fills in this function. Will remove it from here.
>
>> +static int __init pm8921_init(void)
>> +{
>> + return platform_driver_register(&pm8921_driver);
>> +}
>> +postcore_initcall(pm8921_init);
>
> Typically subsys_initcall() has been used.
Yes will change this and others to subsys_initcall()
--
Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm
Innovation Center, Inc. is a member of the Code Aurora Forum.
Mark Brown wrote:
> On Wed, Mar 02, 2011 at 02:13:17PM -0800, [email protected] wrote:
>> Change-Id: Ibb23878cd382af9a750d62ab49482f5dc72e3714
>> Signed-off-by: Abhijeet Dharmapurikar <[email protected]>
>
> Remove the change IDs from upstream submissions. The kernel doesn't use
> gerritt.
>
>> struct pm8921 {
>> - struct device *dev;
>> + struct device *dev;
>> + struct device *irq_dev;
>
> Is it really useful to register a struct device purely for the interrupt
> controller? I'd have expected this to be core functionality of the
> device. The fact that you need to store the device at all is a bit odd
> too as you're using the MFD API.
This design is slightly different from other MFD drivers.
I separated the interrupt from the core because the interrupt
implementation for different Qualcomm pmics remains the same. On 8660
FFA boards for example, we have two pmic chips that have the same
interrupt subdevice implementation (the number of interrupts managed by
each is different). I didn't want to duplicate the exact code in the
core driver - hence a separate interrupt driver.
To answer why we need to keep a reference to irq_dev. This is so because
the gpio code needs to make calls on the irq driver to read the input
values. The gpio code calls pm8xxx_read_irq_stat() on the core and
expects it to read the value. The core then calls an api in the irq
driver (pm8xxx_get_irq_stat)passing it irq_dev to get the required values.
I could have made the gpio code call the irq code directly, but then
that would mean the irq driver has to go over all its devices and find
which device handles this irq number and then read it. That is too much
code execution as compared to remember the irq_dev for each core and let
the gpio code call read apis on it.
>
>> static struct pm8xxx_drvdata pm8921_drvdata = {
>> - .pmic_readb = pm8921_readb,
>> - .pmic_writeb = pm8921_writeb,
>> - .pmic_read_buf = pm8921_read_buf,
>> - .pmic_write_buf = pm8921_write_buf,
>> + .pmic_readb = pm8921_readb,
>> + .pmic_writeb = pm8921_writeb,
>> + .pmic_read_buf = pm8921_read_buf,
>> + .pmic_write_buf = pm8921_write_buf,
>> + .pmic_read_irq_stat = pm8921_read_irq_stat,
>> +};
>
> It'd seem better to indent things as per the final driver in the first
> patch - this reindentation creates a lot of noise in the diff.
>
>> goto err_read_rev;
>> }
>> - pr_info("PMIC revision: %02X\n", val);
>> + pr_info("PMIC revision 1: %02X\n", val);
>> + rev = val;
Yes will fix them
>>
>
> Again, do this in the first patch.
>
>> +static int
>> +pm8xxx_read_block(const struct pm_irq_chip *chip, u8 bp, u8 *ip)
>> +{
>> + int rc;
>> +
>> + rc = pm8xxx_writeb(chip->dev->parent,
>> + SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
>> + if (rc) {
>> + pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
>> + goto bail_out;
>> + }
>> +
>> + rc = pm8xxx_readb(chip->dev->parent,
>> + SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
>> + if (rc)
>> + pr_err("Failed Reading Status rc=%d\n", rc);
>> +bail_out:
>> + return rc;
>> +}
>
> The namespacing here is odd, this looks like it should be a generic API
> not a block specific one.
It indicates that the code intends to read a block of interrupt
statuses. The irq h/w is implemented as follows, there are 256
interrupts. One block manages 8 interrupts, so there are 32 blocks.
One master manages 8 blocks so there are 4 masters. And finally there
is one root that manages all the 4 masters.
When an interrupt triggers, the corresponding bit in the block, master
and root is set. The handler reads the root and figures out which master
is set. It then reads the master and figures out which block in that
master is set. It then reads the block to figure out which interrupt in
that block is set. This hardware design makes the handler find the
interrupt super quick as opposed to checking 256 bits when an interrupt
fires.
With that in mind, the driver has following functions
pm8xxxx_read_root
pm8xxxx_read_master
pm8xxxx_read_block
Do you still think I should change the name?
>
>> + /* Check IRQ bits */
>> + for (k = 0; k < 8; k++) {
>> + if (bits & (1 << k)) {
>> + pmirq = block * 8 + k;
>> + irq = pmirq + chip->irq_base;
>> + /* Check spurious interrupts */
>> + if (((1 << k) & chip->irqs_allowed[block])) {
>> + /* Found one */
>> + chip->irqs_to_handle[*handled] = irq;
>> + (*handled)++;
>> + } else { /* Clear and mask wrong one */
>> + config = PM_IRQF_W_C_M |
>> + (k << PM_IRQF_BITS_SHIFT);
>> +
>> + pm8xxx_config_irq(chip,
>> + block, config);
>> +
>> + if (pm8xxx_can_print())
>> + pr_err("Spurious IRQ: %d "
>> + "[block, bit]="
>> + "[%d, %d]\n",
>> + irq, block, k);
>> + }
>
> The generic IRQ code should be able to take care of spurious interrupts
> for you? It's a bit surprising that there's all this logic - I'd expect
> an IRQ chip to just defer logic about which interrupts are valid and so
> on to the generic IRQ code.
That is correct, the genirq does handle spurious interrupts gracefully.
Will fix this in the next patch series.
>> +
>> +#define NR_PM8921_IRQS 256
>
> Traditionally this'd be namespaced like this:
>
> +#define PM8921_NR_IRQS 256
ok good to know will change that.
--
Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm
Innovation Center, Inc. is a member of the Code Aurora Forum.
Joe Perches wrote:
> On Wed, 2011-03-02 at 14:13 -0800, [email protected] wrote:
>> diff --git a/MAINTAINERS b/MAINTAINERS
>
> The patch subject is not quite correct.
> You're adding patterns, not maintainers.
Ok will fix it in the next patch series.
> Another option is a wildcard pattern match like:
>
> F: drivers/*/pm8???-*
>
> instead of:
>
> F: drivers/gpio/pm8xxx-gpio.c
> F: drivers/mfd/pm8921-core.c
> F: drivers/mfd/pm8xxx-irq.c
> F: drivers/mfd/pm8xxx-mpp.c
Will do, thanks for this wildcard pattern
--
Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm
Innovation Center, Inc. is a member of the Code Aurora Forum.
On Wed, Mar 02, 2011 at 08:38:03PM -0800, Abhijeet Dharmapurikar wrote:
> Mark Brown wrote:
> >Is it really useful to register a struct device purely for the interrupt
> >controller? I'd have expected this to be core functionality of the
> >device. The fact that you need to store the device at all is a bit odd
> >too as you're using the MFD API.
> This design is slightly different from other MFD drivers.
> I separated the interrupt from the core because the interrupt
> implementation for different Qualcomm pmics remains the same. On
> 8660 FFA boards for example, we have two pmic chips that have the
> same interrupt subdevice implementation (the number of interrupts
> managed by each is different). I didn't want to duplicate the exact
> code in the core driver - hence a separate interrupt driver.
Could you deal with this with a library instead?
> With that in mind, the driver has following functions
> pm8xxxx_read_root
> pm8xxxx_read_master
> pm8xxxx_read_block
> Do you still think I should change the name?
I'd suggest adding an _irq in there.
Mark Brown wrote:
> On Wed, Mar 02, 2011 at 08:38:03PM -0800, Abhijeet Dharmapurikar wrote:
>> Mark Brown wrote:
>
>>> Is it really useful to register a struct device purely for the interrupt
>>> controller? I'd have expected this to be core functionality of the
>>> device. The fact that you need to store the device at all is a bit odd
>>> too as you're using the MFD API.
>
>> This design is slightly different from other MFD drivers.
>> I separated the interrupt from the core because the interrupt
>> implementation for different Qualcomm pmics remains the same. On
>> 8660 FFA boards for example, we have two pmic chips that have the
>> same interrupt subdevice implementation (the number of interrupts
>> managed by each is different). I didn't want to duplicate the exact
>> code in the core driver - hence a separate interrupt driver.
>
> Could you deal with this with a library instead?
Can you please clarify what a library means here?
>> pm8xxxx_read_block
>
>> Do you still think I should change the name?
>
> I'd suggest adding an _irq in there.
Ok will do.
--
Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm
Innovation Center, Inc. is a member of the Code Aurora Forum.
On Thu, Mar 03, 2011 at 02:55:00PM -0800, Abhijeet Dharmapurikar wrote:
> Mark Brown wrote:
>> Could you deal with this with a library instead?
> Can you please clarify what a library means here?
You can share the code without creating a struct device, just have the
driver for each chip call into the common code.