On Fri, Oct 01, 2021 at 11:05:15AM +0000, Haakon Bugge wrote:
> Hey,
>
>
> Commit 1477d44ce47d ("RDMA/mlx5: Enable Relaxed Ordering by default
> for kernel ULPs") uses pcie_relaxed_ordering_enabled() to check if
> RO can be enabled. This function checks if the Enable Relaxed
> Ordering bit in the Device Control register is set. However, on a
> VF, this bit is RsvdP (Reserved for future RW
> implementations. Register bits are read-only and must return zero
> when read. Software must preserve the value read for writes to
> bits.).
>
> Hence, AFAICT, RO will not be enabled when using a VF.
>
> How can that be fixed?
When qemu takes a VF and turns it into a PF in a VM it must emulate
the RO bit and return one
Jason
> On 1 Oct 2021, at 13:54, Jason Gunthorpe <[email protected]> wrote:
>
> On Fri, Oct 01, 2021 at 11:05:15AM +0000, Haakon Bugge wrote:
>> Hey,
>>
>>
>> Commit 1477d44ce47d ("RDMA/mlx5: Enable Relaxed Ordering by default
>> for kernel ULPs") uses pcie_relaxed_ordering_enabled() to check if
>> RO can be enabled. This function checks if the Enable Relaxed
>> Ordering bit in the Device Control register is set. However, on a
>> VF, this bit is RsvdP (Reserved for future RW
>> implementations. Register bits are read-only and must return zero
>> when read. Software must preserve the value read for writes to
>> bits.).
>>
>> Hence, AFAICT, RO will not be enabled when using a VF.
>>
>> How can that be fixed?
>
> When qemu takes a VF and turns it into a PF in a VM it must emulate
> the RO bit and return one
I have a pass-through VF:
# lspci -s ff:00.0 -vvv
ff:00.0 Ethernet controller: Mellanox Technologies MT28800 Family [ConnectX-5 Ex Virtual Function]
[]
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- FLReset-
Håkon