2012-05-10 07:45:56

by Hiroshi Doyu

Subject: [PATCH 1/2] iommu/tegra: gart: Fix register offset correctly

DT passes the exact GART register ranges without any overlapping with
MC register ranges. GART register offset needs to be adjusted by one
passed by DT correctly.

Signed-off-by: Hiroshi DOYU <[email protected]>
---
.../bindings/iommu/nvidia,tegra20-gart.txt | 6 +++---
drivers/iommu/tegra-gart.c | 7 ++++---
2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt
index 2d87b91..099d936 100644
--- a/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt
+++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt
@@ -7,8 +7,8 @@ Required properties:

Example:

- gart: gart@7000f000 {
+ gart {
compatible = "nvidia,tegra20-gart";
- reg = < 0x7000f000 0x00000100 /* controller registers */
- 0x58000000 0x02000000 >; /* GART aperture */
+ reg = <0x7000f024 0x00000018 /* controller registers */
+ 0x58000000 0x02000000>; /* GART aperture */
};
diff --git a/drivers/iommu/tegra-gart.c b/drivers/iommu/tegra-gart.c
index 40533bb..0c0a377 100644
--- a/drivers/iommu/tegra-gart.c
+++ b/drivers/iommu/tegra-gart.c
@@ -36,9 +36,10 @@
/* bitmap of the page sizes currently supported */
#define GART_IOMMU_PGSIZES (SZ_4K)

-#define GART_CONFIG 0x24
-#define GART_ENTRY_ADDR 0x28
-#define GART_ENTRY_DATA 0x2c
+#define GART_REG_BASE 0x24
+#define GART_CONFIG (0x24 - GART_REG_BASE)
+#define GART_ENTRY_ADDR (0x28 - GART_REG_BASE)
+#define GART_ENTRY_DATA (0x2c - GART_REG_BASE)
#define GART_ENTRY_PHYS_ADDR_VALID (1 << 31)

#define GART_PAGE_SHIFT 12
--
1.7.5.4

2012-05-10 07:46:03

by Hiroshi Doyu

Subject: [PATCH 2/2] ARM: dt: tegra20.dtsi: Add GART node

Add a node for the Tegra20 GART

Signed-off-by: Hiroshi DOYU <[email protected]>
---
arch/arm/boot/dts/tegra20.dtsi | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 548b42e..c6cf42e 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -207,6 +207,12 @@
phy_type = "utmi";
};

+ gart {
+ compatible = "nvidia,tegra20-gart";
+ reg = <0x7000f024 0x00000018 /* controller registers */
+ 0x58000000 0x02000000>; /* GART aperture */
+ };
+
ahb: ahb@6000c004 {
compatible = "nvidia,tegra20-ahb";
reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
--
1.7.5.4

2012-05-10 17:28:35

by Stephen Warren

Subject: Re: [PATCH 1/2] iommu/tegra: gart: Fix register offset correctly

On 05/10/2012 01:45 AM, Hiroshi DOYU wrote:
> DT passes the exact GART register ranges without any overlapping with
> MC register ranges. GART register offset needs to be adjusted by one
> passed by DT correctly.
>
> Signed-off-by: Hiroshi DOYU <[email protected]>

Acked-by: Stephen Warren <[email protected]>

Joerg, I assume you'll take this patch through the iommu tree and I'll
take patch 2 through the Tegra tree?