The three UFS reference clocks, gcc_ufs_ref_clkref_clk for external
UFS devices, gcc_ufs_card_clkref_clk and gcc_ufs_1_card_clkref_clk for
two PHYs are all sourced from CXO.
Added parent_data for all three reference clocks described above to
reflect that all three clocks are sourced from CXO to have valid
frequency for the ref clock needed by UFS controller driver.
Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver")
Link: https://lore.kernel.org/lkml/Y2Tber39cHuOSR%[email protected]/
Signed-off-by: Shazad Hussain <[email protected]>
Tested-by: Johan Hovold <[email protected]>
Reviewed-by: Johan Hovold <[email protected]>
Tested-by: Andrew Halaney <[email protected]>
Reviewed-by: Andrew Halaney <[email protected]>
Reviewed-by: Reviewed-by: Brian Masney <[email protected]>
---
Changes since v2:
- Tweaked commit message and added R-b T-b from v2
v2 of this patch can be found at
https://lore.kernel.org/all/[email protected]/
v1 of this patch can be found at
https://lore.kernel.org/all/[email protected]/
used below patches for verification on next-20221114
https://lore.kernel.org/lkml/[email protected]/
https://lore.kernel.org/lkml/[email protected]/
https://lore.kernel.org/lkml/[email protected]/
drivers/clk/qcom/gcc-sc8280xp.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c
index a18ed88f3b82..b3198784e1c3 100644
--- a/drivers/clk/qcom/gcc-sc8280xp.c
+++ b/drivers/clk/qcom/gcc-sc8280xp.c
@@ -5364,6 +5364,8 @@ static struct clk_branch gcc_ufs_1_card_clkref_clk = {
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_1_card_clkref_clk",
+ .parent_data = &gcc_parent_data_tcxo,
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@@ -5432,6 +5434,8 @@ static struct clk_branch gcc_ufs_card_clkref_clk = {
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_clkref_clk",
+ .parent_data = &gcc_parent_data_tcxo,
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@@ -5848,6 +5852,8 @@ static struct clk_branch gcc_ufs_ref_clkref_clk = {
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_ref_clkref_clk",
+ .parent_data = &gcc_parent_data_tcxo,
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
--
2.38.0
On Tue, Nov 15, 2022 at 08:59:56PM +0530, Shazad Hussain wrote:
> The three UFS reference clocks, gcc_ufs_ref_clkref_clk for external
> UFS devices, gcc_ufs_card_clkref_clk and gcc_ufs_1_card_clkref_clk for
> two PHYs are all sourced from CXO.
>
> Added parent_data for all three reference clocks described above to
> reflect that all three clocks are sourced from CXO to have valid
> frequency for the ref clock needed by UFS controller driver.
>
> Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver")
> Link: https://lore.kernel.org/lkml/Y2Tber39cHuOSR%[email protected]/
> Signed-off-by: Shazad Hussain <[email protected]>
> Tested-by: Johan Hovold <[email protected]>
> Reviewed-by: Johan Hovold <[email protected]>
> Tested-by: Andrew Halaney <[email protected]>
> Reviewed-by: Andrew Halaney <[email protected]>
> Reviewed-by: Reviewed-by: Brian Masney <[email protected]>
Really-really-reviewed-by? ;)
Reviewed-by: Bjorn Andersson <[email protected]>
@Stephen, could you please pick this for clk-fixes?
Thanks,
Bjorn
> ---
> Changes since v2:
> - Tweaked commit message and added R-b T-b from v2
>
> v2 of this patch can be found at
> https://lore.kernel.org/all/[email protected]/
>
> v1 of this patch can be found at
> https://lore.kernel.org/all/[email protected]/
>
> used below patches for verification on next-20221114
> https://lore.kernel.org/lkml/[email protected]/
> https://lore.kernel.org/lkml/[email protected]/
> https://lore.kernel.org/lkml/[email protected]/
>
> drivers/clk/qcom/gcc-sc8280xp.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c
> index a18ed88f3b82..b3198784e1c3 100644
> --- a/drivers/clk/qcom/gcc-sc8280xp.c
> +++ b/drivers/clk/qcom/gcc-sc8280xp.c
> @@ -5364,6 +5364,8 @@ static struct clk_branch gcc_ufs_1_card_clkref_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(const struct clk_init_data) {
> .name = "gcc_ufs_1_card_clkref_clk",
> + .parent_data = &gcc_parent_data_tcxo,
> + .num_parents = 1,
> .ops = &clk_branch2_ops,
> },
> },
> @@ -5432,6 +5434,8 @@ static struct clk_branch gcc_ufs_card_clkref_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(const struct clk_init_data) {
> .name = "gcc_ufs_card_clkref_clk",
> + .parent_data = &gcc_parent_data_tcxo,
> + .num_parents = 1,
> .ops = &clk_branch2_ops,
> },
> },
> @@ -5848,6 +5852,8 @@ static struct clk_branch gcc_ufs_ref_clkref_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(const struct clk_init_data) {
> .name = "gcc_ufs_ref_clkref_clk",
> + .parent_data = &gcc_parent_data_tcxo,
> + .num_parents = 1,
> .ops = &clk_branch2_ops,
> },
> },
> --
> 2.38.0
>
On 11/15/2022 10:43 PM, Bjorn Andersson wrote:
> On Tue, Nov 15, 2022 at 08:59:56PM +0530, Shazad Hussain wrote:
>> The three UFS reference clocks, gcc_ufs_ref_clkref_clk for external
>> UFS devices, gcc_ufs_card_clkref_clk and gcc_ufs_1_card_clkref_clk for
>> two PHYs are all sourced from CXO.
>>
>> Added parent_data for all three reference clocks described above to
>> reflect that all three clocks are sourced from CXO to have valid
>> frequency for the ref clock needed by UFS controller driver.
>>
>> Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver")
>> Link: https://lore.kernel.org/lkml/Y2Tber39cHuOSR%[email protected]/
>> Signed-off-by: Shazad Hussain <[email protected]>
>> Tested-by: Johan Hovold <[email protected]>
>> Reviewed-by: Johan Hovold <[email protected]>
>> Tested-by: Andrew Halaney <[email protected]>
>> Reviewed-by: Andrew Halaney <[email protected]>
>> Reviewed-by: Reviewed-by: Brian Masney <[email protected]>
>
> Really-really-reviewed-by? >
My bad, thanks for pointing it Bjorn :)
>
> Reviewed-by: Bjorn Andersson <[email protected]>
>
>
> @Stephen, could you please pick this for clk-fixes?
>
> Thanks,
> Bjorn
>
>> ---
>> Changes since v2:
>> - Tweaked commit message and added R-b T-b from v2
>>
>> v2 of this patch can be found at
>> https://lore.kernel.org/all/[email protected]/
>>
>> v1 of this patch can be found at
>> https://lore.kernel.org/all/[email protected]/
>>
>> used below patches for verification on next-20221114
>> https://lore.kernel.org/lkml/[email protected]/
>> https://lore.kernel.org/lkml/[email protected]/
>> https://lore.kernel.org/lkml/[email protected]/
>>
>> drivers/clk/qcom/gcc-sc8280xp.c | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c
>> index a18ed88f3b82..b3198784e1c3 100644
>> --- a/drivers/clk/qcom/gcc-sc8280xp.c
>> +++ b/drivers/clk/qcom/gcc-sc8280xp.c
>> @@ -5364,6 +5364,8 @@ static struct clk_branch gcc_ufs_1_card_clkref_clk = {
>> .enable_mask = BIT(0),
>> .hw.init = &(const struct clk_init_data) {
>> .name = "gcc_ufs_1_card_clkref_clk",
>> + .parent_data = &gcc_parent_data_tcxo,
>> + .num_parents = 1,
>> .ops = &clk_branch2_ops,
>> },
>> },
>> @@ -5432,6 +5434,8 @@ static struct clk_branch gcc_ufs_card_clkref_clk = {
>> .enable_mask = BIT(0),
>> .hw.init = &(const struct clk_init_data) {
>> .name = "gcc_ufs_card_clkref_clk",
>> + .parent_data = &gcc_parent_data_tcxo,
>> + .num_parents = 1,
>> .ops = &clk_branch2_ops,
>> },
>> },
>> @@ -5848,6 +5852,8 @@ static struct clk_branch gcc_ufs_ref_clkref_clk = {
>> .enable_mask = BIT(0),
>> .hw.init = &(const struct clk_init_data) {
>> .name = "gcc_ufs_ref_clkref_clk",
>> + .parent_data = &gcc_parent_data_tcxo,
>> + .num_parents = 1,
>> .ops = &clk_branch2_ops,
>> },
>> },
>> --
>> 2.38.0
>>
Quoting Shazad Hussain (2022-11-15 07:29:56)
> The three UFS reference clocks, gcc_ufs_ref_clkref_clk for external
> UFS devices, gcc_ufs_card_clkref_clk and gcc_ufs_1_card_clkref_clk for
> two PHYs are all sourced from CXO.
>
> Added parent_data for all three reference clocks described above to
> reflect that all three clocks are sourced from CXO to have valid
> frequency for the ref clock needed by UFS controller driver.
>
> Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver")
> Link: https://lore.kernel.org/lkml/Y2Tber39cHuOSR%[email protected]/
> Signed-off-by: Shazad Hussain <[email protected]>
> Tested-by: Johan Hovold <[email protected]>
> Reviewed-by: Johan Hovold <[email protected]>
> Tested-by: Andrew Halaney <[email protected]>
> Reviewed-by: Andrew Halaney <[email protected]>
> Reviewed-by: Reviewed-by: Brian Masney <[email protected]>
> ---
Fixed the double Rb
Applied to clk-fixes