The E6xx (TunnelCreek) CPUs have 9 GPIO lines in the resume well. Update
the resume functions to allow for more than 8 GPIO lines, using the core
functions as a template.
Cc: <[email protected]> # 3.4.x
Cc: <[email protected]> # 3.8.x
Cc: Grant Likely <[email protected]>
Cc: Linus Walleij <[email protected]>
Signed-off-by: Darren Hart <[email protected]>
---
drivers/gpio/gpio-sch.c | 37 +++++++++++++++++++++++++++----------
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/drivers/gpio/gpio-sch.c b/drivers/gpio/gpio-sch.c
index edae963..7e7b52b 100644
--- a/drivers/gpio/gpio-sch.c
+++ b/drivers/gpio/gpio-sch.c
@@ -125,13 +125,17 @@ static int sch_gpio_resume_direction_in(struct gpio_chip *gc,
unsigned gpio_num)
{
u8 curr_dirs;
+ unsigned short offset, bit;
spin_lock(&gpio_lock);
- curr_dirs = inb(gpio_ba + RGIO);
+ offset = RGIO + gpio_num / 8;
+ bit = gpio_num % 8;
+
+ curr_dirs = inb(gpio_ba + offset);
- if (!(curr_dirs & (1 << gpio_num)))
- outb(curr_dirs | (1 << gpio_num) , gpio_ba + RGIO);
+ if (!(curr_dirs & (1 << bit)))
+ outb(curr_dirs | (1 << bit), gpio_ba + offset);
spin_unlock(&gpio_lock);
return 0;
@@ -139,22 +143,31 @@ static int sch_gpio_resume_direction_in(struct gpio_chip *gc,
static int sch_gpio_resume_get(struct gpio_chip *gc, unsigned gpio_num)
{
- return !!(inb(gpio_ba + RGLV) & (1 << gpio_num));
+ unsigned short offset, bit;
+
+ offset = RGLV + gpio_num / 8;
+ bit = gpio_num % 8;
+
+ return !!(inb(gpio_ba + offset) & (1 << bit));
}
static void sch_gpio_resume_set(struct gpio_chip *gc,
unsigned gpio_num, int val)
{
u8 curr_vals;
+ unsigned short offset, bit;
spin_lock(&gpio_lock);
- curr_vals = inb(gpio_ba + RGLV);
+ offset = RGLV + gpio_num / 8;
+ bit = gpio_num % 8;
+
+ curr_vals = inb(gpio_ba + offset);
if (val)
- outb(curr_vals | (1 << gpio_num), gpio_ba + RGLV);
+ outb(curr_vals | (1 << bit), gpio_ba + offset);
else
- outb((curr_vals & ~(1 << gpio_num)), gpio_ba + RGLV);
+ outb((curr_vals & ~(1 << bit)), gpio_ba + offset);
spin_unlock(&gpio_lock);
}
@@ -163,14 +176,18 @@ static int sch_gpio_resume_direction_out(struct gpio_chip *gc,
unsigned gpio_num, int val)
{
u8 curr_dirs;
+ unsigned short offset, bit;
sch_gpio_resume_set(gc, gpio_num, val);
+ offset = RGIO + gpio_num / 8;
+ bit = gpio_num % 8;
+
spin_lock(&gpio_lock);
- curr_dirs = inb(gpio_ba + RGIO);
- if (curr_dirs & (1 << gpio_num))
- outb(curr_dirs & ~(1 << gpio_num), gpio_ba + RGIO);
+ curr_dirs = inb(gpio_ba + offset);
+ if (curr_dirs & (1 << bit))
+ outb(curr_dirs & ~(1 << bit), gpio_ba + offset);
spin_unlock(&gpio_lock);
return 0;
--
1.8.1.2
On Wed, Mar 6, 2013 at 10:49 PM, Darren Hart <[email protected]> wrote:
> The E6xx (TunnelCreek) CPUs have 9 GPIO lines in the resume well. Update
> the resume functions to allow for more than 8 GPIO lines, using the core
> functions as a template.
>
> Cc: <[email protected]> # 3.4.x
> Cc: <[email protected]> # 3.8.x
> Cc: Grant Likely <[email protected]>
> Cc: Linus Walleij <[email protected]>
> Signed-off-by: Darren Hart <[email protected]>
I have applied this for next (v3.10)
I cannot for my life figure out what kind of *regression* you are
fixing so that it should go into fixes for the -rc:s or the two stable
branches indicated above.
I need a more verbose commit message with descriptions of
user-percieved problems on deployed systems that for that.
BTW: are you interested in adding yourself as mainatiner of
this driver in the MAINTAINERS file Darren?
Yours,
Linus Walleij
On 03/27/2013 01:20 AM, Linus Walleij wrote:
> On Wed, Mar 6, 2013 at 10:49 PM, Darren Hart <[email protected]> wrote:
>
>> The E6xx (TunnelCreek) CPUs have 9 GPIO lines in the resume well. Update
>> the resume functions to allow for more than 8 GPIO lines, using the core
>> functions as a template.
>>
>> Cc: <[email protected]> # 3.4.x
>> Cc: <[email protected]> # 3.8.x
>> Cc: Grant Likely <[email protected]>
>> Cc: Linus Walleij <[email protected]>
>> Signed-off-by: Darren Hart <[email protected]>
>
> I have applied this for next (v3.10)
>
> I cannot for my life figure out what kind of *regression* you are
> fixing so that it should go into fixes for the -rc:s or the two stable
> branches indicated above.
I apologize. This is not a regression, it has always been broken for the
TunnelCreek (which was added later). With only 8 bits for the resume well,
trying to read the 9th GPIO line always fails. I suspect it was just never
tested or needed until a board came along using it. As adding support
for new
systems is acceptable for stable, I felt this landed in that bucket, as
well as
the "obvious bug fix" bucket.
> I need a more verbose commit message with descriptions of
> user-percieved problems on deployed systems that for that.
Would you like me to resubmit with a more verbose commit message? Happy
to do so.
> BTW: are you interested in adding yourself as mainatiner of
> this driver in the MAINTAINERS file Darren?
That might make sense. I'm doing a lot of TunnelCreek driver fixes for
the MinnowBoard. If that would be helpful, I'm willing.
Thanks,
--
Darren Hart
Intel Open Source Technology Center
Yocto Project - Technical Lead - Linux Kernel