Add platform support for EHRPWM and ECAP by providing clock nodes and
device tree nodes.
This series depends on [1] and [2] and is available for testing at [3]
[1] http://gitorious.org/linux-davinci/linux-davinci/trees/davinci-for-v3.9/dt-2
[2] https://gitorious.org/linux-pwm/linux-pwm/trees/for-next
[3] https://github.com/avinashphilip/am335x_linux/tree/davinci-for-v3.9_soc_pwm
Philip Avinash (3):
arm: davinci: clock node support for ECAP & EHRPWM
ARM: davinci: da850: Enable EHRPWM TBCLK from CFG_CHIP1
ARM: davinci: da850: add EHRPWM & ECAP DT node
arch/arm/boot/dts/da850.dtsi | 30 ++++++++++++++++++++++++++++
arch/arm/mach-davinci/da850.c | 24 ++++++++++++++++++++++
arch/arm/mach-davinci/da8xx-dt.c | 20 +++++++++++++++++++
arch/arm/mach-davinci/include/mach/da8xx.h | 1 +
4 files changed, 75 insertions(+)
--
1.7.9.5
Add da850 EHRPWM & ECAP DT node.
Also adds OF_DEV_AUXDATA for EHRPWM & ECAP driver to use EHRPWM & ECAP
clock.
Signed-off-by: Philip Avinash <[email protected]>
---
:100644 100644 3ec1bda... 9b5b613... M arch/arm/boot/dts/da850.dtsi
:100644 100644 72466ab... e32484c... M arch/arm/mach-davinci/da8xx-dt.c
arch/arm/boot/dts/da850.dtsi | 30 ++++++++++++++++++++++++++++++
arch/arm/mach-davinci/da8xx-dt.c | 5 +++++
2 files changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 3ec1bda..9b5b613 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -107,6 +107,36 @@
reg = <0x21000 0x1000>;
status = "disabled";
};
+ ehrpwm0: ehrpwm@01f00000 {
+ compatible = "ti,da850-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x300000 0x2000>;
+ status = "disabled";
+ };
+ ehrpwm1: ehrpwm@01f02000 {
+ compatible = "ti,da850-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x302000 0x2000>;
+ status = "disabled";
+ };
+ ecap0: ecap@01f06000 {
+ compatible = "ti,da850-ecap";
+ #pwm-cells = <3>;
+ reg = <0x306000 0x80>;
+ status = "disabled";
+ };
+ ecap1: ecap@01f07000 {
+ compatible = "ti,da850-ecap";
+ #pwm-cells = <3>;
+ reg = <0x307000 0x80>;
+ status = "disabled";
+ };
+ ecap2: ecap@01f08000 {
+ compatible = "ti,da850-ecap";
+ #pwm-cells = <3>;
+ reg = <0x308000 0x80>;
+ status = "disabled";
+ };
};
nand_cs3@62000000 {
compatible = "ti,davinci-nand";
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index 72466ab..e32484c 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -41,6 +41,11 @@ static void __init da8xx_init_irq(void)
struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("ti,davinci-i2c", 0x01c22000, "i2c_davinci.1", NULL),
OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "watchdog", NULL),
+ OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f00000, "ehrpwm", NULL),
+ OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f02000, "ehrpwm", NULL),
+ OF_DEV_AUXDATA("ti,da850-ecap", 0x01f06000, "ecap", NULL),
+ OF_DEV_AUXDATA("ti,da850-ecap", 0x01f07000, "ecap", NULL),
+ OF_DEV_AUXDATA("ti,da850-ecap", 0x01f08000, "ecap", NULL),
{}
};
--
1.7.9.5
da850 platforms require TBCLK synchronization in CFG_CHIP1 register for
TBCLK enable in EHRPWM modules. Enabling of TBCLK is done only if EHRPWM
DT node status is set to "okay" DT blob.
Also adds macro definitions for DA8XX_EHRPWM_TBCLKSYNC and
DA8XX_CFGCHIP1_REG.
Signed-off-by: Philip Avinash <[email protected]>
---
:100644 100644 6b7a0a2... 72466ab... M arch/arm/mach-davinci/da8xx-dt.c
:100644 100644 de439b7... be77ce2... M arch/arm/mach-davinci/include/mach/da8xx.h
arch/arm/mach-davinci/da8xx-dt.c | 15 +++++++++++++++
arch/arm/mach-davinci/include/mach/da8xx.h | 1 +
2 files changed, 16 insertions(+)
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index 6b7a0a2..72466ab 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -19,6 +19,7 @@
#include <mach/da8xx.h>
#define DA8XX_NUM_UARTS 3
+#define DA8XX_EHRPWM_TBCLKSYNC BIT(12)
void __init da8xx_uart_clk_enable(void)
{
@@ -47,10 +48,24 @@ struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
static void __init da850_init_machine(void)
{
+ struct device_node *ehrpwm_np;
+ const char *ehrpwm_compat = "ti,da850-ehrpwm";
+ void __iomem *cfg_chip1_base;
+
+ cfg_chip1_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG);
+
of_platform_populate(NULL, of_default_bus_match_table,
da850_auxdata_lookup, NULL);
da8xx_uart_clk_enable();
+
+ for_each_compatible_node(ehrpwm_np, NULL, ehrpwm_compat)
+ if (of_device_is_available(ehrpwm_np)) {
+ /* Enable TBCLK synchronization for EHRWPM modules */
+ writel(readl(cfg_chip1_base) | DA8XX_EHRPWM_TBCLKSYNC,
+ cfg_chip1_base);
+ break;
+ }
}
static const char *da850_boards_compat[] __initdata = {
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index de439b7..be77ce2 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -55,6 +55,7 @@ extern unsigned int da850_max_speed;
#define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x))
#define DA8XX_JTAG_ID_REG 0x18
#define DA8XX_CFGCHIP0_REG 0x17c
+#define DA8XX_CFGCHIP1_REG 0x180
#define DA8XX_CFGCHIP2_REG 0x184
#define DA8XX_CFGCHIP3_REG 0x188
--
1.7.9.5
Add clock node support for ECAP and EHRPWM modules.
Also adds dummy clock for EHRWPM TBCLK to comply with pwm-tiehrpwm
driver.
Signed-off-by: Philip Avinash <[email protected]>
---
:100644 100644 0c4a26d... 891d075... M arch/arm/mach-davinci/da850.c
arch/arm/mach-davinci/da850.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 0c4a26d..891d075 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -383,6 +383,27 @@ static struct clk dsp_clk = {
.flags = PSC_LRST | PSC_FORCE,
};
+static struct clk ehrpwm_clk = {
+ .name = "ehrpwm",
+ .parent = &pll0_sysclk2,
+ .lpsc = DA8XX_LPSC1_PWM,
+ .gpsc = 1,
+ .flags = DA850_CLK_ASYNC3,
+};
+
+static struct clk ehrpwm_tbclk = {
+ .name = "ehrpwm_tbclk",
+ .parent = NULL,
+};
+
+static struct clk ecap_clk = {
+ .name = "ecap",
+ .parent = &pll0_sysclk2,
+ .lpsc = DA8XX_LPSC1_ECAP,
+ .gpsc = 1,
+ .flags = DA850_CLK_ASYNC3,
+};
+
static struct clk_lookup da850_clks[] = {
CLK(NULL, "ref", &ref_clk),
CLK(NULL, "pll0", &pll0_clk),
@@ -430,6 +451,9 @@ static struct clk_lookup da850_clks[] = {
CLK("vpif", NULL, &vpif_clk),
CLK("ahci", NULL, &sata_clk),
CLK("davinci-rproc.0", NULL, &dsp_clk),
+ CLK("ehrpwm", "fck", &ehrpwm_clk),
+ CLK("ehrpwm", "tbclk", &ehrpwm_tbclk),
+ CLK("ecap", "fck", &ecap_clk),
CLK(NULL, NULL, NULL),
};
--
1.7.9.5
On 3/14/2013 4:07 PM, Philip Avinash wrote:
> Add clock node support for ECAP and EHRPWM modules.
> Also adds dummy clock for EHRWPM TBCLK to comply with pwm-tiehrpwm
> driver.
This is not right. So the version of IP used on AM335x uses a TBCLK and
that's absent on the version used on DA850? If yes, the driver should
never request clock on DA850.
Thanks,
Sekhar
On 3/14/2013 4:07 PM, Philip Avinash wrote:
> da850 platforms require TBCLK synchronization in CFG_CHIP1 register for
> TBCLK enable in EHRPWM modules. Enabling of TBCLK is done only if EHRPWM
> DT node status is set to "okay" DT blob.
> Also adds macro definitions for DA8XX_EHRPWM_TBCLKSYNC and
> DA8XX_CFGCHIP1_REG.
So there is actually a TBCLK in DA850 - it's just not modeled as a clock
similar to the way it is done on AM335x? If yes, then instead of adding
a dummy clock node and doing the TBCLK enable as part of init, why not
model TBCLK in clock tree even on DA850?
Thanks,
Sekhar
>>>>> "P" == Philip Avinash <[email protected]> writes:
P> Add da850 EHRPWM & ECAP DT node.
P> Also adds OF_DEV_AUXDATA for EHRPWM & ECAP driver to use EHRPWM & ECAP
P> clock.
P> Signed-off-by: Philip Avinash <[email protected]>
P> ---
P> :100644 100644 3ec1bda... 9b5b613... M arch/arm/boot/dts/da850.dtsi
P> :100644 100644 72466ab... e32484c... M arch/arm/mach-davinci/da8xx-dt.c
P> arch/arm/boot/dts/da850.dtsi | 30 ++++++++++++++++++++++++++++++
P> arch/arm/mach-davinci/da8xx-dt.c | 5 +++++
P> 2 files changed, 35 insertions(+)
P> diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
P> index 3ec1bda..9b5b613 100644
P> --- a/arch/arm/boot/dts/da850.dtsi
P> +++ b/arch/arm/boot/dts/da850.dtsi
P> @@ -107,6 +107,36 @@
P> reg = <0x21000 0x1000>;
P> status = "disabled";
P> };
P> + ehrpwm0: ehrpwm@01f00000 {
P> + compatible = "ti,da850-ehrpwm";
This should be:
compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
P> + ecap0: ecap@01f06000 {
P> + compatible = "ti,da850-ecap";
And:
compatible = "ti,da850-ecap", "ti,am33xx-ecap";
--
Bye, Peter Korsgaard
On Thu, Mar 14, 2013 at 18:31:52, Nori, Sekhar wrote:
> On 3/14/2013 4:07 PM, Philip Avinash wrote:
> > da850 platforms require TBCLK synchronization in CFG_CHIP1 register for
> > TBCLK enable in EHRPWM modules. Enabling of TBCLK is done only if EHRPWM
> > DT node status is set to "okay" DT blob.
> > Also adds macro definitions for DA8XX_EHRPWM_TBCLKSYNC and
> > DA8XX_CFGCHIP1_REG.
>
> So there is actually a TBCLK in DA850 - it's just not modeled as a clock
> similar to the way it is done on AM335x? If yes, then instead of adding
> a dummy clock node and doing the TBCLK enable as part of init, why not
> model TBCLK in clock tree even on DA850?
TBCLK enabling should done from platform specific way. In DA850 it is done at
CFGCHIP1 register. Unfortunately Davinci clock frame work will support only
clock nodes inside PLLC and PSC modules. Handling of CFGCHP1 require
modifications in clock frame work.
Hence handling it as part of initialization.
Thanks
Avinash
>
> Thanks,
> Sekhar
>
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On 3/15/2013 10:27 AM, Philip, Avinash wrote:
> On Thu, Mar 14, 2013 at 18:31:52, Nori, Sekhar wrote:
>> On 3/14/2013 4:07 PM, Philip Avinash wrote:
>>> da850 platforms require TBCLK synchronization in CFG_CHIP1 register for
>>> TBCLK enable in EHRPWM modules. Enabling of TBCLK is done only if EHRPWM
>>> DT node status is set to "okay" DT blob.
>>> Also adds macro definitions for DA8XX_EHRPWM_TBCLKSYNC and
>>> DA8XX_CFGCHIP1_REG.
>>
>> So there is actually a TBCLK in DA850 - it's just not modeled as a clock
>> similar to the way it is done on AM335x? If yes, then instead of adding
>> a dummy clock node and doing the TBCLK enable as part of init, why not
>> model TBCLK in clock tree even on DA850?
>
>
> TBCLK enabling should done from platform specific way. In DA850 it is done at
> CFGCHIP1 register. Unfortunately Davinci clock frame work will support only
> clock nodes inside PLLC and PSC modules. Handling of CFGCHP1 require
That's true at the moment, but that can be fixed.
> modifications in clock frame work.
>
> Hence handling it as part of initialization.
I am curious as to how this clock is handled in am335x. I searched for
tbclk in arch/arm/ of linux-next but could not find any references.
Where should I be looking?
Thanks,
Sekhar
On Fri, Mar 15, 2013 at 10:38:58, Nori, Sekhar wrote:
> On 3/15/2013 10:27 AM, Philip, Avinash wrote:
> > On Thu, Mar 14, 2013 at 18:31:52, Nori, Sekhar wrote:
> >> On 3/14/2013 4:07 PM, Philip Avinash wrote:
> >>> da850 platforms require TBCLK synchronization in CFG_CHIP1 register for
> >>> TBCLK enable in EHRPWM modules. Enabling of TBCLK is done only if EHRPWM
> >>> DT node status is set to "okay" DT blob.
> >>> Also adds macro definitions for DA8XX_EHRPWM_TBCLKSYNC and
> >>> DA8XX_CFGCHIP1_REG.
> >>
> >> So there is actually a TBCLK in DA850 - it's just not modeled as a clock
> >> similar to the way it is done on AM335x? If yes, then instead of adding
> >> a dummy clock node and doing the TBCLK enable as part of init, why not
> >> model TBCLK in clock tree even on DA850?
> >
> >
> > TBCLK enabling should done from platform specific way. In DA850 it is done at
> > CFGCHIP1 register. Unfortunately Davinci clock frame work will support only
> > clock nodes inside PLLC and PSC modules. Handling of CFGCHP1 require
>
> That's true at the moment, but that can be fixed.
I will check.
>
> > modifications in clock frame work.
> >
> > Hence handling it as part of initialization.
>
> I am curious as to how this clock is handled in am335x. I searched for
> tbclk in arch/arm/ of linux-next but could not find any references.
> Where should I be looking?
Patch is submitted. This patch is not in Paul's tree.
[PATCH v2] ARM: AM33XX: clk: Add clock node for EHRPWM TBCLK
https://patchwork.kernel.org/patch/2127581/
Paul,
Can you accept the above patch.
Thanks
Avinash
>
> Thanks,
> Sekhar
>
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On 3/15/2013 10:51 AM, Philip, Avinash wrote:
> On Fri, Mar 15, 2013 at 10:38:58, Nori, Sekhar wrote:
>> On 3/15/2013 10:27 AM, Philip, Avinash wrote:
>>> On Thu, Mar 14, 2013 at 18:31:52, Nori, Sekhar wrote:
>>>> On 3/14/2013 4:07 PM, Philip Avinash wrote:
>>>>> da850 platforms require TBCLK synchronization in CFG_CHIP1 register for
>>>>> TBCLK enable in EHRPWM modules. Enabling of TBCLK is done only if EHRPWM
>>>>> DT node status is set to "okay" DT blob.
>>>>> Also adds macro definitions for DA8XX_EHRPWM_TBCLKSYNC and
>>>>> DA8XX_CFGCHIP1_REG.
>>>>
>>>> So there is actually a TBCLK in DA850 - it's just not modeled as a clock
>>>> similar to the way it is done on AM335x? If yes, then instead of adding
>>>> a dummy clock node and doing the TBCLK enable as part of init, why not
>>>> model TBCLK in clock tree even on DA850?
>>>
>>>
>>> TBCLK enabling should done from platform specific way. In DA850 it is done at
>>> CFGCHIP1 register. Unfortunately Davinci clock frame work will support only
>>> clock nodes inside PLLC and PSC modules. Handling of CFGCHP1 require
>>
>> That's true at the moment, but that can be fixed.
>
> I will check.
For an example of non-PLL non-PSC clock on davinci, you can look at cdce
clock registration in board-dm646x-evm.c
>
>>
>>> modifications in clock frame work.
>>>
>>> Hence handling it as part of initialization.
>>
>> I am curious as to how this clock is handled in am335x. I searched for
>> tbclk in arch/arm/ of linux-next but could not find any references.
>> Where should I be looking?
>
> Patch is submitted. This patch is not in Paul's tree.
>
> [PATCH v2] ARM: AM33XX: clk: Add clock node for EHRPWM TBCLK
> https://patchwork.kernel.org/patch/2127581/
Thanks!
~Sekhar