2013-06-05 13:38:08

by Peter De Schrijver

Subject: [PATCH] clk: tegra: pllp_out2 divider is int only

The pllp_out2 should be integer only, the fractional bit should always be 0.

Signed-off-by: Peter De Schrijver <[email protected]>
---
drivers/clk/tegra/clk-tegra114.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index eb27764..5e029fe 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1203,8 +1203,8 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
/* PLLP_OUT2 */
clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
- TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
- &pll_div_lock);
+ TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24,
+ 8, 1, &pll_div_lock);
clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
clk_base + PLLP_OUTA, 17, 16,
CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
--
1.7.7.rc0.72.g4b5ea.dirty

2013-06-05 16:22:36

by Stephen Warren

Subject: Re: [PATCH] clk: tegra: pllp_out2 divider is int only

On 06/05/2013 07:37 AM, Peter De Schrijver wrote:
> The pllp_out2 should be integer only, the fractional bit should always be 0.

Tested-by: Stephen Warren <[email protected]>
Acked-by: Stephen Warren <[email protected]>

2013-06-12 00:26:29

by Mike Turquette

Subject: Re: [PATCH] clk: tegra: pllp_out2 divider is int only

Quoting Peter De Schrijver (2013-06-05 06:37:17)
> The pllp_out2 should be integer only, the fractional bit should always be 0.
>
> Signed-off-by: Peter De Schrijver <[email protected]>

Taken into clk-next.

Thanks,
Mike

> ---
> drivers/clk/tegra/clk-tegra114.c | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> index eb27764..5e029fe 100644
> --- a/drivers/clk/tegra/clk-tegra114.c
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -1203,8 +1203,8 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
> /* PLLP_OUT2 */
> clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
> clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
> - TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
> - &pll_div_lock);
> + TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24,
> + 8, 1, &pll_div_lock);
> clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
> clk_base + PLLP_OUTA, 17, 16,
> CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
> --
> 1.7.7.rc0.72.g4b5ea.dirty